[people/ms/u-boot.git] / board / xilinx / zynqmp / zynqmp.c

/*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
 * Michal Simek <michal.simek@xilinx.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <netdev.h>
#include <ahci.h>
#include <scsi.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <usb.h>
#include <dwc3-uboot.h>

DECLARE_GLOBAL_DATA_PTR;

int board_init(void)
{
	printf("EL Level:\tEL%d\n", current_el());

	return 0;
}

int board_early_init_r(void)
{
	u32 val;

	val = readl(&crlapb_base->timestamp_ref_ctrl);
	val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
	writel(val, &crlapb_base->timestamp_ref_ctrl);

	/* Program freq register in System counter and enable system counter */
	writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
	       ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
	       &iou_scntr->counter_control_register);

	return 0;
}

int dram_init(void)
{
	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;

	return 0;
}

int timer_init(void)
{
	return 0;
}

void reset_cpu(ulong addr)
{
}

#ifdef CONFIG_SCSI_AHCI_PLAT
void scsi_init(void)
{
	ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
	scsi_scan(1);
}
#endif

#ifdef CONFIG_CMD_MMC
int board_mmc_init(bd_t *bd)
{
	int ret = 0;

	u32 ver = zynqmp_get_silicon_version();

	if (ver != ZYNQMP_CSU_VERSION_VELOCE) {
#if defined(CONFIG_ZYNQ_SDHCI)
# if defined(CONFIG_ZYNQ_SDHCI0)
		ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
# endif
# if defined(CONFIG_ZYNQ_SDHCI1)
		ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
# endif
#endif
	}

	return ret;
}
#endif

int board_late_init(void)
{
	u32 reg = 0;
	u8 bootmode;

	reg = readl(&crlapb_base->boot_mode);
	bootmode = reg & BOOT_MODES_MASK;

	switch (bootmode) {
	case SD_MODE:
	case EMMC_MODE:
		setenv("modeboot", "sdboot");
		break;
	default:
		printf("Invalid Boot Mode:0x%x\n", bootmode);
		break;
	}

	return 0;
}

int checkboard(void)
{
	puts("Board:\tXilinx ZynqMP\n");
	return 0;
}

#ifdef CONFIG_USB_DWC3
static struct dwc3_device dwc3_device_data = {
	.maximum_speed = USB_SPEED_HIGH,
	.base = ZYNQMP_USB0_XHCI_BASEADDR,
	.dr_mode = USB_DR_MODE_PERIPHERAL,
	.index = 0,
};

int usb_gadget_handle_interrupts(void)
{
	dwc3_uboot_handle_interrupt(0);
	return 0;
}

int board_usb_init(int index, enum usb_init_type init)
{
	return dwc3_uboot_init(&dwc3_device_data);
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	dwc3_uboot_exit(index);
	return 0;
}
#endif
Commit	Line	Data
84c7204b MS	1	/*
	2	* (C) Copyright 2014 - 2015 Xilinx, Inc.
	3	* Michal Simek <michal.simek@xilinx.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <netdev.h>
6fe6f135 MS	10	#include <ahci.h>
6fe6f135 MS	11	#include <scsi.h>
84c7204b MS	12	#include <asm/arch/hardware.h>
	13	#include <asm/arch/sys_proto.h>
	14	#include <asm/io.h>
16fa00a7 SDPP	15	#include <usb.h>
16fa00a7 SDPP	16	#include <dwc3-uboot.h>
84c7204b MS	17
	18	DECLARE_GLOBAL_DATA_PTR;
	19
	20	int board_init(void)
	21	{
a0736efb MS	22	printf("EL Level:\tEL%d\n", current_el());
a0736efb MS	23
84c7204b MS	24	return 0;
	25	}
	26
	27	int board_early_init_r(void)
	28	{
	29	u32 val;
	30
	31	val = readl(&crlapb_base->timestamp_ref_ctrl);
	32	val \|= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
	33	writel(val, &crlapb_base->timestamp_ref_ctrl);
	34
	35	/* Program freq register in System counter and enable system counter */
	36	writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
	37	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG \|
	38	ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
	39	&iou_scntr->counter_control_register);
	40
	41	return 0;
	42	}
	43
	44	int dram_init(void)
	45	{
	46	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
	47
	48	return 0;
	49	}
	50
	51	int timer_init(void)
	52	{
	53	return 0;
	54	}
	55
	56	void reset_cpu(ulong addr)
	57	{
	58	}
	59
6fe6f135 MS	60	#ifdef CONFIG_SCSI_AHCI_PLAT
	61	void scsi_init(void)
	62	{
	63	ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
	64	scsi_scan(1);
	65	}
	66	#endif
	67
84c7204b MS	68	#ifdef CONFIG_CMD_MMC
	69	int board_mmc_init(bd_t *bd)
	70	{
	71	int ret = 0;
	72
16247d28 MS	73	u32 ver = zynqmp_get_silicon_version();
	74
	75	if (ver != ZYNQMP_CSU_VERSION_VELOCE) {
84c7204b MS	76	#if defined(CONFIG_ZYNQ_SDHCI)
84c7204b MS	77	# if defined(CONFIG_ZYNQ_SDHCI0)
16247d28	78	ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
84c7204b MS	79	# endif
84c7204b MS	80	# if defined(CONFIG_ZYNQ_SDHCI1)
16247d28	81	ret \|= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
84c7204b MS	82	# endif
84c7204b MS	83	#endif
16247d28	84	}
84c7204b MS	85
	86	return ret;
	87	}
	88	#endif
	89
	90	int board_late_init(void)
	91	{
	92	u32 reg = 0;
	93	u8 bootmode;
	94
	95	reg = readl(&crlapb_base->boot_mode);
	96	bootmode = reg & BOOT_MODES_MASK;
	97
	98	switch (bootmode) {
	99	case SD_MODE:
39c56f55	100	case EMMC_MODE:
84c7204b MS	101	setenv("modeboot", "sdboot");
	102	break;
	103	default:
	104	printf("Invalid Boot Mode:0x%x\n", bootmode);
	105	break;
	106	}
	107
	108	return 0;
	109	}
84696ff5 SDPP	110
	111	int checkboard(void)
	112	{
	113	puts("Board:\tXilinx ZynqMP\n");
	114	return 0;
	115	}
16fa00a7 SDPP	116
	117	#ifdef CONFIG_USB_DWC3
	118	static struct dwc3_device dwc3_device_data = {
	119	.maximum_speed = USB_SPEED_HIGH,
	120	.base = ZYNQMP_USB0_XHCI_BASEADDR,
	121	.dr_mode = USB_DR_MODE_PERIPHERAL,
	122	.index = 0,
	123	};
	124
	125	int usb_gadget_handle_interrupts(void)
	126	{
	127	dwc3_uboot_handle_interrupt(0);
	128	return 0;
	129	}
	130
	131	int board_usb_init(int index, enum usb_init_type init)
	132	{
	133	return dwc3_uboot_init(&dwc3_device_data);
	134	}
	135
	136	int board_usb_cleanup(int index, enum usb_init_type init)
	137	{
	138	dwc3_uboot_exit(index);
	139	return 0;
	140	}
	141	#endif