[people/ms/u-boot.git] / board / xilinx / zynqmp / zynqmp.c

/*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
 * Michal Simek <michal.simek@xilinx.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <sata.h>
#include <ahci.h>
#include <scsi.h>
#include <malloc.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <usb.h>
#include <dwc3-uboot.h>
#include <zynqmppl.h>
#include <i2c.h>
#include <g_dnl.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
    !defined(CONFIG_SPL_BUILD)
static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;

static const struct {
	u32 id;
	char *name;
} zynqmp_devices[] = {
	{
		.id = 0x10,
		.name = "3eg",
	},
	{
		.id = 0x11,
		.name = "2eg",
	},
	{
		.id = 0x20,
		.name = "5ev",
	},
	{
		.id = 0x21,
		.name = "4ev",
	},
	{
		.id = 0x30,
		.name = "7ev",
	},
	{
		.id = 0x38,
		.name = "9eg",
	},
	{
		.id = 0x39,
		.name = "6eg",
	},
	{
		.id = 0x40,
		.name = "11eg",
	},
	{
		.id = 0x50,
		.name = "15eg",
	},
	{
		.id = 0x58,
		.name = "19eg",
	},
	{
		.id = 0x59,
		.name = "17eg",
	},
};
#endif

int chip_id(unsigned char id)
{
	struct pt_regs regs;
	int val = -EINVAL;

	if (current_el() != 3) {
		regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
		regs.regs[1] = 0;
		regs.regs[2] = 0;
		regs.regs[3] = 0;

		smc_call(&regs);

		/*
		 * SMC returns:
		 * regs[0][31:0]  = status of the operation
		 * regs[0][63:32] = CSU.IDCODE register
		 * regs[1][31:0]  = CSU.version register
		 */
		switch (id) {
		case IDCODE:
			regs.regs[0] = upper_32_bits(regs.regs[0]);
			regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
					ZYNQMP_CSU_IDCODE_SVD_MASK;
			regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
			val = regs.regs[0];
			break;
		case VERSION:
			regs.regs[1] = lower_32_bits(regs.regs[1]);
			regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
			val = regs.regs[1];
			break;
		default:
			printf("%s, Invalid Req:0x%x\n", __func__, id);
		}
	} else {
		switch (id) {
		case IDCODE:
			val = readl(ZYNQMP_CSU_IDCODE_ADDR);
			val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
			       ZYNQMP_CSU_IDCODE_SVD_MASK;
			val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
			break;
		case VERSION:
			val = readl(ZYNQMP_CSU_VER_ADDR);
			val &= ZYNQMP_CSU_SILICON_VER_MASK;
			break;
		default:
			printf("%s, Invalid Req:0x%x\n", __func__, id);
		}
	}

	return val;
}

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	!defined(CONFIG_SPL_BUILD)
static char *zynqmp_get_silicon_idcode_name(void)
{
	u32 i, id;

	id = chip_id(IDCODE);
	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
		if (zynqmp_devices[i].id == id)
			return zynqmp_devices[i].name;
	}
	return "unknown";
}
#endif

int board_early_init_f(void)
{
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
	zynqmp_pmufw_version();
#endif

#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
	psu_init();
#endif

	return 0;
}

#define ZYNQMP_VERSION_SIZE	9

int board_init(void)
{
	printf("EL Level:\tEL%d\n", current_el());

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
    !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
    defined(CONFIG_SPL_BUILD))
	if (current_el() != 3) {
		static char version[ZYNQMP_VERSION_SIZE];

		strncat(version, "xczu", 4);
		zynqmppl.name = strncat(version,
					zynqmp_get_silicon_idcode_name(),
					ZYNQMP_VERSION_SIZE - 5);
		printf("Chip ID:\t%s\n", zynqmppl.name);
		fpga_init();
		fpga_add(fpga_xilinx, &zynqmppl);
	}
#endif

	return 0;
}

int board_early_init_r(void)
{
	u32 val;

	val = readl(&crlapb_base->timestamp_ref_ctrl);
	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;

	if (current_el() == 3 && !val) {
		val = readl(&crlapb_base->timestamp_ref_ctrl);
		val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
		writel(val, &crlapb_base->timestamp_ref_ctrl);

		/* Program freq register in System counter */
		writel(zynqmp_get_system_timer_freq(),
		       &iou_scntr_secure->base_frequency_id_register);
		/* And enable system counter */
		writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
		       &iou_scntr_secure->counter_control_register);
	}
	return 0;
}

int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
{
#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
    defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
    defined(CONFIG_ZYNQ_EEPROM_BUS)
	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);

	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
			CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
			ethaddr, 6))
		printf("I2C EEPROM MAC address read failed\n");
#endif

	return 0;
}

#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
int dram_init_banksize(void)
{
	return fdtdec_setup_memory_banksize();
}

int dram_init(void)
{
	if (fdtdec_setup_memory_size() != 0)
		return -EINVAL;

	return 0;
}
#else
int dram_init(void)
{
	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;

	return 0;
}
#endif

void reset_cpu(ulong addr)
{
}

int board_late_init(void)
{
	u32 reg = 0;
	u8 bootmode;
	const char *mode;
	char *new_targets;

	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
		debug("Saved variables - Skipping\n");
		return 0;
	}

	reg = readl(&crlapb_base->boot_mode);
	if (reg >> BOOT_MODE_ALT_SHIFT)
		reg >>= BOOT_MODE_ALT_SHIFT;

	bootmode = reg & BOOT_MODES_MASK;

	puts("Bootmode: ");
	switch (bootmode) {
	case USB_MODE:
		puts("USB_MODE\n");
		mode = "usb";
		break;
	case JTAG_MODE:
		puts("JTAG_MODE\n");
		mode = "pxe dhcp";
		break;
	case QSPI_MODE_24BIT:
	case QSPI_MODE_32BIT:
		mode = "qspi0";
		puts("QSPI_MODE\n");
		break;
	case EMMC_MODE:
		puts("EMMC_MODE\n");
		mode = "mmc0";
		break;
	case SD_MODE:
		puts("SD_MODE\n");
		mode = "mmc0";
		break;
	case SD1_LSHFT_MODE:
		puts("LVL_SHFT_");
		/* fall through */
	case SD_MODE1:
		puts("SD_MODE1\n");
#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
		mode = "mmc1";
#else
		mode = "mmc0";
#endif
		break;
	case NAND_MODE:
		puts("NAND_MODE\n");
		mode = "nand0";
		break;
	default:
		mode = "";
		printf("Invalid Boot Mode:0x%x\n", bootmode);
		break;
	}

	/*
	 * One terminating char + one byte for space between mode
	 * and default boot_targets
	 */
	new_targets = calloc(1, strlen(mode) +
				strlen(env_get("boot_targets")) + 2);

	sprintf(new_targets, "%s %s", mode, env_get("boot_targets"));
	env_set("boot_targets", new_targets);

	return 0;
}

int checkboard(void)
{
	puts("Board: Xilinx ZynqMP\n");
	return 0;
}

#ifdef CONFIG_USB_DWC3
static struct dwc3_device dwc3_device_data0 = {
	.maximum_speed = USB_SPEED_HIGH,
	.base = ZYNQMP_USB0_XHCI_BASEADDR,
	.dr_mode = USB_DR_MODE_PERIPHERAL,
	.index = 0,
};

static struct dwc3_device dwc3_device_data1 = {
	.maximum_speed = USB_SPEED_HIGH,
	.base = ZYNQMP_USB1_XHCI_BASEADDR,
	.dr_mode = USB_DR_MODE_PERIPHERAL,
	.index = 1,
};

int usb_gadget_handle_interrupts(int index)
{
	dwc3_uboot_handle_interrupt(index);
	return 0;
}

int board_usb_init(int index, enum usb_init_type init)
{
	debug("%s: index %x\n", __func__, index);

#if defined(CONFIG_USB_GADGET_DOWNLOAD)
	g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
#endif

	switch (index) {
	case 0:
		return dwc3_uboot_init(&dwc3_device_data0);
	case 1:
		return dwc3_uboot_init(&dwc3_device_data1);
	};

	return -1;
}

int board_usb_cleanup(int index, enum usb_init_type init)
{
	dwc3_uboot_exit(index);
	return 0;
}
#endif
Commit	Line	Data
84c7204b MS	1	/*
	2	* (C) Copyright 2014 - 2015 Xilinx, Inc.
	3	* Michal Simek <michal.simek@xilinx.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
679b994a	9	#include <sata.h>
6fe6f135 MS	10	#include <ahci.h>
6fe6f135 MS	11	#include <scsi.h>
b72894f1	12	#include <malloc.h>
0785dfd8	13	#include <asm/arch/clk.h>
84c7204b MS	14	#include <asm/arch/hardware.h>
	15	#include <asm/arch/sys_proto.h>
	16	#include <asm/io.h>
16fa00a7 SDPP	17	#include <usb.h>
16fa00a7 SDPP	18	#include <dwc3-uboot.h>
47e60cbd	19	#include <zynqmppl.h>
6919b4bf	20	#include <i2c.h>
9feff385	21	#include <g_dnl.h>
84c7204b MS	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
47e60cbd MS	25	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	26	!defined(CONFIG_SPL_BUILD)
	27	static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
	28
	29	static const struct {
8ebdf9ef	30	u32 id;
47e60cbd MS	31	char *name;
	32	} zynqmp_devices[] = {
	33	{
	34	.id = 0x10,
	35	.name = "3eg",
	36	},
	37	{
	38	.id = 0x11,
	39	.name = "2eg",
	40	},
	41	{
	42	.id = 0x20,
	43	.name = "5ev",
	44	},
	45	{
	46	.id = 0x21,
	47	.name = "4ev",
	48	},
	49	{
	50	.id = 0x30,
	51	.name = "7ev",
	52	},
	53	{
	54	.id = 0x38,
	55	.name = "9eg",
	56	},
	57	{
	58	.id = 0x39,
	59	.name = "6eg",
	60	},
	61	{
	62	.id = 0x40,
	63	.name = "11eg",
	64	},
	65	{
	66	.id = 0x50,
	67	.name = "15eg",
	68	},
	69	{
	70	.id = 0x58,
	71	.name = "19eg",
	72	},
	73	{
	74	.id = 0x59,
	75	.name = "17eg",
	76	},
	77	};
74ba69db	78	#endif
47e60cbd	79
f52bf5a3	80	int chip_id(unsigned char id)
47e60cbd MS	81	{
47e60cbd MS	82	struct pt_regs regs;
db3123b4	83	int val = -EINVAL;
47e60cbd	84
74ba69db SDPP	85	if (current_el() != 3) {
	86	regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
	87	regs.regs[1] = 0;
	88	regs.regs[2] = 0;
	89	regs.regs[3] = 0;
	90
	91	smc_call(&regs);
	92
	93	/*
	94	* SMC returns:
	95	* regs[0][31:0] = status of the operation
	96	* regs[0][63:32] = CSU.IDCODE register
	97	* regs[1][31:0] = CSU.version register
	98	*/
	99	switch (id) {
	100	case IDCODE:
	101	regs.regs[0] = upper_32_bits(regs.regs[0]);
	102	regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK \|
	103	ZYNQMP_CSU_IDCODE_SVD_MASK;
	104	regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
	105	val = regs.regs[0];
	106	break;
	107	case VERSION:
	108	regs.regs[1] = lower_32_bits(regs.regs[1]);
	109	regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
	110	val = regs.regs[1];
	111	break;
	112	default:
	113	printf("%s, Invalid Req:0x%x\n", __func__, id);
	114	}
	115	} else {
	116	switch (id) {
	117	case IDCODE:
	118	val = readl(ZYNQMP_CSU_IDCODE_ADDR);
	119	val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK \|
	120	ZYNQMP_CSU_IDCODE_SVD_MASK;
	121	val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
	122	break;
	123	case VERSION:
	124	val = readl(ZYNQMP_CSU_VER_ADDR);
	125	val &= ZYNQMP_CSU_SILICON_VER_MASK;
	126	break;
	127	default:
	128	printf("%s, Invalid Req:0x%x\n", __func__, id);
	129	}
db3123b4	130	}
0cba6abb	131
db3123b4	132	return val;
47e60cbd MS	133	}
47e60cbd MS	134
74ba69db SDPP	135	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
74ba69db SDPP	136	!defined(CONFIG_SPL_BUILD)
47e60cbd MS	137	static char *zynqmp_get_silicon_idcode_name(void)
47e60cbd MS	138	{
8ebdf9ef	139	u32 i, id;
47e60cbd	140
db3123b4	141	id = chip_id(IDCODE);
47e60cbd MS	142	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
	143	if (zynqmp_devices[i].id == id)
	144	return zynqmp_devices[i].name;
	145	}
	146	return "unknown";
	147	}
	148	#endif
	149
fb4000e8 MS	150	int board_early_init_f(void)
	151	{
	152	#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
	153	zynqmp_pmufw_version();
	154	#endif
55de0929	155
fd1b635c	156	#if defined(CONFIG_SPL_BUILD) \|\| defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
55de0929 MS	157	psu_init();
	158	#endif
	159
fb4000e8 MS	160	return 0;
	161	}
	162
47e60cbd MS	163	#define ZYNQMP_VERSION_SIZE 9
47e60cbd MS	164
84c7204b MS	165	int board_init(void)
84c7204b MS	166	{
a0736efb MS	167	printf("EL Level:\tEL%d\n", current_el());
a0736efb MS	168
47e60cbd MS	169	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
	170	!defined(CONFIG_SPL_BUILD) \|\| (defined(CONFIG_SPL_FPGA_SUPPORT) && \
	171	defined(CONFIG_SPL_BUILD))
	172	if (current_el() != 3) {
	173	static char version[ZYNQMP_VERSION_SIZE];
	174
df1cd46f	175	strncat(version, "xczu", 4);
47e60cbd MS	176	zynqmppl.name = strncat(version,
47e60cbd MS	177	zynqmp_get_silicon_idcode_name(),
df1cd46f	178	ZYNQMP_VERSION_SIZE - 5);
47e60cbd MS	179	printf("Chip ID:\t%s\n", zynqmppl.name);
	180	fpga_init();
	181	fpga_add(fpga_xilinx, &zynqmppl);
	182	}
	183	#endif
	184
84c7204b MS	185	return 0;
	186	}
	187
	188	int board_early_init_r(void)
	189	{
	190	u32 val;
	191
90a35db4 MS	192	val = readl(&crlapb_base->timestamp_ref_ctrl);
	193	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
	194
	195	if (current_el() == 3 && !val) {
0785dfd8 MS	196	val = readl(&crlapb_base->timestamp_ref_ctrl);
	197	val \|= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
	198	writel(val, &crlapb_base->timestamp_ref_ctrl);
84c7204b	199
0785dfd8 MS	200	/* Program freq register in System counter */
	201	writel(zynqmp_get_system_timer_freq(),
	202	&iou_scntr_secure->base_frequency_id_register);
	203	/* And enable system counter */
	204	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
	205	&iou_scntr_secure->counter_control_register);
	206	}
84c7204b MS	207	return 0;
	208	}
	209
6919b4bf MS	210	int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
	211	{
	212	#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
	213	defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
	214	defined(CONFIG_ZYNQ_EEPROM_BUS)
	215	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
	216
	217	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
	218	CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
	219	ethaddr, 6))
	220	printf("I2C EEPROM MAC address read failed\n");
	221	#endif
	222
	223	return 0;
	224	}
	225
8d59d7f6	226	#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
76b00aca	227	int dram_init_banksize(void)
361a8799	228	{
da3f003b	229	return fdtdec_setup_memory_banksize();
8a5db0ab	230	}
8d59d7f6	231
361a8799	232	int dram_init(void)
8a5db0ab	233	{
950f86ca NR	234	if (fdtdec_setup_memory_size() != 0)
950f86ca NR	235	return -EINVAL;
8a5db0ab	236
361a8799	237	return 0;
8d59d7f6 MS	238	}
8d59d7f6 MS	239	#else
84c7204b MS	240	int dram_init(void)
	241	{
	242	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
	243
	244	return 0;
	245	}
8d59d7f6	246	#endif
84c7204b	247
84c7204b MS	248	void reset_cpu(ulong addr)
	249	{
	250	}
	251
84c7204b MS	252	int board_late_init(void)
	253	{
	254	u32 reg = 0;
	255	u8 bootmode;
b72894f1 MS	256	const char *mode;
	257	char *new_targets;
	258
	259	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
	260	debug("Saved variables - Skipping\n");
	261	return 0;
	262	}
84c7204b MS	263
84c7204b MS	264	reg = readl(&crlapb_base->boot_mode);
47359a03 MS	265	if (reg >> BOOT_MODE_ALT_SHIFT)
	266	reg >>= BOOT_MODE_ALT_SHIFT;
	267
84c7204b MS	268	bootmode = reg & BOOT_MODES_MASK;
84c7204b MS	269
fb90917c	270	puts("Bootmode: ");
84c7204b	271	switch (bootmode) {
d58fc12e MS	272	case USB_MODE:
	273	puts("USB_MODE\n");
	274	mode = "usb";
	275	break;
0a5bcc8c	276	case JTAG_MODE:
fb90917c	277	puts("JTAG_MODE\n");
b72894f1	278	mode = "pxe dhcp";
0a5bcc8c SDPP	279	break;
	280	case QSPI_MODE_24BIT:
	281	case QSPI_MODE_32BIT:
b72894f1	282	mode = "qspi0";
fb90917c	283	puts("QSPI_MODE\n");
0a5bcc8c	284	break;
39c56f55	285	case EMMC_MODE:
78678fee	286	puts("EMMC_MODE\n");
b72894f1	287	mode = "mmc0";
78678fee MS	288	break;
78678fee MS	289	case SD_MODE:
fb90917c	290	puts("SD_MODE\n");
b72894f1	291	mode = "mmc0";
84c7204b	292	break;
e1992276 SDPP	293	case SD1_LSHFT_MODE:
	294	puts("LVL_SHFT_");
	295	/* fall through */
af813acd	296	case SD_MODE1:
fb90917c	297	puts("SD_MODE1\n");
2d9925bc	298	#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
b72894f1 MS	299	mode = "mmc1";
	300	#else
	301	mode = "mmc0";
2d9925bc	302	#endif
af813acd MS	303	break;
af813acd MS	304	case NAND_MODE:
fb90917c	305	puts("NAND_MODE\n");
b72894f1	306	mode = "nand0";
af813acd	307	break;
84c7204b	308	default:
b72894f1	309	mode = "";
84c7204b MS	310	printf("Invalid Boot Mode:0x%x\n", bootmode);
	311	break;
	312	}
	313
b72894f1 MS	314	/*
	315	* One terminating char + one byte for space between mode
	316	* and default boot_targets
	317	*/
	318	new_targets = calloc(1, strlen(mode) +
00caae6d	319	strlen(env_get("boot_targets")) + 2);
b72894f1	320
00caae6d	321	sprintf(new_targets, "%s %s", mode, env_get("boot_targets"));
382bee57	322	env_set("boot_targets", new_targets);
b72894f1	323
84c7204b MS	324	return 0;
84c7204b MS	325	}
84696ff5 SDPP	326
	327	int checkboard(void)
	328	{
5af08556	329	puts("Board: Xilinx ZynqMP\n");
84696ff5 SDPP	330	return 0;
84696ff5 SDPP	331	}
16fa00a7 SDPP	332
16fa00a7 SDPP	333	#ifdef CONFIG_USB_DWC3
275bd6d1	334	static struct dwc3_device dwc3_device_data0 = {
16fa00a7 SDPP	335	.maximum_speed = USB_SPEED_HIGH,
	336	.base = ZYNQMP_USB0_XHCI_BASEADDR,
	337	.dr_mode = USB_DR_MODE_PERIPHERAL,
	338	.index = 0,
	339	};
	340
275bd6d1 MS	341	static struct dwc3_device dwc3_device_data1 = {
	342	.maximum_speed = USB_SPEED_HIGH,
	343	.base = ZYNQMP_USB1_XHCI_BASEADDR,
	344	.dr_mode = USB_DR_MODE_PERIPHERAL,
	345	.index = 1,
	346	};
	347
9feff385	348	int usb_gadget_handle_interrupts(int index)
16fa00a7	349	{
9feff385	350	dwc3_uboot_handle_interrupt(index);
16fa00a7 SDPP	351	return 0;
	352	}
	353
	354	int board_usb_init(int index, enum usb_init_type init)
	355	{
275bd6d1 MS	356	debug("%s: index %x\n", __func__, index);
275bd6d1 MS	357
8ecd50c8 MS	358	#if defined(CONFIG_USB_GADGET_DOWNLOAD)
	359	g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
	360	#endif
	361
275bd6d1 MS	362	switch (index) {
	363	case 0:
	364	return dwc3_uboot_init(&dwc3_device_data0);
	365	case 1:
	366	return dwc3_uboot_init(&dwc3_device_data1);
	367	};
	368
	369	return -1;
16fa00a7 SDPP	370	}
	371
	372	int board_usb_cleanup(int index, enum usb_init_type init)
	373	{
	374	dwc3_uboot_exit(index);
	375	return 0;
	376	}
	377	#endif