projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 779e9751 SR |
1 | /* |
| 2 | * (C) Copyright 2007 | |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 4 | * | |
| 1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 779e9751 SR |
6 | */ |
| 7 | ||
| 8 | #include <config.h> | |
| 9 | #include <common.h> | |
| 10 | #include <command.h> | |
| 11 | #include <asm/processor.h> | |
| 12 | #include <asm/io.h> | |
| 09887762 | 13 | #include <asm/ppc4xx-gpio.h> |
| 779e9751 SR |
14 | #include <i2c.h> |
| 15 | ||
| 16 | #if defined(CONFIG_ZEUS) | |
| 17 | ||
| 18 | u8 buf_zeus_ce[] = { | |
| 19 | /*00 01 02 03 04 05 06 07 */ | |
| 20 | 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
| 21 | /*08 09 0a 0b 0c 0d 0e 0f */ | |
| 22 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
| 23 | /*10 11 12 13 14 15 16 17 */ | |
| 24 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
| 25 | /*18 19 1a 1b 1c 1d 1e 1f */ | |
| 26 | 0x00, 0xc0, 0x50, 0x12, 0x72, 0x3e, 0x00, 0x00 }; | |
| 27 | ||
| 28 | u8 buf_zeus_pe[] = { | |
| 29 | ||
| 30 | /* CPU_CLOCK_DIV 1 = 00 | |
| 31 | CPU_PLB_FREQ_DIV 3 = 10 | |
| 32 | OPB_PLB_FREQ_DIV 2 = 01 | |
| 33 | EBC_PLB_FREQ_DIV 2 = 00 | |
| 34 | MAL_PLB_FREQ_DIV 1 = 00 | |
| 35 | PCI_PLB_FRQ_DIV 3 = 10 | |
| 36 | PLL_PLLOUTA = IS SET | |
| 37 | PLL_OPERATING = IS NOT SET | |
| 38 | PLL_FDB_MUL 10 = 1010 | |
| 39 | PLL_FWD_DIV_A 3 = 101 | |
| 40 | PLL_FWD_DIV_B 3 = 101 | |
| 41 | TUNE = 0x2be */ | |
| 42 | /*00 01 02 03 04 05 06 07 */ | |
| 43 | 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
| 44 | /*08 09 0a 0b 0c 0d 0e 0f */ | |
| 45 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
| 46 | /*10 11 12 13 14 15 16 17 */ | |
| 47 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
| 48 | /*18 19 1a 1b 1c 1d 1e 1f */ | |
| 49 | 0x00, 0x60, 0x68, 0x2d, 0x42, 0xbe, 0x00, 0x00 }; | |
| 50 | ||
| 51 | static int update_boot_eeprom(void) | |
| 52 | { | |
| 53 | u32 len = 0x20; | |
| 6d0f6bcf | 54 | u8 chip = CONFIG_SYS_I2C_EEPROM_ADDR; |
| 779e9751 SR |
55 | u8 *pbuf; |
| 56 | u8 base; | |
| 57 | int i; | |
| 58 | ||
| 6d0f6bcf | 59 | if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_ZEUS_PE)) { |
| 779e9751 SR |
60 | pbuf = buf_zeus_pe; |
| 61 | base = 0x40; | |
| 62 | } else { | |
| 63 | pbuf = buf_zeus_ce; | |
| 64 | base = 0x00; | |
| 65 | } | |
| 66 | ||
| 67 | for (i = 0; i < len; i++, base++) { | |
| 68 | if (i2c_write(chip, base, 1, &pbuf[i], 1) != 0) { | |
| 69 | printf("i2c_write fail\n"); | |
| 70 | return 1; | |
| 71 | } | |
| 72 | udelay(11000); | |
| 73 | } | |
| 74 | ||
| 75 | return 0; | |
| 76 | } | |
| 77 | ||
| 54841ab5 | 78 | int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[]) |
| 779e9751 SR |
79 | { |
| 80 | return update_boot_eeprom(); | |
| 81 | } | |
| 82 | ||
| 83 | U_BOOT_CMD ( | |
| 84 | update_boot_eeprom, 1, 1, do_update_boot_eeprom, | |
| 2fb2604d | 85 | "update boot eeprom content", |
| a89c33db | 86 | "" |
| 779e9751 SR |
87 | ); |
| 88 | ||
| 89 | #endif |