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81a8824f 1/*
3f4978c7
HS
2 * (C) Copyright 2009
3 * Sergey Kubushyn, himself, ksi@koi8.net
4 *
5 * Changes for unified multibus/multiadapter I2C support.
6 *
81a8824f
WD
7 * (C) Copyright 2001
8 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
9 *
1a459660 10 * SPDX-License-Identifier: GPL-2.0+
81a8824f
WD
11 */
12
13/*
14 * I2C Functions similar to the standard memory functions.
15 *
16 * There are several parameters in many of the commands that bear further
17 * explanations:
18 *
81a8824f
WD
19 * {i2c_chip} is the I2C chip address (the first byte sent on the bus).
20 * Each I2C chip on the bus has a unique address. On the I2C data bus,
21 * the address is the upper seven bits and the LSB is the "read/write"
22 * bit. Note that the {i2c_chip} address specified on the command
23 * line is not shifted up: e.g. a typical EEPROM memory chip may have
24 * an I2C address of 0x50, but the data put on the bus will be 0xA0
25 * for write and 0xA1 for read. This "non shifted" address notation
26 * matches at least half of the data sheets :-/.
27 *
28 * {addr} is the address (or offset) within the chip. Small memory
29 * chips have 8 bit addresses. Large memory chips have 16 bit
30 * addresses. Other memory chips have 9, 10, or 11 bit addresses.
31 * Many non-memory chips have multiple registers and {addr} is used
32 * as the register index. Some non-memory chips have only one register
33 * and therefore don't need any {addr} parameter.
34 *
35 * The default {addr} parameter is one byte (.1) which works well for
36 * memories and registers with 8 bits of address space.
37 *
38 * You can specify the length of the {addr} field with the optional .0,
39 * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are
40 * manipulating a single register device which doesn't use an address
41 * field, use "0.0" for the address and the ".0" length field will
42 * suppress the address in the I2C data stream. This also works for
43 * successive reads using the I2C auto-incrementing memory pointer.
44 *
45 * If you are manipulating a large memory with 2-byte addresses, use
46 * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal).
47 *
48 * Then there are the unfortunate memory chips that spill the most
49 * significant 1, 2, or 3 bits of address into the chip address byte.
50 * This effectively makes one chip (logically) look like 2, 4, or
51 * 8 chips. This is handled (awkwardly) by #defining
6d0f6bcf 52 * CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
81a8824f
WD
53 * {addr} field (since .1 is the default, it doesn't actually have to
54 * be specified). Examples: given a memory chip at I2C chip address
55 * 0x50, the following would happen...
0f89c54b 56 * i2c md 50 0 10 display 16 bytes starting at 0x000
81a8824f 57 * On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd>
0f89c54b 58 * i2c md 50 100 10 display 16 bytes starting at 0x100
81a8824f 59 * On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd>
0f89c54b 60 * i2c md 50 210 10 display 16 bytes starting at 0x210
81a8824f
WD
61 * On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd>
62 * This is awfully ugly. It would be nice if someone would think up
63 * a better way of handling this.
64 *
65 * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de).
66 */
67
68#include <common.h>
0098e179 69#include <bootretry.h>
18d66533 70#include <cli.h>
81a8824f 71#include <command.h>
24b852a7 72#include <console.h>
63656b76 73#include <dm.h>
735987c5 74#include <edid.h>
67b23a32 75#include <environment.h>
63656b76 76#include <errno.h>
81a8824f 77#include <i2c.h>
67b23a32 78#include <malloc.h>
81a8824f 79#include <asm/byteorder.h>
2515d843 80#include <linux/compiler.h>
81a8824f 81
3f4978c7
HS
82DECLARE_GLOBAL_DATA_PTR;
83
81a8824f
WD
84/* Display values from last command.
85 * Memory modify remembered values are different from display memory.
86 */
5468461d 87static uint i2c_dp_last_chip;
81a8824f
WD
88static uint i2c_dp_last_addr;
89static uint i2c_dp_last_alen;
90static uint i2c_dp_last_length = 0x10;
91
5468461d 92static uint i2c_mm_last_chip;
81a8824f
WD
93static uint i2c_mm_last_addr;
94static uint i2c_mm_last_alen;
95
bb99ad6d
BW
96/* If only one I2C bus is present, the list of devices to ignore when
97 * the probe command is issued is represented by a 1D array of addresses.
98 * When multiple buses are present, the list is an array of bus-address
99 * pairs. The following macros take care of this */
100
6d0f6bcf 101#if defined(CONFIG_SYS_I2C_NOPROBES)
9a2accb4 102#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
bb99ad6d
BW
103static struct
104{
105 uchar bus;
106 uchar addr;
6d0f6bcf 107} i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
bb99ad6d
BW
108#define GET_BUS_NUM i2c_get_bus_num()
109#define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
110#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
111#define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
112#else /* single bus */
6d0f6bcf 113static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
bb99ad6d
BW
114#define GET_BUS_NUM 0
115#define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
116#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
117#define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
3f4978c7 118#endif /* defined(CONFIG_SYS_I2C) */
67b23a32
HS
119#endif
120
a266fe95
FM
121#define DISP_LINE_LEN 16
122
63656b76
SG
123/*
124 * Default for driver model is to use the chip's existing address length.
125 * For legacy code, this is not stored, so we need to use a suitable
126 * default.
127 */
128#ifdef CONFIG_DM_I2C
129#define DEFAULT_ADDR_LEN (-1)
130#else
131#define DEFAULT_ADDR_LEN 1
132#endif
133
134#ifdef CONFIG_DM_I2C
135static struct udevice *i2c_cur_bus;
136
f9a4c2da 137static int cmd_i2c_set_bus_num(unsigned int busnum)
63656b76
SG
138{
139 struct udevice *bus;
140 int ret;
141
142 ret = uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus);
143 if (ret) {
144 debug("%s: No bus %d\n", __func__, busnum);
145 return ret;
146 }
147 i2c_cur_bus = bus;
148
149 return 0;
150}
151
152static int i2c_get_cur_bus(struct udevice **busp)
153{
154 if (!i2c_cur_bus) {
155 puts("No I2C bus selected\n");
156 return -ENODEV;
157 }
158 *busp = i2c_cur_bus;
159
160 return 0;
161}
162
163static int i2c_get_cur_bus_chip(uint chip_addr, struct udevice **devp)
164{
165 struct udevice *bus;
166 int ret;
167
168 ret = i2c_get_cur_bus(&bus);
169 if (ret)
170 return ret;
171
25ab4b03 172 return i2c_get_chip(bus, chip_addr, 1, devp);
63656b76
SG
173}
174
175#endif
176
06afa388
MV
177/**
178 * i2c_init_board() - Board-specific I2C bus init
179 *
180 * This function is the default no-op implementation of I2C bus
181 * initialization. This function can be overriden by board-specific
182 * implementation if needed.
183 */
2515d843
MV
184__weak
185void i2c_init_board(void)
c649dda5 186{
c649dda5 187}
c649dda5 188
655b34a7 189/* TODO: Implement architecture-specific get/set functions */
06afa388
MV
190
191/**
192 * i2c_get_bus_speed() - Return I2C bus speed
193 *
194 * This function is the default implementation of function for retrieveing
195 * the current I2C bus speed in Hz.
196 *
197 * A driver implementing runtime switching of I2C bus speed must override
198 * this function to report the speed correctly. Simple or legacy drivers
199 * can use this fallback.
200 *
201 * Returns I2C bus speed in Hz.
202 */
63656b76 203#if !defined(CONFIG_SYS_I2C) && !defined(CONFIG_DM_I2C)
3f4978c7
HS
204/*
205 * TODO: Implement architecture-specific get/set functions
206 * Should go away, if we switched completely to new multibus support
207 */
2515d843
MV
208__weak
209unsigned int i2c_get_bus_speed(void)
655b34a7
PT
210{
211 return CONFIG_SYS_I2C_SPEED;
212}
655b34a7 213
06afa388
MV
214/**
215 * i2c_set_bus_speed() - Configure I2C bus speed
216 * @speed: Newly set speed of the I2C bus in Hz
217 *
218 * This function is the default implementation of function for setting
219 * the I2C bus speed in Hz.
220 *
221 * A driver implementing runtime switching of I2C bus speed must override
222 * this function to report the speed correctly. Simple or legacy drivers
223 * can use this fallback.
224 *
225 * Returns zero on success, negative value on error.
226 */
2515d843
MV
227__weak
228int i2c_set_bus_speed(unsigned int speed)
655b34a7
PT
229{
230 if (speed != CONFIG_SYS_I2C_SPEED)
231 return -1;
232
233 return 0;
234}
3f4978c7 235#endif
655b34a7 236
06afa388
MV
237/**
238 * get_alen() - Small parser helper function to get address length
239 *
240 * Returns the address length.
2c0dc990 241 */
63656b76 242static uint get_alen(char *arg, int default_len)
2c0dc990
FM
243{
244 int j;
245 int alen;
246
63656b76 247 alen = default_len;
2c0dc990
FM
248 for (j = 0; j < 8; j++) {
249 if (arg[j] == '.') {
250 alen = arg[j+1] - '0';
2c0dc990
FM
251 break;
252 } else if (arg[j] == '\0')
253 break;
254 }
255 return alen;
256}
257
c1a6f371
SG
258enum i2c_err_op {
259 I2C_ERR_READ,
260 I2C_ERR_WRITE,
261};
262
263static int i2c_report_err(int ret, enum i2c_err_op op)
264{
265 printf("Error %s the chip: %d\n",
266 op == I2C_ERR_READ ? "reading" : "writing", ret);
267
268 return CMD_RET_FAILURE;
269}
270
06afa388
MV
271/**
272 * do_i2c_read() - Handle the "i2c read" command-line command
273 * @cmdtp: Command data struct pointer
274 * @flag: Command flag
275 * @argc: Command-line argument count
276 * @argv: Array of command-line arguments
277 *
278 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
279 * on error.
280 *
652e5354
FM
281 * Syntax:
282 * i2c read {i2c_chip} {devaddr}{.0, .1, .2} {len} {memaddr}
283 */
54841ab5 284static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
652e5354 285{
5468461d 286 uint chip;
63656b76
SG
287 uint devaddr, length;
288 int alen;
652e5354 289 u_char *memaddr;
63656b76
SG
290 int ret;
291#ifdef CONFIG_DM_I2C
292 struct udevice *dev;
293#endif
652e5354 294
47e26b1b 295 if (argc != 5)
4c12eeb8 296 return CMD_RET_USAGE;
652e5354
FM
297
298 /*
299 * I2C chip address
300 */
301 chip = simple_strtoul(argv[1], NULL, 16);
302
303 /*
304 * I2C data address within the chip. This can be 1 or
305 * 2 bytes long. Some day it might be 3 bytes long :-).
306 */
307 devaddr = simple_strtoul(argv[2], NULL, 16);
63656b76 308 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 309 if (alen > 3)
4c12eeb8 310 return CMD_RET_USAGE;
652e5354
FM
311
312 /*
313 * Length is the number of objects, not number of bytes.
314 */
315 length = simple_strtoul(argv[3], NULL, 16);
316
317 /*
318 * memaddr is the address where to store things in memory
319 */
320 memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
321
63656b76
SG
322#ifdef CONFIG_DM_I2C
323 ret = i2c_get_cur_bus_chip(chip, &dev);
324 if (!ret && alen != -1)
325 ret = i2c_set_chip_offset_len(dev, alen);
326 if (!ret)
f9a4c2da 327 ret = dm_i2c_read(dev, devaddr, memaddr, length);
63656b76
SG
328#else
329 ret = i2c_read(chip, devaddr, alen, memaddr, length);
330#endif
331 if (ret)
332 return i2c_report_err(ret, I2C_ERR_READ);
333
652e5354
FM
334 return 0;
335}
336
ff5d2dce
YS
337static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
338{
5468461d 339 uint chip;
63656b76
SG
340 uint devaddr, length;
341 int alen;
ff5d2dce 342 u_char *memaddr;
63656b76
SG
343 int ret;
344#ifdef CONFIG_DM_I2C
345 struct udevice *dev;
ed16f146 346 struct dm_i2c_chip *i2c_chip;
63656b76 347#endif
ff5d2dce 348
ed16f146 349 if ((argc < 5) || (argc > 6))
ff5d2dce
YS
350 return cmd_usage(cmdtp);
351
352 /*
353 * memaddr is the address where to store things in memory
354 */
355 memaddr = (u_char *)simple_strtoul(argv[1], NULL, 16);
356
357 /*
358 * I2C chip address
359 */
360 chip = simple_strtoul(argv[2], NULL, 16);
361
362 /*
363 * I2C data address within the chip. This can be 1 or
364 * 2 bytes long. Some day it might be 3 bytes long :-).
365 */
366 devaddr = simple_strtoul(argv[3], NULL, 16);
63656b76 367 alen = get_alen(argv[3], DEFAULT_ADDR_LEN);
ff5d2dce
YS
368 if (alen > 3)
369 return cmd_usage(cmdtp);
370
371 /*
ed16f146 372 * Length is the number of bytes.
ff5d2dce
YS
373 */
374 length = simple_strtoul(argv[4], NULL, 16);
375
63656b76
SG
376#ifdef CONFIG_DM_I2C
377 ret = i2c_get_cur_bus_chip(chip, &dev);
378 if (!ret && alen != -1)
379 ret = i2c_set_chip_offset_len(dev, alen);
380 if (ret)
381 return i2c_report_err(ret, I2C_ERR_WRITE);
ed16f146
LP
382 i2c_chip = dev_get_parent_platdata(dev);
383 if (!i2c_chip)
384 return i2c_report_err(ret, I2C_ERR_WRITE);
63656b76
SG
385#endif
386
ed16f146
LP
387 if (argc == 6 && !strcmp(argv[5], "-s")) {
388 /*
389 * Write all bytes in a single I2C transaction. If the target
390 * device is an EEPROM, it is your responsibility to not cross
391 * a page boundary. No write delay upon completion, take this
392 * into account if linking commands.
393 */
63656b76 394#ifdef CONFIG_DM_I2C
ed16f146
LP
395 i2c_chip->flags &= ~DM_I2C_CHIP_WR_ADDRESS;
396 ret = dm_i2c_write(dev, devaddr, memaddr, length);
63656b76 397#else
ed16f146 398 ret = i2c_write(chip, devaddr, alen, memaddr, length);
63656b76
SG
399#endif
400 if (ret)
401 return i2c_report_err(ret, I2C_ERR_WRITE);
ed16f146
LP
402 } else {
403 /*
404 * Repeated addressing - perform <length> separate
405 * write transactions of one byte each
406 */
407 while (length-- > 0) {
408#ifdef CONFIG_DM_I2C
409 i2c_chip->flags |= DM_I2C_CHIP_WR_ADDRESS;
410 ret = dm_i2c_write(dev, devaddr++, memaddr++, 1);
411#else
412 ret = i2c_write(chip, devaddr++, alen, memaddr++, 1);
413#endif
414 if (ret)
415 return i2c_report_err(ret, I2C_ERR_WRITE);
ff5d2dce
YS
416/*
417 * No write delay with FRAM devices.
418 */
419#if !defined(CONFIG_SYS_I2C_FRAM)
ed16f146 420 udelay(11000);
ff5d2dce 421#endif
ed16f146 422 }
ff5d2dce
YS
423 }
424 return 0;
425}
426
63656b76
SG
427#ifdef CONFIG_DM_I2C
428static int do_i2c_flags(cmd_tbl_t *cmdtp, int flag, int argc,
429 char *const argv[])
430{
431 struct udevice *dev;
432 uint flags;
433 int chip;
434 int ret;
435
436 if (argc < 2)
437 return CMD_RET_USAGE;
438
439 chip = simple_strtoul(argv[1], NULL, 16);
440 ret = i2c_get_cur_bus_chip(chip, &dev);
441 if (ret)
442 return i2c_report_err(ret, I2C_ERR_READ);
443
444 if (argc > 2) {
445 flags = simple_strtoul(argv[2], NULL, 16);
446 ret = i2c_set_chip_flags(dev, flags);
447 } else {
448 ret = i2c_get_chip_flags(dev, &flags);
449 if (!ret)
450 printf("%x\n", flags);
451 }
452 if (ret)
453 return i2c_report_err(ret, I2C_ERR_READ);
454
455 return 0;
456}
c10c8e31
SG
457
458static int do_i2c_olen(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
459{
460 struct udevice *dev;
461 uint olen;
462 int chip;
463 int ret;
464
465 if (argc < 2)
466 return CMD_RET_USAGE;
467
468 chip = simple_strtoul(argv[1], NULL, 16);
469 ret = i2c_get_cur_bus_chip(chip, &dev);
470 if (ret)
471 return i2c_report_err(ret, I2C_ERR_READ);
472
473 if (argc > 2) {
474 olen = simple_strtoul(argv[2], NULL, 16);
475 ret = i2c_set_chip_offset_len(dev, olen);
476 } else {
477 ret = i2c_get_chip_offset_len(dev);
478 if (ret >= 0) {
479 printf("%x\n", ret);
480 ret = 0;
481 }
482 }
483 if (ret)
484 return i2c_report_err(ret, I2C_ERR_READ);
485
486 return 0;
487}
63656b76
SG
488#endif
489
06afa388
MV
490/**
491 * do_i2c_md() - Handle the "i2c md" command-line command
492 * @cmdtp: Command data struct pointer
493 * @flag: Command flag
494 * @argc: Command-line argument count
495 * @argv: Array of command-line arguments
496 *
497 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
498 * on error.
499 *
4a8cf338
FM
500 * Syntax:
501 * i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
502 */
54841ab5 503static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f 504{
5468461d 505 uint chip;
63656b76
SG
506 uint addr, length;
507 int alen;
81a8824f 508 int j, nbytes, linebytes;
63656b76
SG
509 int ret;
510#ifdef CONFIG_DM_I2C
511 struct udevice *dev;
512#endif
81a8824f
WD
513
514 /* We use the last specified parameters, unless new ones are
515 * entered.
516 */
517 chip = i2c_dp_last_chip;
518 addr = i2c_dp_last_addr;
519 alen = i2c_dp_last_alen;
520 length = i2c_dp_last_length;
521
47e26b1b 522 if (argc < 3)
4c12eeb8 523 return CMD_RET_USAGE;
81a8824f
WD
524
525 if ((flag & CMD_FLAG_REPEAT) == 0) {
526 /*
527 * New command specified.
528 */
81a8824f
WD
529
530 /*
531 * I2C chip address
532 */
533 chip = simple_strtoul(argv[1], NULL, 16);
534
535 /*
536 * I2C data address within the chip. This can be 1 or
537 * 2 bytes long. Some day it might be 3 bytes long :-).
538 */
539 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 540 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 541 if (alen > 3)
4c12eeb8 542 return CMD_RET_USAGE;
81a8824f
WD
543
544 /*
545 * If another parameter, it is the length to display.
546 * Length is the number of objects, not number of bytes.
547 */
548 if (argc > 3)
549 length = simple_strtoul(argv[3], NULL, 16);
550 }
551
63656b76
SG
552#ifdef CONFIG_DM_I2C
553 ret = i2c_get_cur_bus_chip(chip, &dev);
554 if (!ret && alen != -1)
555 ret = i2c_set_chip_offset_len(dev, alen);
556 if (ret)
557 return i2c_report_err(ret, I2C_ERR_READ);
558#endif
559
81a8824f
WD
560 /*
561 * Print the lines.
562 *
563 * We buffer all read data, so we can make sure data is read only
564 * once.
565 */
566 nbytes = length;
567 do {
568 unsigned char linebuf[DISP_LINE_LEN];
569 unsigned char *cp;
570
571 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
572
63656b76 573#ifdef CONFIG_DM_I2C
f9a4c2da 574 ret = dm_i2c_read(dev, addr, linebuf, linebytes);
63656b76
SG
575#else
576 ret = i2c_read(chip, addr, alen, linebuf, linebytes);
577#endif
578 if (ret)
9e533cb0 579 return i2c_report_err(ret, I2C_ERR_READ);
e857a5bd 580 else {
81a8824f
WD
581 printf("%04x:", addr);
582 cp = linebuf;
583 for (j=0; j<linebytes; j++) {
584 printf(" %02x", *cp++);
585 addr++;
586 }
4b9206ed 587 puts (" ");
81a8824f
WD
588 cp = linebuf;
589 for (j=0; j<linebytes; j++) {
590 if ((*cp < 0x20) || (*cp > 0x7e))
4b9206ed 591 puts (".");
81a8824f
WD
592 else
593 printf("%c", *cp);
594 cp++;
595 }
4b9206ed 596 putc ('\n');
81a8824f
WD
597 }
598 nbytes -= linebytes;
599 } while (nbytes > 0);
600
601 i2c_dp_last_chip = chip;
602 i2c_dp_last_addr = addr;
603 i2c_dp_last_alen = alen;
604 i2c_dp_last_length = length;
605
606 return 0;
607}
608
06afa388
MV
609/**
610 * do_i2c_mw() - Handle the "i2c mw" command-line command
611 * @cmdtp: Command data struct pointer
612 * @flag: Command flag
613 * @argc: Command-line argument count
614 * @argv: Array of command-line arguments
615 *
616 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
617 * on error.
81a8824f
WD
618 *
619 * Syntax:
0f89c54b 620 * i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
81a8824f 621 */
54841ab5 622static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f 623{
5468461d 624 uint chip;
81a8824f 625 ulong addr;
63656b76 626 int alen;
81a8824f
WD
627 uchar byte;
628 int count;
63656b76
SG
629 int ret;
630#ifdef CONFIG_DM_I2C
631 struct udevice *dev;
632#endif
81a8824f 633
47e26b1b 634 if ((argc < 4) || (argc > 5))
4c12eeb8 635 return CMD_RET_USAGE;
81a8824f
WD
636
637 /*
53677ef1
WD
638 * Chip is always specified.
639 */
81a8824f
WD
640 chip = simple_strtoul(argv[1], NULL, 16);
641
642 /*
643 * Address is always specified.
644 */
645 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 646 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 647 if (alen > 3)
4c12eeb8 648 return CMD_RET_USAGE;
81a8824f 649
63656b76
SG
650#ifdef CONFIG_DM_I2C
651 ret = i2c_get_cur_bus_chip(chip, &dev);
652 if (!ret && alen != -1)
653 ret = i2c_set_chip_offset_len(dev, alen);
654 if (ret)
655 return i2c_report_err(ret, I2C_ERR_WRITE);
656#endif
81a8824f
WD
657 /*
658 * Value to write is always specified.
659 */
660 byte = simple_strtoul(argv[3], NULL, 16);
661
662 /*
663 * Optional count
664 */
e857a5bd 665 if (argc == 5)
81a8824f 666 count = simple_strtoul(argv[4], NULL, 16);
e857a5bd 667 else
81a8824f 668 count = 1;
81a8824f
WD
669
670 while (count-- > 0) {
63656b76 671#ifdef CONFIG_DM_I2C
f9a4c2da 672 ret = dm_i2c_write(dev, addr++, &byte, 1);
63656b76
SG
673#else
674 ret = i2c_write(chip, addr++, alen, &byte, 1);
675#endif
676 if (ret)
9e533cb0 677 return i2c_report_err(ret, I2C_ERR_WRITE);
81a8824f
WD
678 /*
679 * Wait for the write to complete. The write can take
680 * up to 10mSec (we allow a little more time).
81a8824f 681 */
d4f5c728 682/*
683 * No write delay with FRAM devices.
684 */
6d0f6bcf 685#if !defined(CONFIG_SYS_I2C_FRAM)
81a8824f 686 udelay(11000);
d4f5c728 687#endif
81a8824f
WD
688 }
689
06afa388 690 return 0;
81a8824f
WD
691}
692
06afa388
MV
693/**
694 * do_i2c_crc() - Handle the "i2c crc32" command-line command
695 * @cmdtp: Command data struct pointer
696 * @flag: Command flag
697 * @argc: Command-line argument count
698 * @argv: Array of command-line arguments
699 *
700 * Calculate a CRC on memory
701 *
702 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
703 * on error.
81a8824f
WD
704 *
705 * Syntax:
0f89c54b 706 * i2c crc32 {i2c_chip} {addr}{.0, .1, .2} {count}
81a8824f 707 */
54841ab5 708static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f 709{
5468461d 710 uint chip;
81a8824f 711 ulong addr;
63656b76 712 int alen;
81a8824f
WD
713 int count;
714 uchar byte;
715 ulong crc;
716 ulong err;
63656b76
SG
717 int ret = 0;
718#ifdef CONFIG_DM_I2C
719 struct udevice *dev;
720#endif
81a8824f 721
47e26b1b 722 if (argc < 4)
4c12eeb8 723 return CMD_RET_USAGE;
81a8824f
WD
724
725 /*
53677ef1
WD
726 * Chip is always specified.
727 */
81a8824f
WD
728 chip = simple_strtoul(argv[1], NULL, 16);
729
730 /*
731 * Address is always specified.
732 */
733 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 734 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 735 if (alen > 3)
4c12eeb8 736 return CMD_RET_USAGE;
81a8824f 737
63656b76
SG
738#ifdef CONFIG_DM_I2C
739 ret = i2c_get_cur_bus_chip(chip, &dev);
740 if (!ret && alen != -1)
741 ret = i2c_set_chip_offset_len(dev, alen);
742 if (ret)
743 return i2c_report_err(ret, I2C_ERR_READ);
744#endif
81a8824f
WD
745 /*
746 * Count is always specified
747 */
748 count = simple_strtoul(argv[3], NULL, 16);
749
750 printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1);
751 /*
752 * CRC a byte at a time. This is going to be slooow, but hey, the
753 * memories are small and slow too so hopefully nobody notices.
754 */
755 crc = 0;
756 err = 0;
e857a5bd 757 while (count-- > 0) {
63656b76 758#ifdef CONFIG_DM_I2C
f9a4c2da 759 ret = dm_i2c_read(dev, addr, &byte, 1);
63656b76
SG
760#else
761 ret = i2c_read(chip, addr, alen, &byte, 1);
762#endif
763 if (ret)
81a8824f 764 err++;
81a8824f
WD
765 crc = crc32 (crc, &byte, 1);
766 addr++;
767 }
e857a5bd 768 if (err > 0)
63656b76 769 i2c_report_err(ret, I2C_ERR_READ);
e857a5bd 770 else
81a8824f 771 printf ("%08lx\n", crc);
81a8824f
WD
772
773 return 0;
774}
775
06afa388
MV
776/**
777 * mod_i2c_mem() - Handle the "i2c mm" and "i2c nm" command-line command
778 * @cmdtp: Command data struct pointer
779 * @flag: Command flag
780 * @argc: Command-line argument count
781 * @argv: Array of command-line arguments
782 *
783 * Modify memory.
784 *
785 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
786 * on error.
81a8824f
WD
787 *
788 * Syntax:
0f89c54b
PT
789 * i2c mm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
790 * i2c nm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
81a8824f 791 */
81a8824f 792static int
54841ab5 793mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
81a8824f 794{
5468461d 795 uint chip;
81a8824f 796 ulong addr;
63656b76 797 int alen;
81a8824f
WD
798 ulong data;
799 int size = 1;
800 int nbytes;
63656b76
SG
801 int ret;
802#ifdef CONFIG_DM_I2C
803 struct udevice *dev;
804#endif
81a8824f 805
47e26b1b 806 if (argc != 3)
4c12eeb8 807 return CMD_RET_USAGE;
81a8824f 808
b26440f1 809 bootretry_reset_cmd_timeout(); /* got a good command to get here */
81a8824f
WD
810 /*
811 * We use the last specified parameters, unless new ones are
812 * entered.
813 */
814 chip = i2c_mm_last_chip;
815 addr = i2c_mm_last_addr;
816 alen = i2c_mm_last_alen;
817
818 if ((flag & CMD_FLAG_REPEAT) == 0) {
819 /*
820 * New command specified. Check for a size specification.
821 * Defaults to byte if no or incorrect specification.
822 */
823 size = cmd_get_data_size(argv[0], 1);
824
825 /*
53677ef1
WD
826 * Chip is always specified.
827 */
81a8824f
WD
828 chip = simple_strtoul(argv[1], NULL, 16);
829
830 /*
831 * Address is always specified.
832 */
833 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 834 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 835 if (alen > 3)
4c12eeb8 836 return CMD_RET_USAGE;
81a8824f
WD
837 }
838
63656b76
SG
839#ifdef CONFIG_DM_I2C
840 ret = i2c_get_cur_bus_chip(chip, &dev);
841 if (!ret && alen != -1)
842 ret = i2c_set_chip_offset_len(dev, alen);
843 if (ret)
844 return i2c_report_err(ret, I2C_ERR_WRITE);
845#endif
846
81a8824f
WD
847 /*
848 * Print the address, followed by value. Then accept input for
849 * the next value. A non-converted value exits.
850 */
851 do {
852 printf("%08lx:", addr);
63656b76 853#ifdef CONFIG_DM_I2C
f9a4c2da 854 ret = dm_i2c_read(dev, addr, (uchar *)&data, size);
63656b76
SG
855#else
856 ret = i2c_read(chip, addr, alen, (uchar *)&data, size);
857#endif
858 if (ret)
9e533cb0
MY
859 return i2c_report_err(ret, I2C_ERR_READ);
860
861 data = cpu_to_be32(data);
862 if (size == 1)
863 printf(" %02lx", (data >> 24) & 0x000000FF);
864 else if (size == 2)
865 printf(" %04lx", (data >> 16) & 0x0000FFFF);
866 else
867 printf(" %08lx", data);
81a8824f 868
e1bf824d 869 nbytes = cli_readline(" ? ");
81a8824f
WD
870 if (nbytes == 0) {
871 /*
872 * <CR> pressed as only input, don't modify current
873 * location and move to next.
874 */
875 if (incrflag)
876 addr += size;
877 nbytes = size;
b26440f1
SG
878 /* good enough to not time out */
879 bootretry_reset_cmd_timeout();
81a8824f
WD
880 }
881#ifdef CONFIG_BOOT_RETRY_TIME
e857a5bd 882 else if (nbytes == -2)
81a8824f 883 break; /* timed out, exit the command */
81a8824f
WD
884#endif
885 else {
886 char *endp;
887
888 data = simple_strtoul(console_buffer, &endp, 16);
e857a5bd 889 if (size == 1)
81a8824f 890 data = data << 24;
e857a5bd 891 else if (size == 2)
81a8824f 892 data = data << 16;
81a8824f
WD
893 data = be32_to_cpu(data);
894 nbytes = endp - console_buffer;
895 if (nbytes) {
81a8824f
WD
896 /*
897 * good enough to not time out
898 */
b26440f1 899 bootretry_reset_cmd_timeout();
63656b76 900#ifdef CONFIG_DM_I2C
f9a4c2da
SG
901 ret = dm_i2c_write(dev, addr, (uchar *)&data,
902 size);
63656b76
SG
903#else
904 ret = i2c_write(chip, addr, alen,
905 (uchar *)&data, size);
906#endif
907 if (ret)
9e533cb0
MY
908 return i2c_report_err(ret,
909 I2C_ERR_WRITE);
6d0f6bcf
JCPV
910#ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
911 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
2535d602 912#endif
81a8824f
WD
913 if (incrflag)
914 addr += size;
915 }
916 }
917 } while (nbytes);
918
0800707b
PT
919 i2c_mm_last_chip = chip;
920 i2c_mm_last_addr = addr;
921 i2c_mm_last_alen = alen;
81a8824f
WD
922
923 return 0;
924}
925
06afa388
MV
926/**
927 * do_i2c_probe() - Handle the "i2c probe" command-line command
928 * @cmdtp: Command data struct pointer
929 * @flag: Command flag
930 * @argc: Command-line argument count
931 * @argv: Array of command-line arguments
932 *
933 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
934 * on error.
935 *
81a8824f 936 * Syntax:
54b99e51
EN
937 * i2c probe {addr}
938 *
939 * Returns zero (success) if one or more I2C devices was found
81a8824f 940 */
54841ab5 941static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f
WD
942{
943 int j;
54b99e51
EN
944 int addr = -1;
945 int found = 0;
6d0f6bcf 946#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 947 int k, skip;
3f4978c7 948 unsigned int bus = GET_BUS_NUM;
bb99ad6d 949#endif /* NOPROBES */
63656b76
SG
950 int ret;
951#ifdef CONFIG_DM_I2C
952 struct udevice *bus, *dev;
953
954 if (i2c_get_cur_bus(&bus))
955 return CMD_RET_FAILURE;
956#endif
81a8824f 957
54b99e51
EN
958 if (argc == 2)
959 addr = simple_strtol(argv[1], 0, 16);
960
4b9206ed 961 puts ("Valid chip addresses:");
e857a5bd 962 for (j = 0; j < 128; j++) {
54b99e51
EN
963 if ((0 <= addr) && (j != addr))
964 continue;
965
6d0f6bcf 966#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 967 skip = 0;
cfb25cc4 968 for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
e857a5bd 969 if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
81a8824f
WD
970 skip = 1;
971 break;
972 }
973 }
974 if (skip)
975 continue;
976#endif
63656b76 977#ifdef CONFIG_DM_I2C
f9a4c2da 978 ret = dm_i2c_probe(bus, j, 0, &dev);
63656b76
SG
979#else
980 ret = i2c_probe(j);
981#endif
982 if (ret == 0) {
81a8824f 983 printf(" %02X", j);
54b99e51
EN
984 found++;
985 }
81a8824f 986 }
4b9206ed 987 putc ('\n');
81a8824f 988
6d0f6bcf 989#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 990 puts ("Excluded chip addresses:");
cfb25cc4 991 for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) {
e857a5bd 992 if (COMPARE_BUS(bus,k))
bb99ad6d
BW
993 printf(" %02X", NO_PROBE_ADDR(k));
994 }
4b9206ed 995 putc ('\n');
81a8824f
WD
996#endif
997
54b99e51 998 return (0 == found);
81a8824f
WD
999}
1000
06afa388
MV
1001/**
1002 * do_i2c_loop() - Handle the "i2c loop" command-line command
1003 * @cmdtp: Command data struct pointer
1004 * @flag: Command flag
1005 * @argc: Command-line argument count
1006 * @argv: Array of command-line arguments
1007 *
1008 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1009 * on error.
1010 *
81a8824f 1011 * Syntax:
0f89c54b 1012 * i2c loop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
81a8824f
WD
1013 * {length} - Number of bytes to read
1014 * {delay} - A DECIMAL number and defaults to 1000 uSec
1015 */
54841ab5 1016static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f 1017{
5468461d 1018 uint chip;
63656b76 1019 int alen;
81a8824f
WD
1020 uint addr;
1021 uint length;
1022 u_char bytes[16];
1023 int delay;
63656b76
SG
1024 int ret;
1025#ifdef CONFIG_DM_I2C
1026 struct udevice *dev;
1027#endif
81a8824f 1028
47e26b1b 1029 if (argc < 3)
4c12eeb8 1030 return CMD_RET_USAGE;
81a8824f
WD
1031
1032 /*
1033 * Chip is always specified.
1034 */
1035 chip = simple_strtoul(argv[1], NULL, 16);
1036
1037 /*
1038 * Address is always specified.
1039 */
1040 addr = simple_strtoul(argv[2], NULL, 16);
63656b76 1041 alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
7a92e53c 1042 if (alen > 3)
4c12eeb8 1043 return CMD_RET_USAGE;
63656b76
SG
1044#ifdef CONFIG_DM_I2C
1045 ret = i2c_get_cur_bus_chip(chip, &dev);
1046 if (!ret && alen != -1)
1047 ret = i2c_set_chip_offset_len(dev, alen);
1048 if (ret)
1049 return i2c_report_err(ret, I2C_ERR_WRITE);
1050#endif
81a8824f
WD
1051
1052 /*
1053 * Length is the number of objects, not number of bytes.
1054 */
1055 length = 1;
1056 length = simple_strtoul(argv[3], NULL, 16);
e857a5bd 1057 if (length > sizeof(bytes))
81a8824f 1058 length = sizeof(bytes);
81a8824f
WD
1059
1060 /*
1061 * The delay time (uSec) is optional.
1062 */
1063 delay = 1000;
e857a5bd 1064 if (argc > 3)
81a8824f 1065 delay = simple_strtoul(argv[4], NULL, 10);
81a8824f
WD
1066 /*
1067 * Run the loop...
1068 */
e857a5bd 1069 while (1) {
63656b76 1070#ifdef CONFIG_DM_I2C
f9a4c2da 1071 ret = dm_i2c_read(dev, addr, bytes, length);
63656b76
SG
1072#else
1073 ret = i2c_read(chip, addr, alen, bytes, length);
1074#endif
1075 if (ret)
1076 i2c_report_err(ret, I2C_ERR_READ);
81a8824f
WD
1077 udelay(delay);
1078 }
1079
1080 /* NOTREACHED */
1081 return 0;
1082}
1083
81a8824f
WD
1084/*
1085 * The SDRAM command is separately configured because many
1086 * (most?) embedded boards don't use SDRAM DIMMs.
06afa388
MV
1087 *
1088 * FIXME: Document and probably move elsewhere!
81a8824f 1089 */
c76fe474 1090#if defined(CONFIG_CMD_SDRAM)
632de067
LJ
1091static void print_ddr2_tcyc (u_char const b)
1092{
1093 printf ("%d.", (b >> 4) & 0x0F);
1094 switch (b & 0x0F) {
1095 case 0x0:
1096 case 0x1:
1097 case 0x2:
1098 case 0x3:
1099 case 0x4:
1100 case 0x5:
1101 case 0x6:
1102 case 0x7:
1103 case 0x8:
1104 case 0x9:
1105 printf ("%d ns\n", b & 0x0F);
1106 break;
1107 case 0xA:
1108 puts ("25 ns\n");
1109 break;
1110 case 0xB:
1111 puts ("33 ns\n");
1112 break;
1113 case 0xC:
1114 puts ("66 ns\n");
1115 break;
1116 case 0xD:
1117 puts ("75 ns\n");
1118 break;
1119 default:
1120 puts ("?? ns\n");
1121 break;
1122 }
1123}
1124
1125static void decode_bits (u_char const b, char const *str[], int const do_once)
1126{
1127 u_char mask;
1128
1129 for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
1130 if (b & mask) {
1131 puts (*str);
1132 if (do_once)
1133 return;
1134 }
1135 }
1136}
81a8824f
WD
1137
1138/*
1139 * Syntax:
0f89c54b 1140 * i2c sdram {i2c_chip}
81a8824f 1141 */
54841ab5 1142static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
81a8824f 1143{
18c4e7f7 1144 enum { unknown, EDO, SDRAM, DDR, DDR2, DDR3, DDR4 } type;
632de067 1145
5468461d 1146 uint chip;
81a8824f
WD
1147 u_char data[128];
1148 u_char cksum;
1149 int j;
1150
632de067
LJ
1151 static const char *decode_CAS_DDR2[] = {
1152 " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
1153 };
1154
1155 static const char *decode_CAS_default[] = {
1156 " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
1157 };
1158
1159 static const char *decode_CS_WE_default[] = {
1160 " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
1161 };
1162
1163 static const char *decode_byte21_default[] = {
1164 " TBD (bit 7)\n",
1165 " Redundant row address\n",
1166 " Differential clock input\n",
1167 " Registerd DQMB inputs\n",
1168 " Buffered DQMB inputs\n",
1169 " On-card PLL\n",
1170 " Registered address/control lines\n",
1171 " Buffered address/control lines\n"
1172 };
1173
1174 static const char *decode_byte22_DDR2[] = {
1175 " TBD (bit 7)\n",
1176 " TBD (bit 6)\n",
1177 " TBD (bit 5)\n",
1178 " TBD (bit 4)\n",
1179 " TBD (bit 3)\n",
1180 " Supports partial array self refresh\n",
1181 " Supports 50 ohm ODT\n",
1182 " Supports weak driver\n"
1183 };
1184
1185 static const char *decode_row_density_DDR2[] = {
1186 "512 MiB", "256 MiB", "128 MiB", "16 GiB",
1187 "8 GiB", "4 GiB", "2 GiB", "1 GiB"
1188 };
1189
1190 static const char *decode_row_density_default[] = {
1191 "512 MiB", "256 MiB", "128 MiB", "64 MiB",
1192 "32 MiB", "16 MiB", "8 MiB", "4 MiB"
1193 };
1194
47e26b1b 1195 if (argc < 2)
4c12eeb8 1196 return CMD_RET_USAGE;
47e26b1b 1197
81a8824f
WD
1198 /*
1199 * Chip is always specified.
632de067
LJ
1200 */
1201 chip = simple_strtoul (argv[1], NULL, 16);
81a8824f 1202
632de067 1203 if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
4b9206ed 1204 puts ("No SDRAM Serial Presence Detect found.\n");
81a8824f
WD
1205 return 1;
1206 }
1207
1208 cksum = 0;
1209 for (j = 0; j < 63; j++) {
1210 cksum += data[j];
1211 }
e857a5bd 1212 if (cksum != data[63]) {
81a8824f 1213 printf ("WARNING: Configuration data checksum failure:\n"
632de067 1214 " is 0x%02x, calculated 0x%02x\n", data[63], cksum);
81a8824f 1215 }
632de067 1216 printf ("SPD data revision %d.%d\n",
81a8824f 1217 (data[62] >> 4) & 0x0F, data[62] & 0x0F);
632de067
LJ
1218 printf ("Bytes used 0x%02X\n", data[0]);
1219 printf ("Serial memory size 0x%02X\n", 1 << data[1]);
1220
4b9206ed 1221 puts ("Memory type ");
632de067 1222 switch (data[2]) {
0df6b844
LJ
1223 case 2:
1224 type = EDO;
1225 puts ("EDO\n");
1226 break;
1227 case 4:
1228 type = SDRAM;
1229 puts ("SDRAM\n");
1230 break;
18c4e7f7
MS
1231 case 7:
1232 type = DDR;
1233 puts("DDR\n");
1234 break;
0df6b844
LJ
1235 case 8:
1236 type = DDR2;
1237 puts ("DDR2\n");
1238 break;
18c4e7f7
MS
1239 case 11:
1240 type = DDR3;
1241 puts("DDR3\n");
1242 break;
1243 case 12:
1244 type = DDR4;
1245 puts("DDR4\n");
1246 break;
0df6b844
LJ
1247 default:
1248 type = unknown;
1249 puts ("unknown\n");
1250 break;
81a8824f 1251 }
632de067 1252
4b9206ed 1253 puts ("Row address bits ");
e857a5bd 1254 if ((data[3] & 0x00F0) == 0)
632de067 1255 printf ("%d\n", data[3] & 0x0F);
e857a5bd 1256 else
632de067
LJ
1257 printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
1258
4b9206ed 1259 puts ("Column address bits ");
e857a5bd 1260 if ((data[4] & 0x00F0) == 0)
632de067 1261 printf ("%d\n", data[4] & 0x0F);
e857a5bd 1262 else
632de067 1263 printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
0df6b844
LJ
1264
1265 switch (type) {
1266 case DDR2:
632de067
LJ
1267 printf ("Number of ranks %d\n",
1268 (data[5] & 0x07) + 1);
0df6b844
LJ
1269 break;
1270 default:
632de067 1271 printf ("Module rows %d\n", data[5]);
0df6b844
LJ
1272 break;
1273 }
1274
1275 switch (type) {
1276 case DDR2:
632de067 1277 printf ("Module data width %d bits\n", data[6]);
0df6b844
LJ
1278 break;
1279 default:
632de067
LJ
1280 printf ("Module data width %d bits\n",
1281 (data[7] << 8) | data[6]);
0df6b844
LJ
1282 break;
1283 }
1284
4b9206ed 1285 puts ("Interface signal levels ");
81a8824f 1286 switch(data[8]) {
0df6b844 1287 case 0: puts ("TTL 5.0 V\n"); break;
4b9206ed 1288 case 1: puts ("LVTTL\n"); break;
0df6b844
LJ
1289 case 2: puts ("HSTL 1.5 V\n"); break;
1290 case 3: puts ("SSTL 3.3 V\n"); break;
1291 case 4: puts ("SSTL 2.5 V\n"); break;
1292 case 5: puts ("SSTL 1.8 V\n"); break;
4b9206ed 1293 default: puts ("unknown\n"); break;
81a8824f 1294 }
0df6b844
LJ
1295
1296 switch (type) {
1297 case DDR2:
632de067
LJ
1298 printf ("SDRAM cycle time ");
1299 print_ddr2_tcyc (data[9]);
0df6b844
LJ
1300 break;
1301 default:
632de067
LJ
1302 printf ("SDRAM cycle time %d.%d ns\n",
1303 (data[9] >> 4) & 0x0F, data[9] & 0x0F);
0df6b844
LJ
1304 break;
1305 }
1306
1307 switch (type) {
1308 case DDR2:
632de067
LJ
1309 printf ("SDRAM access time 0.%d%d ns\n",
1310 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
0df6b844
LJ
1311 break;
1312 default:
632de067
LJ
1313 printf ("SDRAM access time %d.%d ns\n",
1314 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
0df6b844
LJ
1315 break;
1316 }
1317
4b9206ed 1318 puts ("EDC configuration ");
632de067 1319 switch (data[11]) {
4b9206ed
WD
1320 case 0: puts ("None\n"); break;
1321 case 1: puts ("Parity\n"); break;
1322 case 2: puts ("ECC\n"); break;
1323 default: puts ("unknown\n"); break;
81a8824f 1324 }
632de067 1325
e857a5bd 1326 if ((data[12] & 0x80) == 0)
4b9206ed 1327 puts ("No self refresh, rate ");
e857a5bd 1328 else
4b9206ed 1329 puts ("Self refresh, rate ");
632de067 1330
81a8824f 1331 switch(data[12] & 0x7F) {
632de067
LJ
1332 case 0: puts ("15.625 us\n"); break;
1333 case 1: puts ("3.9 us\n"); break;
1334 case 2: puts ("7.8 us\n"); break;
1335 case 3: puts ("31.3 us\n"); break;
1336 case 4: puts ("62.5 us\n"); break;
1337 case 5: puts ("125 us\n"); break;
4b9206ed 1338 default: puts ("unknown\n"); break;
81a8824f 1339 }
0df6b844
LJ
1340
1341 switch (type) {
1342 case DDR2:
632de067 1343 printf ("SDRAM width (primary) %d\n", data[13]);
0df6b844
LJ
1344 break;
1345 default:
632de067 1346 printf ("SDRAM width (primary) %d\n", data[13] & 0x7F);
0df6b844 1347 if ((data[13] & 0x80) != 0) {
632de067
LJ
1348 printf (" (second bank) %d\n",
1349 2 * (data[13] & 0x7F));
0df6b844
LJ
1350 }
1351 break;
1352 }
1353
1354 switch (type) {
1355 case DDR2:
1356 if (data[14] != 0)
632de067 1357 printf ("EDC width %d\n", data[14]);
0df6b844
LJ
1358 break;
1359 default:
1360 if (data[14] != 0) {
632de067
LJ
1361 printf ("EDC width %d\n",
1362 data[14] & 0x7F);
0df6b844
LJ
1363
1364 if ((data[14] & 0x80) != 0) {
632de067
LJ
1365 printf (" (second bank) %d\n",
1366 2 * (data[14] & 0x7F));
0df6b844
LJ
1367 }
1368 }
1369 break;
81a8824f 1370 }
0df6b844 1371
632de067
LJ
1372 if (DDR2 != type) {
1373 printf ("Min clock delay, back-to-back random column addresses "
1374 "%d\n", data[15]);
0df6b844
LJ
1375 }
1376
4b9206ed
WD
1377 puts ("Burst length(s) ");
1378 if (data[16] & 0x80) puts (" Page");
1379 if (data[16] & 0x08) puts (" 8");
1380 if (data[16] & 0x04) puts (" 4");
1381 if (data[16] & 0x02) puts (" 2");
1382 if (data[16] & 0x01) puts (" 1");
1383 putc ('\n');
632de067 1384 printf ("Number of banks %d\n", data[17]);
0df6b844
LJ
1385
1386 switch (type) {
1387 case DDR2:
1388 puts ("CAS latency(s) ");
632de067 1389 decode_bits (data[18], decode_CAS_DDR2, 0);
0df6b844
LJ
1390 putc ('\n');
1391 break;
1392 default:
1393 puts ("CAS latency(s) ");
632de067 1394 decode_bits (data[18], decode_CAS_default, 0);
0df6b844
LJ
1395 putc ('\n');
1396 break;
1397 }
1398
1399 if (DDR2 != type) {
1400 puts ("CS latency(s) ");
632de067 1401 decode_bits (data[19], decode_CS_WE_default, 0);
0df6b844
LJ
1402 putc ('\n');
1403 }
1404
1405 if (DDR2 != type) {
1406 puts ("WE latency(s) ");
632de067 1407 decode_bits (data[20], decode_CS_WE_default, 0);
0df6b844
LJ
1408 putc ('\n');
1409 }
1410
1411 switch (type) {
1412 case DDR2:
1413 puts ("Module attributes:\n");
1414 if (data[21] & 0x80)
1415 puts (" TBD (bit 7)\n");
1416 if (data[21] & 0x40)
1417 puts (" Analysis probe installed\n");
1418 if (data[21] & 0x20)
1419 puts (" TBD (bit 5)\n");
1420 if (data[21] & 0x10)
1421 puts (" FET switch external enable\n");
632de067 1422 printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
0df6b844 1423 if (data[20] & 0x11) {
632de067
LJ
1424 printf (" %d active registers on DIMM\n",
1425 (data[21] & 0x03) + 1);
0df6b844
LJ
1426 }
1427 break;
1428 default:
1429 puts ("Module attributes:\n");
1430 if (!data[21])
1431 puts (" (none)\n");
632de067
LJ
1432 else
1433 decode_bits (data[21], decode_byte21_default, 0);
0df6b844
LJ
1434 break;
1435 }
1436
1437 switch (type) {
1438 case DDR2:
632de067 1439 decode_bits (data[22], decode_byte22_DDR2, 0);
0df6b844
LJ
1440 break;
1441 default:
1442 puts ("Device attributes:\n");
1443 if (data[22] & 0x80) puts (" TBD (bit 7)\n");
1444 if (data[22] & 0x40) puts (" TBD (bit 6)\n");
1445 if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
1446 else puts (" Upper Vcc tolerance 10%\n");
1447 if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
1448 else puts (" Lower Vcc tolerance 10%\n");
1449 if (data[22] & 0x08) puts (" Supports write1/read burst\n");
1450 if (data[22] & 0x04) puts (" Supports precharge all\n");
1451 if (data[22] & 0x02) puts (" Supports auto precharge\n");
1452 if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
1453 break;
1454 }
1455
1456 switch (type) {
1457 case DDR2:
632de067
LJ
1458 printf ("SDRAM cycle time (2nd highest CAS latency) ");
1459 print_ddr2_tcyc (data[23]);
0df6b844
LJ
1460 break;
1461 default:
632de067
LJ
1462 printf ("SDRAM cycle time (2nd highest CAS latency) %d."
1463 "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
0df6b844
LJ
1464 break;
1465 }
1466
1467 switch (type) {
1468 case DDR2:
632de067
LJ
1469 printf ("SDRAM access from clock (2nd highest CAS latency) 0."
1470 "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
0df6b844
LJ
1471 break;
1472 default:
632de067
LJ
1473 printf ("SDRAM access from clock (2nd highest CAS latency) %d."
1474 "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
0df6b844
LJ
1475 break;
1476 }
1477
1478 switch (type) {
1479 case DDR2:
632de067
LJ
1480 printf ("SDRAM cycle time (3rd highest CAS latency) ");
1481 print_ddr2_tcyc (data[25]);
0df6b844
LJ
1482 break;
1483 default:
632de067
LJ
1484 printf ("SDRAM cycle time (3rd highest CAS latency) %d."
1485 "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
0df6b844
LJ
1486 break;
1487 }
1488
1489 switch (type) {
1490 case DDR2:
632de067
LJ
1491 printf ("SDRAM access from clock (3rd highest CAS latency) 0."
1492 "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
0df6b844
LJ
1493 break;
1494 default:
632de067
LJ
1495 printf ("SDRAM access from clock (3rd highest CAS latency) %d."
1496 "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
0df6b844
LJ
1497 break;
1498 }
1499
1500 switch (type) {
1501 case DDR2:
632de067
LJ
1502 printf ("Minimum row precharge %d.%02d ns\n",
1503 (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
0df6b844
LJ
1504 break;
1505 default:
632de067 1506 printf ("Minimum row precharge %d ns\n", data[27]);
0df6b844
LJ
1507 break;
1508 }
1509
1510 switch (type) {
1511 case DDR2:
632de067
LJ
1512 printf ("Row active to row active min %d.%02d ns\n",
1513 (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
0df6b844
LJ
1514 break;
1515 default:
632de067 1516 printf ("Row active to row active min %d ns\n", data[28]);
0df6b844
LJ
1517 break;
1518 }
1519
1520 switch (type) {
1521 case DDR2:
632de067
LJ
1522 printf ("RAS to CAS delay min %d.%02d ns\n",
1523 (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
0df6b844
LJ
1524 break;
1525 default:
632de067 1526 printf ("RAS to CAS delay min %d ns\n", data[29]);
0df6b844
LJ
1527 break;
1528 }
1529
632de067 1530 printf ("Minimum RAS pulse width %d ns\n", data[30]);
0df6b844
LJ
1531
1532 switch (type) {
1533 case DDR2:
632de067
LJ
1534 puts ("Density of each row ");
1535 decode_bits (data[31], decode_row_density_DDR2, 1);
1536 putc ('\n');
0df6b844
LJ
1537 break;
1538 default:
632de067
LJ
1539 puts ("Density of each row ");
1540 decode_bits (data[31], decode_row_density_default, 1);
1541 putc ('\n');
0df6b844
LJ
1542 break;
1543 }
1544
1545 switch (type) {
1546 case DDR2:
632de067 1547 puts ("Command and Address setup ");
0df6b844 1548 if (data[32] >= 0xA0) {
632de067
LJ
1549 printf ("1.%d%d ns\n",
1550 ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
0df6b844 1551 } else {
632de067
LJ
1552 printf ("0.%d%d ns\n",
1553 ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
0df6b844
LJ
1554 }
1555 break;
1556 default:
632de067
LJ
1557 printf ("Command and Address setup %c%d.%d ns\n",
1558 (data[32] & 0x80) ? '-' : '+',
1559 (data[32] >> 4) & 0x07, data[32] & 0x0F);
0df6b844
LJ
1560 break;
1561 }
1562
1563 switch (type) {
1564 case DDR2:
632de067 1565 puts ("Command and Address hold ");
0df6b844 1566 if (data[33] >= 0xA0) {
632de067
LJ
1567 printf ("1.%d%d ns\n",
1568 ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
0df6b844 1569 } else {
632de067
LJ
1570 printf ("0.%d%d ns\n",
1571 ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
0df6b844
LJ
1572 }
1573 break;
1574 default:
632de067
LJ
1575 printf ("Command and Address hold %c%d.%d ns\n",
1576 (data[33] & 0x80) ? '-' : '+',
1577 (data[33] >> 4) & 0x07, data[33] & 0x0F);
0df6b844
LJ
1578 break;
1579 }
1580
1581 switch (type) {
1582 case DDR2:
632de067
LJ
1583 printf ("Data signal input setup 0.%d%d ns\n",
1584 (data[34] >> 4) & 0x0F, data[34] & 0x0F);
0df6b844
LJ
1585 break;
1586 default:
632de067
LJ
1587 printf ("Data signal input setup %c%d.%d ns\n",
1588 (data[34] & 0x80) ? '-' : '+',
1589 (data[34] >> 4) & 0x07, data[34] & 0x0F);
0df6b844
LJ
1590 break;
1591 }
1592
1593 switch (type) {
1594 case DDR2:
632de067
LJ
1595 printf ("Data signal input hold 0.%d%d ns\n",
1596 (data[35] >> 4) & 0x0F, data[35] & 0x0F);
0df6b844
LJ
1597 break;
1598 default:
632de067
LJ
1599 printf ("Data signal input hold %c%d.%d ns\n",
1600 (data[35] & 0x80) ? '-' : '+',
1601 (data[35] >> 4) & 0x07, data[35] & 0x0F);
0df6b844
LJ
1602 break;
1603 }
1604
4b9206ed 1605 puts ("Manufacturer's JEDEC ID ");
e857a5bd 1606 for (j = 64; j <= 71; j++)
632de067 1607 printf ("%02X ", data[j]);
4b9206ed 1608 putc ('\n');
632de067 1609 printf ("Manufacturing Location %02X\n", data[72]);
4b9206ed 1610 puts ("Manufacturer's Part Number ");
e857a5bd 1611 for (j = 73; j <= 90; j++)
632de067 1612 printf ("%02X ", data[j]);
4b9206ed 1613 putc ('\n');
632de067
LJ
1614 printf ("Revision Code %02X %02X\n", data[91], data[92]);
1615 printf ("Manufacturing Date %02X %02X\n", data[93], data[94]);
4b9206ed 1616 puts ("Assembly Serial Number ");
e857a5bd 1617 for (j = 95; j <= 98; j++)
632de067 1618 printf ("%02X ", data[j]);
4b9206ed 1619 putc ('\n');
81a8824f 1620
0df6b844 1621 if (DDR2 != type) {
632de067
LJ
1622 printf ("Speed rating PC%d\n",
1623 data[126] == 0x66 ? 66 : data[126]);
0df6b844 1624 }
81a8824f
WD
1625 return 0;
1626}
90253178 1627#endif
81a8824f 1628
735987c5
TWHT
1629/*
1630 * Syntax:
1631 * i2c edid {i2c_chip}
1632 */
1633#if defined(CONFIG_I2C_EDID)
1634int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1635{
5468461d 1636 uint chip;
735987c5 1637 struct edid1_info edid;
63656b76
SG
1638 int ret;
1639#ifdef CONFIG_DM_I2C
1640 struct udevice *dev;
1641#endif
735987c5
TWHT
1642
1643 if (argc < 2) {
1644 cmd_usage(cmdtp);
1645 return 1;
1646 }
1647
1648 chip = simple_strtoul(argv[1], NULL, 16);
63656b76
SG
1649#ifdef CONFIG_DM_I2C
1650 ret = i2c_get_cur_bus_chip(chip, &dev);
1651 if (!ret)
f9a4c2da 1652 ret = dm_i2c_read(dev, 0, (uchar *)&edid, sizeof(edid));
63656b76
SG
1653#else
1654 ret = i2c_read(chip, 0, 1, (uchar *)&edid, sizeof(edid));
1655#endif
1656 if (ret)
1657 return i2c_report_err(ret, I2C_ERR_READ);
735987c5
TWHT
1658
1659 if (edid_check_info(&edid)) {
1660 puts("Content isn't valid EDID.\n");
1661 return 1;
1662 }
1663
1664 edid_print_info(&edid);
1665 return 0;
1666
1667}
1668#endif /* CONFIG_I2C_EDID */
1669
59aa9df3
SG
1670#ifdef CONFIG_DM_I2C
1671static void show_bus(struct udevice *bus)
1672{
1673 struct udevice *dev;
1674
1675 printf("Bus %d:\t%s", bus->req_seq, bus->name);
1676 if (device_active(bus))
1677 printf(" (active %d)", bus->seq);
1678 printf("\n");
1679 for (device_find_first_child(bus, &dev);
1680 dev;
1681 device_find_next_child(&dev)) {
1682 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
1683
1684 printf(" %02x: %s, offset len %x, flags %x\n",
1685 chip->chip_addr, dev->name, chip->offset_len,
1686 chip->flags);
1687 }
1688}
1689#endif
1690
06afa388 1691/**
3f4978c7 1692 * do_i2c_show_bus() - Handle the "i2c bus" command-line command
06afa388
MV
1693 * @cmdtp: Command data struct pointer
1694 * @flag: Command flag
1695 * @argc: Command-line argument count
1696 * @argv: Array of command-line arguments
1697 *
1698 * Returns zero always.
1699 */
59aa9df3 1700#if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C)
0e350f81
JH
1701static int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc,
1702 char * const argv[])
67b23a32 1703{
67b23a32
HS
1704 if (argc == 1) {
1705 /* show all busses */
59aa9df3
SG
1706#ifdef CONFIG_DM_I2C
1707 struct udevice *bus;
1708 struct uclass *uc;
1709 int ret;
1710
1711 ret = uclass_get(UCLASS_I2C, &uc);
1712 if (ret)
1713 return CMD_RET_FAILURE;
1714 uclass_foreach_dev(bus, uc)
1715 show_bus(bus);
1716#else
1717 int i;
1718
3f4978c7
HS
1719 for (i = 0; i < CONFIG_SYS_NUM_I2C_BUSES; i++) {
1720 printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
1721#ifndef CONFIG_SYS_I2C_DIRECT_BUS
59aa9df3
SG
1722 int j;
1723
3f4978c7
HS
1724 for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
1725 if (i2c_bus[i].next_hop[j].chip == 0)
1726 break;
1727 printf("->%s@0x%2x:%d",
1728 i2c_bus[i].next_hop[j].mux.name,
1729 i2c_bus[i].next_hop[j].chip,
1730 i2c_bus[i].next_hop[j].channel);
67b23a32 1731 }
3f4978c7
HS
1732#endif
1733 printf("\n");
67b23a32 1734 }
59aa9df3 1735#endif
67b23a32 1736 } else {
59aa9df3
SG
1737 int i;
1738
3f4978c7
HS
1739 /* show specific bus */
1740 i = simple_strtoul(argv[1], NULL, 10);
59aa9df3
SG
1741#ifdef CONFIG_DM_I2C
1742 struct udevice *bus;
1743 int ret;
1744
1745 ret = uclass_get_device_by_seq(UCLASS_I2C, i, &bus);
1746 if (ret) {
1747 printf("Invalid bus %d: err=%d\n", i, ret);
1748 return CMD_RET_FAILURE;
1749 }
1750 show_bus(bus);
1751#else
3f4978c7
HS
1752 if (i >= CONFIG_SYS_NUM_I2C_BUSES) {
1753 printf("Invalid bus %d\n", i);
1754 return -1;
1755 }
1756 printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
1757#ifndef CONFIG_SYS_I2C_DIRECT_BUS
59aa9df3 1758 int j;
3f4978c7
HS
1759 for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
1760 if (i2c_bus[i].next_hop[j].chip == 0)
1761 break;
1762 printf("->%s@0x%2x:%d",
1763 i2c_bus[i].next_hop[j].mux.name,
1764 i2c_bus[i].next_hop[j].chip,
1765 i2c_bus[i].next_hop[j].channel);
1766 }
1767#endif
1768 printf("\n");
59aa9df3 1769#endif
67b23a32 1770 }
3f4978c7
HS
1771
1772 return 0;
67b23a32 1773}
3f4978c7 1774#endif
67b23a32 1775
06afa388
MV
1776/**
1777 * do_i2c_bus_num() - Handle the "i2c dev" command-line command
1778 * @cmdtp: Command data struct pointer
1779 * @flag: Command flag
1780 * @argc: Command-line argument count
1781 * @argv: Array of command-line arguments
1782 *
1783 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1784 * on error.
1785 */
63656b76
SG
1786#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS) || \
1787 defined(CONFIG_DM_I2C)
0e350f81
JH
1788static int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc,
1789 char * const argv[])
bb99ad6d 1790{
3f4978c7 1791 int ret = 0;
63656b76 1792 int bus_no;
bb99ad6d 1793
63656b76 1794 if (argc == 1) {
e857a5bd 1795 /* querying current setting */
63656b76
SG
1796#ifdef CONFIG_DM_I2C
1797 struct udevice *bus;
1798
1799 if (!i2c_get_cur_bus(&bus))
1800 bus_no = bus->seq;
1801 else
1802 bus_no = -1;
1803#else
1804 bus_no = i2c_get_bus_num();
1805#endif
1806 printf("Current bus is %d\n", bus_no);
1807 } else {
3f4978c7 1808 bus_no = simple_strtoul(argv[1], NULL, 10);
880a4127 1809#if defined(CONFIG_SYS_I2C)
3f4978c7
HS
1810 if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) {
1811 printf("Invalid bus %d\n", bus_no);
1812 return -1;
1813 }
880a4127 1814#endif
3f4978c7 1815 printf("Setting bus to %d\n", bus_no);
f9a4c2da
SG
1816#ifdef CONFIG_DM_I2C
1817 ret = cmd_i2c_set_bus_num(bus_no);
1818#else
3f4978c7 1819 ret = i2c_set_bus_num(bus_no);
f9a4c2da 1820#endif
e857a5bd 1821 if (ret)
bb99ad6d 1822 printf("Failure changing bus number (%d)\n", ret);
bb99ad6d 1823 }
4fbd258e
SG
1824
1825 return ret ? CMD_RET_FAILURE : 0;
bb99ad6d 1826}
3f4978c7 1827#endif /* defined(CONFIG_SYS_I2C) */
bb99ad6d 1828
06afa388
MV
1829/**
1830 * do_i2c_bus_speed() - Handle the "i2c speed" command-line command
1831 * @cmdtp: Command data struct pointer
1832 * @flag: Command flag
1833 * @argc: Command-line argument count
1834 * @argv: Array of command-line arguments
1835 *
1836 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1837 * on error.
1838 */
54841ab5 1839static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bb99ad6d
BW
1840{
1841 int speed, ret=0;
1842
63656b76
SG
1843#ifdef CONFIG_DM_I2C
1844 struct udevice *bus;
1845
1846 if (i2c_get_cur_bus(&bus))
1847 return 1;
1848#endif
1849 if (argc == 1) {
1850#ifdef CONFIG_DM_I2C
ca88b9b9 1851 speed = dm_i2c_get_bus_speed(bus);
63656b76
SG
1852#else
1853 speed = i2c_get_bus_speed();
1854#endif
e857a5bd 1855 /* querying current speed */
63656b76
SG
1856 printf("Current bus speed=%d\n", speed);
1857 } else {
bb99ad6d
BW
1858 speed = simple_strtoul(argv[1], NULL, 10);
1859 printf("Setting bus speed to %d Hz\n", speed);
63656b76 1860#ifdef CONFIG_DM_I2C
ca88b9b9 1861 ret = dm_i2c_set_bus_speed(bus, speed);
63656b76 1862#else
bb99ad6d 1863 ret = i2c_set_bus_speed(speed);
63656b76 1864#endif
e857a5bd 1865 if (ret)
bb99ad6d 1866 printf("Failure changing bus speed (%d)\n", ret);
bb99ad6d 1867 }
4fbd258e
SG
1868
1869 return ret ? CMD_RET_FAILURE : 0;
bb99ad6d
BW
1870}
1871
06afa388
MV
1872/**
1873 * do_i2c_mm() - Handle the "i2c mm" command-line command
1874 * @cmdtp: Command data struct pointer
1875 * @flag: Command flag
1876 * @argc: Command-line argument count
1877 * @argv: Array of command-line arguments
1878 *
1879 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1880 * on error.
1881 */
54841ab5 1882static int do_i2c_mm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bb99ad6d 1883{
bfc3b77e
FM
1884 return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
1885}
1886
06afa388
MV
1887/**
1888 * do_i2c_nm() - Handle the "i2c nm" command-line command
1889 * @cmdtp: Command data struct pointer
1890 * @flag: Command flag
1891 * @argc: Command-line argument count
1892 * @argv: Array of command-line arguments
1893 *
1894 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1895 * on error.
1896 */
54841ab5 1897static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bfc3b77e
FM
1898{
1899 return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
1900}
e96ad5d3 1901
06afa388
MV
1902/**
1903 * do_i2c_reset() - Handle the "i2c reset" command-line command
1904 * @cmdtp: Command data struct pointer
1905 * @flag: Command flag
1906 * @argc: Command-line argument count
1907 * @argv: Array of command-line arguments
1908 *
1909 * Returns zero always.
1910 */
54841ab5 1911static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bfc3b77e 1912{
63656b76
SG
1913#if defined(CONFIG_DM_I2C)
1914 struct udevice *bus;
1915
1916 if (i2c_get_cur_bus(&bus))
1917 return CMD_RET_FAILURE;
1918 if (i2c_deblock(bus)) {
1919 printf("Error: Not supported by the driver\n");
1920 return CMD_RET_FAILURE;
1921 }
1922#elif defined(CONFIG_SYS_I2C)
3f4978c7
HS
1923 i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr);
1924#else
bfc3b77e 1925 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
3f4978c7 1926#endif
bfc3b77e
FM
1927 return 0;
1928}
1929
1930static cmd_tbl_t cmd_i2c_sub[] = {
59aa9df3 1931#if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C)
3f4978c7 1932 U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""),
9a2accb4 1933#endif
bfc3b77e 1934 U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
3f4978c7 1935#if defined(CONFIG_SYS_I2C) || \
63656b76 1936 defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
bfc3b77e 1937 U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
bb99ad6d 1938#endif /* CONFIG_I2C_MULTI_BUS */
735987c5
TWHT
1939#if defined(CONFIG_I2C_EDID)
1940 U_BOOT_CMD_MKENT(edid, 1, 1, do_edid, "", ""),
1941#endif /* CONFIG_I2C_EDID */
bfc3b77e
FM
1942 U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""),
1943 U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""),
1944 U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""),
1945 U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""),
1946 U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
1947 U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
652e5354 1948 U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
ed16f146 1949 U_BOOT_CMD_MKENT(write, 6, 0, do_i2c_write, "", ""),
63656b76
SG
1950#ifdef CONFIG_DM_I2C
1951 U_BOOT_CMD_MKENT(flags, 2, 1, do_i2c_flags, "", ""),
c10c8e31 1952 U_BOOT_CMD_MKENT(olen, 2, 1, do_i2c_olen, "", ""),
63656b76 1953#endif
bfc3b77e 1954 U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
c76fe474 1955#if defined(CONFIG_CMD_SDRAM)
bfc3b77e 1956 U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
90253178 1957#endif
bfc3b77e
FM
1958 U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
1959};
1960
e4099c8b
MS
1961static __maybe_unused void i2c_reloc(void)
1962{
1963 static int relocated;
1964
1965 if (!relocated) {
1966 fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
1967 relocated = 1;
1968 };
f1d2b313 1969}
f1d2b313 1970
06afa388
MV
1971/**
1972 * do_i2c() - Handle the "i2c" command-line command
1973 * @cmdtp: Command data struct pointer
1974 * @flag: Command flag
1975 * @argc: Command-line argument count
1976 * @argv: Array of command-line arguments
1977 *
1978 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1979 * on error.
1980 */
54841ab5 1981static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bfc3b77e
FM
1982{
1983 cmd_tbl_t *c;
1984
e4099c8b
MS
1985#ifdef CONFIG_NEEDS_MANUAL_RELOC
1986 i2c_reloc();
1987#endif
1988
4444b221 1989 if (argc < 2)
4c12eeb8 1990 return CMD_RET_USAGE;
4444b221 1991
bfc3b77e
FM
1992 /* Strip off leading 'i2c' command argument */
1993 argc--;
1994 argv++;
1995
1996 c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub));
1997
47e26b1b 1998 if (c)
4c12eeb8 1999 return c->cmd(cmdtp, flag, argc, argv);
47e26b1b 2000 else
4c12eeb8 2001 return CMD_RET_USAGE;
bb99ad6d 2002}
8bde7f77
WD
2003
2004/***************************************************/
088f1b19
KP
2005#ifdef CONFIG_SYS_LONGHELP
2006static char i2c_help_text[] =
59aa9df3 2007#if defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C)
3f4978c7 2008 "bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n"
9a2accb4 2009#endif
fb0070e9 2010 "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
3f4978c7 2011#if defined(CONFIG_SYS_I2C) || \
63656b76 2012 defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
9bc2e4ee 2013 "i2c dev [dev] - show or set current I2C bus\n"
d9fc7032 2014#endif /* CONFIG_I2C_MULTI_BUS */
735987c5
TWHT
2015#if defined(CONFIG_I2C_EDID)
2016 "i2c edid chip - print EDID configuration information\n"
2017#endif /* CONFIG_I2C_EDID */
fb0070e9 2018 "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
d9fc7032
MF
2019 "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
2020 "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
2021 "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
2022 "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
54b99e51 2023 "i2c probe [address] - test for and show device(s) on the I2C bus\n"
63656b76 2024 "i2c read chip address[.0, .1, .2] length memaddress - read to memory\n"
ed16f146
LP
2025 "i2c write memaddress chip address[.0, .1, .2] length [-s] - write memory\n"
2026 " to I2C; the -s option selects bulk write in a single transaction\n"
63656b76
SG
2027#ifdef CONFIG_DM_I2C
2028 "i2c flags chip [flags] - set or get chip flags\n"
c10c8e31 2029 "i2c olen chip [offset_length] - set or get chip offset length\n"
63656b76 2030#endif
e43a27c4 2031 "i2c reset - re-init the I2C Controller\n"
c76fe474 2032#if defined(CONFIG_CMD_SDRAM)
fb0070e9 2033 "i2c sdram chip - print SDRAM configuration information\n"
90253178 2034#endif
088f1b19
KP
2035 "i2c speed [speed] - show or set I2C bus speed";
2036#endif
2037
2038U_BOOT_CMD(
ed16f146 2039 i2c, 7, 1, do_i2c,
088f1b19
KP
2040 "I2C sub-system",
2041 i2c_help_text
d9fc7032 2042);