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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1938f4a5 SG |
2 | /* |
3 | * Copyright (c) 2011 The Chromium OS Authors. | |
4 | * (C) Copyright 2002-2006 | |
5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
6 | * | |
7 | * (C) Copyright 2002 | |
8 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
9 | * Marius Groeger <mgroeger@sysgo.de> | |
1938f4a5 SG |
10 | */ |
11 | ||
12 | #include <common.h> | |
f0293d33 | 13 | #include <bloblist.h> |
52f24238 | 14 | #include <bootstage.h> |
d96c2604 | 15 | #include <clock_legacy.h> |
24b852a7 | 16 | #include <console.h> |
5d6c61ac | 17 | #include <cpu.h> |
30c7c434 | 18 | #include <cpu_func.h> |
ab7cd627 | 19 | #include <dm.h> |
4bfd1f5d | 20 | #include <env.h> |
f3998fdc | 21 | #include <env_internal.h> |
1938f4a5 | 22 | #include <fdtdec.h> |
f828bf25 | 23 | #include <fs.h> |
db41d65a | 24 | #include <hang.h> |
e4fef6cf | 25 | #include <i2c.h> |
67c4e9f8 | 26 | #include <init.h> |
1938f4a5 | 27 | #include <initcall.h> |
3c1ecde4 | 28 | #include <lcd.h> |
f7ae49fc | 29 | #include <log.h> |
fb5cf7f1 | 30 | #include <malloc.h> |
0eb25b61 | 31 | #include <mapmem.h> |
a733b06b | 32 | #include <os.h> |
1938f4a5 | 33 | #include <post.h> |
e47b2d67 | 34 | #include <relocate.h> |
b03e0510 | 35 | #include <serial.h> |
b0edea3c SG |
36 | #ifdef CONFIG_SPL |
37 | #include <spl.h> | |
38 | #endif | |
c5d4001a | 39 | #include <status_led.h> |
23471aed | 40 | #include <sysreset.h> |
1057e6cf | 41 | #include <timer.h> |
71c52dba | 42 | #include <trace.h> |
5a541945 | 43 | #include <video.h> |
e4fef6cf | 44 | #include <watchdog.h> |
90526e9f | 45 | #include <asm/cache.h> |
b885d02e SG |
46 | #ifdef CONFIG_MACH_TYPE |
47 | #include <asm/mach-types.h> | |
48 | #endif | |
1fbf97dc SG |
49 | #if defined(CONFIG_MP) && defined(CONFIG_PPC) |
50 | #include <asm/mp.h> | |
51 | #endif | |
1938f4a5 SG |
52 | #include <asm/io.h> |
53 | #include <asm/sections.h> | |
ab7cd627 | 54 | #include <dm/root.h> |
056285fd | 55 | #include <linux/errno.h> |
1938f4a5 SG |
56 | |
57 | /* | |
58 | * Pointer to initial global data area | |
59 | * | |
60 | * Here we initialize it if needed. | |
61 | */ | |
62 | #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR | |
63 | #undef XTRN_DECLARE_GLOBAL_DATA_PTR | |
64 | #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ | |
16ef1474 | 65 | DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR); |
1938f4a5 SG |
66 | #else |
67 | DECLARE_GLOBAL_DATA_PTR; | |
68 | #endif | |
69 | ||
70 | /* | |
4c509343 | 71 | * TODO(sjg@chromium.org): IMO this code should be |
1938f4a5 SG |
72 | * refactored to a single function, something like: |
73 | * | |
74 | * void led_set_state(enum led_colour_t colour, int on); | |
75 | */ | |
76 | /************************************************************************ | |
77 | * Coloured LED functionality | |
78 | ************************************************************************ | |
79 | * May be supplied by boards if desired | |
80 | */ | |
c5d4001a JH |
81 | __weak void coloured_LED_init(void) {} |
82 | __weak void red_led_on(void) {} | |
83 | __weak void red_led_off(void) {} | |
84 | __weak void green_led_on(void) {} | |
85 | __weak void green_led_off(void) {} | |
86 | __weak void yellow_led_on(void) {} | |
87 | __weak void yellow_led_off(void) {} | |
88 | __weak void blue_led_on(void) {} | |
89 | __weak void blue_led_off(void) {} | |
1938f4a5 SG |
90 | |
91 | /* | |
92 | * Why is gd allocated a register? Prior to reloc it might be better to | |
93 | * just pass it around to each function in this file? | |
94 | * | |
95 | * After reloc one could argue that it is hardly used and doesn't need | |
96 | * to be in a register. Or if it is it should perhaps hold pointers to all | |
97 | * global data for all modules, so that post-reloc we can avoid the massive | |
98 | * literal pool we get on ARM. Or perhaps just encourage each module to use | |
99 | * a structure... | |
100 | */ | |
101 | ||
d54d7eb9 | 102 | #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) |
e4fef6cf SG |
103 | static int init_func_watchdog_init(void) |
104 | { | |
ea3310e8 TR |
105 | # if defined(CONFIG_HW_WATCHDOG) && \ |
106 | (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ | |
1473f6ac | 107 | defined(CONFIG_SH) || \ |
46d7a3b3 | 108 | defined(CONFIG_DESIGNWARE_WATCHDOG) || \ |
14a380a8 | 109 | defined(CONFIG_IMX_WATCHDOG)) |
d54d7eb9 | 110 | hw_watchdog_init(); |
e4fef6cf | 111 | puts(" Watchdog enabled\n"); |
ba169d98 | 112 | # endif |
e4fef6cf SG |
113 | WATCHDOG_RESET(); |
114 | ||
115 | return 0; | |
116 | } | |
117 | ||
118 | int init_func_watchdog_reset(void) | |
119 | { | |
120 | WATCHDOG_RESET(); | |
121 | ||
122 | return 0; | |
123 | } | |
124 | #endif /* CONFIG_WATCHDOG */ | |
125 | ||
dd2a6cd0 | 126 | __weak void board_add_ram_info(int use_default) |
e4fef6cf SG |
127 | { |
128 | /* please define platform specific board_add_ram_info() */ | |
129 | } | |
130 | ||
1938f4a5 SG |
131 | static int init_baud_rate(void) |
132 | { | |
bfebc8c9 | 133 | gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); |
1938f4a5 SG |
134 | return 0; |
135 | } | |
136 | ||
137 | static int display_text_info(void) | |
138 | { | |
9b217498 | 139 | #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) |
9fdee7d7 | 140 | ulong bss_start, bss_end, text_base; |
1938f4a5 | 141 | |
632efa74 SG |
142 | bss_start = (ulong)&__bss_start; |
143 | bss_end = (ulong)&__bss_end; | |
b60eff31 | 144 | |
d54d7eb9 | 145 | #ifdef CONFIG_SYS_TEXT_BASE |
9fdee7d7 | 146 | text_base = CONFIG_SYS_TEXT_BASE; |
d54d7eb9 | 147 | #else |
9fdee7d7 | 148 | text_base = CONFIG_SYS_MONITOR_BASE; |
d54d7eb9 | 149 | #endif |
9fdee7d7 DS |
150 | |
151 | debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", | |
16ef1474 | 152 | text_base, bss_start, bss_end); |
a733b06b | 153 | #endif |
1938f4a5 | 154 | |
1938f4a5 SG |
155 | return 0; |
156 | } | |
157 | ||
23471aed MS |
158 | #ifdef CONFIG_SYSRESET |
159 | static int print_resetinfo(void) | |
160 | { | |
161 | struct udevice *dev; | |
162 | char status[256]; | |
163 | int ret; | |
164 | ||
165 | ret = uclass_first_device_err(UCLASS_SYSRESET, &dev); | |
166 | if (ret) { | |
167 | debug("%s: No sysreset device found (error: %d)\n", | |
168 | __func__, ret); | |
169 | /* Not all boards have sysreset drivers available during early | |
170 | * boot, so don't fail if one can't be found. | |
171 | */ | |
172 | return 0; | |
173 | } | |
174 | ||
175 | if (!sysreset_get_status(dev, status, sizeof(status))) | |
176 | printf("%s", status); | |
177 | ||
178 | return 0; | |
179 | } | |
180 | #endif | |
181 | ||
5d6c61ac MS |
182 | #if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU) |
183 | static int print_cpuinfo(void) | |
184 | { | |
185 | struct udevice *dev; | |
186 | char desc[512]; | |
187 | int ret; | |
188 | ||
f5b66af2 YL |
189 | dev = cpu_get_current_dev(); |
190 | if (!dev) { | |
191 | debug("%s: Could not get CPU device\n", | |
192 | __func__); | |
193 | return -ENODEV; | |
5d6c61ac MS |
194 | } |
195 | ||
196 | ret = cpu_get_desc(dev, desc, sizeof(desc)); | |
197 | if (ret) { | |
198 | debug("%s: Could not get CPU description (err = %d)\n", | |
199 | dev->name, ret); | |
200 | return ret; | |
201 | } | |
202 | ||
ecfe6633 | 203 | printf("CPU: %s\n", desc); |
5d6c61ac MS |
204 | |
205 | return 0; | |
206 | } | |
207 | #endif | |
208 | ||
1938f4a5 SG |
209 | static int announce_dram_init(void) |
210 | { | |
211 | puts("DRAM: "); | |
212 | return 0; | |
213 | } | |
214 | ||
215 | static int show_dram_config(void) | |
216 | { | |
fa39ffe5 | 217 | unsigned long long size; |
1938f4a5 SG |
218 | |
219 | #ifdef CONFIG_NR_DRAM_BANKS | |
220 | int i; | |
221 | ||
222 | debug("\nRAM Configuration:\n"); | |
223 | for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
224 | size += gd->bd->bi_dram[i].size; | |
715f599f BM |
225 | debug("Bank #%d: %llx ", i, |
226 | (unsigned long long)(gd->bd->bi_dram[i].start)); | |
1938f4a5 SG |
227 | #ifdef DEBUG |
228 | print_size(gd->bd->bi_dram[i].size, "\n"); | |
229 | #endif | |
230 | } | |
231 | debug("\nDRAM: "); | |
232 | #else | |
233 | size = gd->ram_size; | |
234 | #endif | |
235 | ||
e4fef6cf SG |
236 | print_size(size, ""); |
237 | board_add_ram_info(0); | |
238 | putc('\n'); | |
1938f4a5 SG |
239 | |
240 | return 0; | |
241 | } | |
242 | ||
76b00aca | 243 | __weak int dram_init_banksize(void) |
1938f4a5 SG |
244 | { |
245 | #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) | |
246 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
247 | gd->bd->bi_dram[0].size = get_effective_memsize(); | |
248 | #endif | |
76b00aca SG |
249 | |
250 | return 0; | |
1938f4a5 SG |
251 | } |
252 | ||
69153988 | 253 | #if defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
254 | static int init_func_i2c(void) |
255 | { | |
256 | puts("I2C: "); | |
815a76f2 | 257 | #ifdef CONFIG_SYS_I2C |
258 | i2c_init_all(); | |
259 | #else | |
e4fef6cf | 260 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
815a76f2 | 261 | #endif |
e4fef6cf SG |
262 | puts("ready\n"); |
263 | return 0; | |
264 | } | |
265 | #endif | |
266 | ||
1fab98fb RB |
267 | #if defined(CONFIG_VID) |
268 | __weak int init_func_vid(void) | |
269 | { | |
270 | return 0; | |
271 | } | |
272 | #endif | |
273 | ||
1938f4a5 SG |
274 | static int setup_mon_len(void) |
275 | { | |
e945f6dc | 276 | #if defined(__ARM__) || defined(__MICROBLAZE__) |
b60eff31 | 277 | gd->mon_len = (ulong)&__bss_end - (ulong)_start; |
9b217498 | 278 | #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) |
a733b06b | 279 | gd->mon_len = (ulong)&_end - (ulong)_init; |
ea3310e8 | 280 | #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) |
d54d7eb9 | 281 | gd->mon_len = CONFIG_SYS_MONITOR_LEN; |
068feb9b | 282 | #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV) |
2e88bb28 | 283 | gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); |
b0b35953 | 284 | #elif defined(CONFIG_SYS_MONITOR_BASE) |
e4fef6cf SG |
285 | /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ |
286 | gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; | |
632efa74 | 287 | #endif |
1938f4a5 SG |
288 | return 0; |
289 | } | |
290 | ||
b0edea3c SG |
291 | static int setup_spl_handoff(void) |
292 | { | |
293 | #if CONFIG_IS_ENABLED(HANDOFF) | |
294 | gd->spl_handoff = bloblist_find(BLOBLISTT_SPL_HANDOFF, | |
295 | sizeof(struct spl_handoff)); | |
296 | debug("Found SPL hand-off info %p\n", gd->spl_handoff); | |
297 | #endif | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
1938f4a5 SG |
302 | __weak int arch_cpu_init(void) |
303 | { | |
304 | return 0; | |
305 | } | |
306 | ||
8ebf5069 PB |
307 | __weak int mach_cpu_init(void) |
308 | { | |
309 | return 0; | |
310 | } | |
311 | ||
1938f4a5 SG |
312 | /* Get the top of usable RAM */ |
313 | __weak ulong board_get_usable_ram_top(ulong total_size) | |
314 | { | |
54280962 | 315 | #if defined(CONFIG_SYS_SDRAM_BASE) && CONFIG_SYS_SDRAM_BASE > 0 |
1e4d11a5 | 316 | /* |
4c509343 | 317 | * Detect whether we have so much RAM that it goes past the end of our |
1e4d11a5 SW |
318 | * 32-bit address space. If so, clip the usable RAM so it doesn't. |
319 | */ | |
320 | if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) | |
321 | /* | |
322 | * Will wrap back to top of 32-bit space when reservations | |
323 | * are made. | |
324 | */ | |
325 | return 0; | |
326 | #endif | |
1938f4a5 SG |
327 | return gd->ram_top; |
328 | } | |
329 | ||
330 | static int setup_dest_addr(void) | |
331 | { | |
332 | debug("Monitor len: %08lX\n", gd->mon_len); | |
333 | /* | |
334 | * Ram is setup, size stored in gd !! | |
335 | */ | |
336 | debug("Ram size: %08lX\n", (ulong)gd->ram_size); | |
36cc0de0 | 337 | #if defined(CONFIG_SYS_MEM_TOP_HIDE) |
1938f4a5 SG |
338 | /* |
339 | * Subtract specified amount of memory to hide so that it won't | |
340 | * get "touched" at all by U-Boot. By fixing up gd->ram_size | |
341 | * the Linux kernel should now get passed the now "corrected" | |
36cc0de0 YS |
342 | * memory size and won't touch it either. This should work |
343 | * for arch/ppc and arch/powerpc. Only Linux board ports in | |
344 | * arch/powerpc with bootwrapper support, that recalculate the | |
345 | * memory size from the SDRAM controller setup will have to | |
346 | * get fixed. | |
1938f4a5 | 347 | */ |
36cc0de0 YS |
348 | gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; |
349 | #endif | |
1938f4a5 | 350 | #ifdef CONFIG_SYS_SDRAM_BASE |
1473b12a | 351 | gd->ram_base = CONFIG_SYS_SDRAM_BASE; |
1938f4a5 | 352 | #endif |
1473b12a | 353 | gd->ram_top = gd->ram_base + get_effective_memsize(); |
1938f4a5 | 354 | gd->ram_top = board_get_usable_ram_top(gd->mon_len); |
a0ba279a | 355 | gd->relocaddr = gd->ram_top; |
1938f4a5 | 356 | debug("Ram top: %08lX\n", (ulong)gd->ram_top); |
ec3b4820 | 357 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
e4fef6cf SG |
358 | /* |
359 | * We need to make sure the location we intend to put secondary core | |
360 | * boot code is reserved and not used by any part of u-boot | |
361 | */ | |
a0ba279a MY |
362 | if (gd->relocaddr > determine_mp_bootpg(NULL)) { |
363 | gd->relocaddr = determine_mp_bootpg(NULL); | |
364 | debug("Reserving MP boot page to %08lx\n", gd->relocaddr); | |
e4fef6cf SG |
365 | } |
366 | #endif | |
1938f4a5 SG |
367 | return 0; |
368 | } | |
369 | ||
1938f4a5 SG |
370 | #ifdef CONFIG_PRAM |
371 | /* reserve protected RAM */ | |
372 | static int reserve_pram(void) | |
373 | { | |
374 | ulong reg; | |
375 | ||
bfebc8c9 | 376 | reg = env_get_ulong("pram", 10, CONFIG_PRAM); |
a0ba279a | 377 | gd->relocaddr -= (reg << 10); /* size is in kB */ |
1938f4a5 | 378 | debug("Reserving %ldk for protected RAM at %08lx\n", reg, |
a0ba279a | 379 | gd->relocaddr); |
1938f4a5 SG |
380 | return 0; |
381 | } | |
382 | #endif /* CONFIG_PRAM */ | |
383 | ||
384 | /* Round memory pointer down to next 4 kB limit */ | |
385 | static int reserve_round_4k(void) | |
386 | { | |
a0ba279a | 387 | gd->relocaddr &= ~(4096 - 1); |
1938f4a5 SG |
388 | return 0; |
389 | } | |
390 | ||
79926e4f OP |
391 | __weak int arch_reserve_mmu(void) |
392 | { | |
393 | return 0; | |
394 | } | |
395 | ||
5a541945 SG |
396 | static int reserve_video(void) |
397 | { | |
0f079eb5 | 398 | #ifdef CONFIG_DM_VIDEO |
5a541945 SG |
399 | ulong addr; |
400 | int ret; | |
401 | ||
402 | addr = gd->relocaddr; | |
403 | ret = video_reserve(&addr); | |
404 | if (ret) | |
405 | return ret; | |
406 | gd->relocaddr = addr; | |
0f079eb5 | 407 | #elif defined(CONFIG_LCD) |
5a541945 | 408 | # ifdef CONFIG_FB_ADDR |
1938f4a5 | 409 | gd->fb_base = CONFIG_FB_ADDR; |
5a541945 | 410 | # else |
1938f4a5 | 411 | /* reserve memory for LCD display (always full pages) */ |
a0ba279a MY |
412 | gd->relocaddr = lcd_setmem(gd->relocaddr); |
413 | gd->fb_base = gd->relocaddr; | |
5a541945 | 414 | # endif /* CONFIG_FB_ADDR */ |
0f079eb5 | 415 | #endif |
e4fef6cf SG |
416 | |
417 | return 0; | |
418 | } | |
e4fef6cf | 419 | |
8703ef3f SG |
420 | static int reserve_trace(void) |
421 | { | |
422 | #ifdef CONFIG_TRACE | |
423 | gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; | |
424 | gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); | |
7ea33579 HS |
425 | debug("Reserving %luk for trace data at: %08lx\n", |
426 | (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); | |
8703ef3f SG |
427 | #endif |
428 | ||
429 | return 0; | |
430 | } | |
431 | ||
1938f4a5 SG |
432 | static int reserve_uboot(void) |
433 | { | |
ff2b2ba8 AB |
434 | if (!(gd->flags & GD_FLG_SKIP_RELOC)) { |
435 | /* | |
436 | * reserve memory for U-Boot code, data & bss | |
437 | * round down to next 4 kB limit | |
438 | */ | |
439 | gd->relocaddr -= gd->mon_len; | |
440 | gd->relocaddr &= ~(4096 - 1); | |
441 | #if defined(CONFIG_E500) || defined(CONFIG_MIPS) | |
442 | /* round down to next 64 kB limit so that IVPR stays aligned */ | |
443 | gd->relocaddr &= ~(65536 - 1); | |
444 | #endif | |
445 | ||
446 | debug("Reserving %ldk for U-Boot at: %08lx\n", | |
447 | gd->mon_len >> 10, gd->relocaddr); | |
448 | } | |
a0ba279a MY |
449 | |
450 | gd->start_addr_sp = gd->relocaddr; | |
451 | ||
1938f4a5 SG |
452 | return 0; |
453 | } | |
454 | ||
65c141eb PD |
455 | /* |
456 | * reserve after start_addr_sp the requested size and make the stack pointer | |
457 | * 16-byte aligned, this alignment is needed for cast on the reserved memory | |
458 | * ref = x86_64 ABI: https://reviews.llvm.org/D30049: 16 bytes | |
459 | * = ARMv8 Instruction Set Overview: quad word, 16 bytes | |
460 | */ | |
461 | static unsigned long reserve_stack_aligned(size_t size) | |
462 | { | |
463 | return ALIGN_DOWN(gd->start_addr_sp - size, 16); | |
464 | } | |
465 | ||
5f7adb5b VM |
466 | #ifdef CONFIG_SYS_NONCACHED_MEMORY |
467 | static int reserve_noncached(void) | |
468 | { | |
5e0404ff SW |
469 | /* |
470 | * The value of gd->start_addr_sp must match the value of malloc_start | |
471 | * calculated in boatrd_f.c:initr_malloc(), which is passed to | |
472 | * board_r.c:mem_malloc_init() and then used by | |
473 | * cache.c:noncached_init() | |
474 | * | |
475 | * These calculations must match the code in cache.c:noncached_init() | |
476 | */ | |
477 | gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) - | |
478 | MMU_SECTION_SIZE; | |
479 | gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY, | |
480 | MMU_SECTION_SIZE); | |
5f7adb5b VM |
481 | debug("Reserving %dM for noncached_alloc() at: %08lx\n", |
482 | CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp); | |
483 | ||
484 | return 0; | |
485 | } | |
486 | #endif | |
487 | ||
1938f4a5 SG |
488 | /* reserve memory for malloc() area */ |
489 | static int reserve_malloc(void) | |
490 | { | |
65c141eb | 491 | gd->start_addr_sp = reserve_stack_aligned(TOTAL_MALLOC_LEN); |
1938f4a5 | 492 | debug("Reserving %dk for malloc() at: %08lx\n", |
16ef1474 | 493 | TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); |
5f7adb5b VM |
494 | #ifdef CONFIG_SYS_NONCACHED_MEMORY |
495 | reserve_noncached(); | |
496 | #endif | |
497 | ||
1938f4a5 SG |
498 | return 0; |
499 | } | |
500 | ||
501 | /* (permanently) allocate a Board Info struct */ | |
502 | static int reserve_board(void) | |
503 | { | |
d54d7eb9 | 504 | if (!gd->bd) { |
65c141eb | 505 | gd->start_addr_sp = reserve_stack_aligned(sizeof(bd_t)); |
d54d7eb9 SZ |
506 | gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); |
507 | memset(gd->bd, '\0', sizeof(bd_t)); | |
508 | debug("Reserving %zu Bytes for Board Info at: %08lx\n", | |
509 | sizeof(bd_t), gd->start_addr_sp); | |
510 | } | |
1938f4a5 SG |
511 | return 0; |
512 | } | |
513 | ||
514 | static int setup_machine(void) | |
515 | { | |
516 | #ifdef CONFIG_MACH_TYPE | |
517 | gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ | |
518 | #endif | |
519 | return 0; | |
520 | } | |
521 | ||
522 | static int reserve_global_data(void) | |
523 | { | |
65c141eb | 524 | gd->start_addr_sp = reserve_stack_aligned(sizeof(gd_t)); |
a0ba279a | 525 | gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); |
1938f4a5 | 526 | debug("Reserving %zu Bytes for Global Data at: %08lx\n", |
16ef1474 | 527 | sizeof(gd_t), gd->start_addr_sp); |
1938f4a5 SG |
528 | return 0; |
529 | } | |
530 | ||
531 | static int reserve_fdt(void) | |
532 | { | |
e9acb9ea | 533 | #ifndef CONFIG_OF_EMBED |
1938f4a5 | 534 | /* |
4c509343 | 535 | * If the device tree is sitting immediately above our image then we |
1938f4a5 SG |
536 | * must relocate it. If it is embedded in the data section, then it |
537 | * will be relocated with other data. | |
538 | */ | |
539 | if (gd->fdt_blob) { | |
540 | gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); | |
541 | ||
65c141eb | 542 | gd->start_addr_sp = reserve_stack_aligned(gd->fdt_size); |
a0ba279a | 543 | gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); |
a733b06b | 544 | debug("Reserving %lu Bytes for FDT at: %08lx\n", |
a0ba279a | 545 | gd->fdt_size, gd->start_addr_sp); |
1938f4a5 | 546 | } |
e9acb9ea | 547 | #endif |
1938f4a5 SG |
548 | |
549 | return 0; | |
550 | } | |
551 | ||
25e7dc6a SG |
552 | static int reserve_bootstage(void) |
553 | { | |
554 | #ifdef CONFIG_BOOTSTAGE | |
555 | int size = bootstage_get_size(); | |
556 | ||
65c141eb | 557 | gd->start_addr_sp = reserve_stack_aligned(size); |
25e7dc6a SG |
558 | gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); |
559 | debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, | |
560 | gd->start_addr_sp); | |
561 | #endif | |
562 | ||
563 | return 0; | |
564 | } | |
565 | ||
d6f87712 | 566 | __weak int arch_reserve_stacks(void) |
1938f4a5 | 567 | { |
68145d4c AB |
568 | return 0; |
569 | } | |
8cae8a68 | 570 | |
68145d4c AB |
571 | static int reserve_stacks(void) |
572 | { | |
573 | /* make stack pointer 16-byte aligned */ | |
65c141eb | 574 | gd->start_addr_sp = reserve_stack_aligned(16); |
1938f4a5 SG |
575 | |
576 | /* | |
4c509343 | 577 | * let the architecture-specific code tailor gd->start_addr_sp and |
68145d4c | 578 | * gd->irq_sp |
1938f4a5 | 579 | */ |
68145d4c | 580 | return arch_reserve_stacks(); |
1938f4a5 SG |
581 | } |
582 | ||
f0293d33 SG |
583 | static int reserve_bloblist(void) |
584 | { | |
585 | #ifdef CONFIG_BLOBLIST | |
65c141eb | 586 | gd->start_addr_sp = reserve_stack_aligned(CONFIG_BLOBLIST_SIZE); |
f0293d33 SG |
587 | gd->new_bloblist = map_sysmem(gd->start_addr_sp, CONFIG_BLOBLIST_SIZE); |
588 | #endif | |
589 | ||
590 | return 0; | |
591 | } | |
592 | ||
1938f4a5 SG |
593 | static int display_new_sp(void) |
594 | { | |
a0ba279a | 595 | debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); |
1938f4a5 SG |
596 | |
597 | return 0; | |
598 | } | |
599 | ||
e2099d78 VZ |
600 | #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ |
601 | defined(CONFIG_SH) | |
e4fef6cf SG |
602 | static int setup_board_part1(void) |
603 | { | |
604 | bd_t *bd = gd->bd; | |
605 | ||
606 | /* | |
607 | * Save local variables to board info struct | |
608 | */ | |
e4fef6cf SG |
609 | bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ |
610 | bd->bi_memsize = gd->ram_size; /* size in bytes */ | |
611 | ||
612 | #ifdef CONFIG_SYS_SRAM_BASE | |
613 | bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ | |
614 | bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ | |
615 | #endif | |
616 | ||
50258977 | 617 | #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
e4fef6cf SG |
618 | bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ |
619 | #endif | |
064b55cf | 620 | #if defined(CONFIG_M68K) |
e4fef6cf SG |
621 | bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ |
622 | #endif | |
623 | #if defined(CONFIG_MPC83xx) | |
624 | bd->bi_immrbar = CONFIG_SYS_IMMR; | |
625 | #endif | |
e4fef6cf SG |
626 | |
627 | return 0; | |
628 | } | |
fb3db635 | 629 | #endif |
e4fef6cf | 630 | |
fb3db635 | 631 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
632 | static int setup_board_part2(void) |
633 | { | |
634 | bd_t *bd = gd->bd; | |
635 | ||
636 | bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ | |
637 | bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ | |
638 | #if defined(CONFIG_CPM2) | |
639 | bd->bi_cpmfreq = gd->arch.cpm_clk; | |
640 | bd->bi_brgfreq = gd->arch.brg_clk; | |
641 | bd->bi_sccfreq = gd->arch.scc_clk; | |
642 | bd->bi_vco = gd->arch.vco_out; | |
643 | #endif /* CONFIG_CPM2 */ | |
1313db48 AW |
644 | #if defined(CONFIG_M68K) && defined(CONFIG_PCI) |
645 | bd->bi_pcifreq = gd->pci_clk; | |
646 | #endif | |
647 | #if defined(CONFIG_EXTRA_CLOCK) | |
648 | bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ | |
649 | bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ | |
650 | bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ | |
651 | #endif | |
e4fef6cf SG |
652 | |
653 | return 0; | |
654 | } | |
655 | #endif | |
656 | ||
1938f4a5 SG |
657 | #ifdef CONFIG_POST |
658 | static int init_post(void) | |
659 | { | |
660 | post_bootmode_init(); | |
661 | post_run(NULL, POST_ROM | post_bootmode_get(0)); | |
662 | ||
663 | return 0; | |
664 | } | |
665 | #endif | |
666 | ||
1938f4a5 SG |
667 | static int reloc_fdt(void) |
668 | { | |
e9acb9ea | 669 | #ifndef CONFIG_OF_EMBED |
f05ad9ba SG |
670 | if (gd->flags & GD_FLG_SKIP_RELOC) |
671 | return 0; | |
1938f4a5 SG |
672 | if (gd->new_fdt) { |
673 | memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); | |
674 | gd->fdt_blob = gd->new_fdt; | |
675 | } | |
e9acb9ea | 676 | #endif |
1938f4a5 SG |
677 | |
678 | return 0; | |
679 | } | |
680 | ||
25e7dc6a SG |
681 | static int reloc_bootstage(void) |
682 | { | |
683 | #ifdef CONFIG_BOOTSTAGE | |
684 | if (gd->flags & GD_FLG_SKIP_RELOC) | |
685 | return 0; | |
686 | if (gd->new_bootstage) { | |
687 | int size = bootstage_get_size(); | |
688 | ||
689 | debug("Copying bootstage from %p to %p, size %x\n", | |
690 | gd->bootstage, gd->new_bootstage, size); | |
691 | memcpy(gd->new_bootstage, gd->bootstage, size); | |
692 | gd->bootstage = gd->new_bootstage; | |
ac9cd480 | 693 | bootstage_relocate(); |
25e7dc6a SG |
694 | } |
695 | #endif | |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
f0293d33 SG |
700 | static int reloc_bloblist(void) |
701 | { | |
702 | #ifdef CONFIG_BLOBLIST | |
703 | if (gd->flags & GD_FLG_SKIP_RELOC) | |
704 | return 0; | |
705 | if (gd->new_bloblist) { | |
706 | int size = CONFIG_BLOBLIST_SIZE; | |
707 | ||
708 | debug("Copying bloblist from %p to %p, size %x\n", | |
709 | gd->bloblist, gd->new_bloblist, size); | |
710 | memcpy(gd->new_bloblist, gd->bloblist, size); | |
711 | gd->bloblist = gd->new_bloblist; | |
712 | } | |
713 | #endif | |
714 | ||
715 | return 0; | |
716 | } | |
717 | ||
1938f4a5 SG |
718 | static int setup_reloc(void) |
719 | { | |
f05ad9ba SG |
720 | if (gd->flags & GD_FLG_SKIP_RELOC) { |
721 | debug("Skipping relocation due to flag\n"); | |
722 | return 0; | |
723 | } | |
724 | ||
d54d7eb9 | 725 | #ifdef CONFIG_SYS_TEXT_BASE |
53207bfd LW |
726 | #ifdef ARM |
727 | gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; | |
728 | #elif defined(CONFIG_M68K) | |
e310b93e | 729 | /* |
730 | * On all ColdFire arch cpu, monitor code starts always | |
731 | * just after the default vector table location, so at 0x400 | |
732 | */ | |
733 | gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); | |
001d1885 | 734 | #elif !defined(CONFIG_SANDBOX) |
53207bfd | 735 | gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; |
e310b93e | 736 | #endif |
d54d7eb9 | 737 | #endif |
1938f4a5 SG |
738 | memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); |
739 | ||
740 | debug("Relocation Offset is: %08lx\n", gd->reloc_off); | |
a733b06b | 741 | debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", |
a0ba279a MY |
742 | gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), |
743 | gd->start_addr_sp); | |
1938f4a5 SG |
744 | |
745 | return 0; | |
746 | } | |
747 | ||
2a792753 | 748 | #ifdef CONFIG_OF_BOARD_FIXUP |
749 | static int fix_fdt(void) | |
750 | { | |
751 | return board_fix_fdt((void *)gd->fdt_blob); | |
752 | } | |
753 | #endif | |
754 | ||
1938f4a5 | 755 | /* ARM calls relocate_code from its crt0.S */ |
530f27ea SG |
756 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ |
757 | !CONFIG_IS_ENABLED(X86_64) | |
1938f4a5 SG |
758 | |
759 | static int jump_to_copy(void) | |
760 | { | |
f05ad9ba SG |
761 | if (gd->flags & GD_FLG_SKIP_RELOC) |
762 | return 0; | |
48a33806 SG |
763 | /* |
764 | * x86 is special, but in a nice way. It uses a trampoline which | |
765 | * enables the dcache if possible. | |
766 | * | |
767 | * For now, other archs use relocate_code(), which is implemented | |
768 | * similarly for all archs. When we do generic relocation, hopefully | |
769 | * we can make all archs enable the dcache prior to relocation. | |
770 | */ | |
3fb80163 | 771 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
772 | /* |
773 | * SDRAM and console are now initialised. The final stack can now | |
774 | * be setup in SDRAM. Code execution will continue in Flash, but | |
775 | * with the stack in SDRAM and Global Data in temporary memory | |
776 | * (CPU cache) | |
777 | */ | |
f0c7d9c7 | 778 | arch_setup_gd(gd->new_gd); |
48a33806 SG |
779 | board_init_f_r_trampoline(gd->start_addr_sp); |
780 | #else | |
a0ba279a | 781 | relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); |
48a33806 | 782 | #endif |
1938f4a5 SG |
783 | |
784 | return 0; | |
785 | } | |
786 | #endif | |
787 | ||
788 | /* Record the board_init_f() bootstage (after arch_cpu_init()) */ | |
b383d6c0 | 789 | static int initf_bootstage(void) |
1938f4a5 | 790 | { |
baa7d345 SG |
791 | bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && |
792 | IS_ENABLED(CONFIG_BOOTSTAGE_STASH); | |
b383d6c0 SG |
793 | int ret; |
794 | ||
824bb1b4 | 795 | ret = bootstage_init(!from_spl); |
b383d6c0 SG |
796 | if (ret) |
797 | return ret; | |
824bb1b4 SG |
798 | if (from_spl) { |
799 | const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, | |
800 | CONFIG_BOOTSTAGE_STASH_SIZE); | |
801 | ||
802 | ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); | |
803 | if (ret && ret != -ENOENT) { | |
804 | debug("Failed to unstash bootstage: err=%d\n", ret); | |
805 | return ret; | |
806 | } | |
807 | } | |
b383d6c0 | 808 | |
1938f4a5 SG |
809 | bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); |
810 | ||
811 | return 0; | |
812 | } | |
813 | ||
9854a874 SG |
814 | static int initf_console_record(void) |
815 | { | |
f1896c45 | 816 | #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN) |
9854a874 SG |
817 | return console_record_init(); |
818 | #else | |
819 | return 0; | |
820 | #endif | |
821 | } | |
822 | ||
ab7cd627 SG |
823 | static int initf_dm(void) |
824 | { | |
f1896c45 | 825 | #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN) |
ab7cd627 SG |
826 | int ret; |
827 | ||
b67eefdb | 828 | bootstage_start(BOOTSTAGE_ID_ACCUM_DM_F, "dm_f"); |
ab7cd627 | 829 | ret = dm_init_and_scan(true); |
b67eefdb | 830 | bootstage_accum(BOOTSTAGE_ID_ACCUM_DM_F); |
ab7cd627 SG |
831 | if (ret) |
832 | return ret; | |
833 | #endif | |
1057e6cf SG |
834 | #ifdef CONFIG_TIMER_EARLY |
835 | ret = dm_timer_init(); | |
836 | if (ret) | |
837 | return ret; | |
838 | #endif | |
ab7cd627 SG |
839 | |
840 | return 0; | |
841 | } | |
842 | ||
146251f8 SG |
843 | /* Architecture-specific memory reservation */ |
844 | __weak int reserve_arch(void) | |
845 | { | |
846 | return 0; | |
847 | } | |
848 | ||
d4c671cc SG |
849 | __weak int arch_cpu_init_dm(void) |
850 | { | |
851 | return 0; | |
852 | } | |
853 | ||
016e4ae7 OP |
854 | __weak int checkcpu(void) |
855 | { | |
856 | return 0; | |
857 | } | |
858 | ||
fbf9c154 OP |
859 | __weak int clear_bss(void) |
860 | { | |
861 | return 0; | |
862 | } | |
863 | ||
4acff452 | 864 | static const init_fnc_t init_sequence_f[] = { |
1938f4a5 | 865 | setup_mon_len, |
b45122fd | 866 | #ifdef CONFIG_OF_CONTROL |
0879361f | 867 | fdtdec_setup, |
b45122fd | 868 | #endif |
7ef8e9b0 | 869 | #ifdef CONFIG_TRACE_EARLY |
71c52dba | 870 | trace_early_init, |
d210718d | 871 | #endif |
768e0f52 | 872 | initf_malloc, |
af1bc0cf | 873 | log_init, |
5ac44a55 | 874 | initf_bootstage, /* uses its own timer, so does not need DM */ |
f0293d33 SG |
875 | #ifdef CONFIG_BLOBLIST |
876 | bloblist_init, | |
877 | #endif | |
b0edea3c | 878 | setup_spl_handoff, |
9854a874 | 879 | initf_console_record, |
671549e5 SG |
880 | #if defined(CONFIG_HAVE_FSP) |
881 | arch_fsp_init, | |
e4fef6cf | 882 | #endif |
1938f4a5 | 883 | arch_cpu_init, /* basic arch cpu dependent setup */ |
8ebf5069 | 884 | mach_cpu_init, /* SoC/machine dependent CPU setup */ |
3ea0953d | 885 | initf_dm, |
d4c671cc | 886 | arch_cpu_init_dm, |
1938f4a5 SG |
887 | #if defined(CONFIG_BOARD_EARLY_INIT_F) |
888 | board_early_init_f, | |
889 | #endif | |
727e94a4 | 890 | #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) |
c252c068 | 891 | /* get CPU and bus clocks according to the environment variable */ |
e4fef6cf | 892 | get_clocks, /* get CPU and bus clocks (etc.) */ |
1793e782 | 893 | #endif |
0ce45287 | 894 | #if !defined(CONFIG_M68K) |
1938f4a5 | 895 | timer_init, /* initialize timer */ |
0ce45287 | 896 | #endif |
e4fef6cf SG |
897 | #if defined(CONFIG_BOARD_POSTCLK_INIT) |
898 | board_postclk_init, | |
1938f4a5 SG |
899 | #endif |
900 | env_init, /* initialize environment */ | |
901 | init_baud_rate, /* initialze baudrate settings */ | |
902 | serial_init, /* serial communications setup */ | |
903 | console_init_f, /* stage 1 init of console */ | |
904 | display_options, /* say that we are here */ | |
905 | display_text_info, /* show debugging info if required */ | |
e4fef6cf | 906 | checkcpu, |
23471aed MS |
907 | #if defined(CONFIG_SYSRESET) |
908 | print_resetinfo, | |
909 | #endif | |
cc664000 | 910 | #if defined(CONFIG_DISPLAY_CPUINFO) |
1938f4a5 | 911 | print_cpuinfo, /* display cpu info (and speed) */ |
cc664000 | 912 | #endif |
af9e6ad4 CJF |
913 | #if defined(CONFIG_DTB_RESELECT) |
914 | embedded_dtb_select, | |
915 | #endif | |
1938f4a5 | 916 | #if defined(CONFIG_DISPLAY_BOARDINFO) |
0365ffcc | 917 | show_board_info, |
e4fef6cf SG |
918 | #endif |
919 | INIT_FUNC_WATCHDOG_INIT | |
920 | #if defined(CONFIG_MISC_INIT_F) | |
921 | misc_init_f, | |
922 | #endif | |
923 | INIT_FUNC_WATCHDOG_RESET | |
69153988 | 924 | #if defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
925 | init_func_i2c, |
926 | #endif | |
1fab98fb RB |
927 | #if defined(CONFIG_VID) && !defined(CONFIG_SPL) |
928 | init_func_vid, | |
1938f4a5 SG |
929 | #endif |
930 | announce_dram_init, | |
1938f4a5 | 931 | dram_init, /* configure available RAM banks */ |
e4fef6cf SG |
932 | #ifdef CONFIG_POST |
933 | post_init_f, | |
934 | #endif | |
935 | INIT_FUNC_WATCHDOG_RESET | |
936 | #if defined(CONFIG_SYS_DRAM_TEST) | |
937 | testdram, | |
938 | #endif /* CONFIG_SYS_DRAM_TEST */ | |
939 | INIT_FUNC_WATCHDOG_RESET | |
940 | ||
1938f4a5 SG |
941 | #ifdef CONFIG_POST |
942 | init_post, | |
943 | #endif | |
e4fef6cf | 944 | INIT_FUNC_WATCHDOG_RESET |
1938f4a5 SG |
945 | /* |
946 | * Now that we have DRAM mapped and working, we can | |
947 | * relocate the code and continue running from DRAM. | |
948 | * | |
949 | * Reserve memory at end of RAM for (top down in that order): | |
950 | * - area that won't get touched by U-Boot and Linux (optional) | |
951 | * - kernel log buffer | |
952 | * - protected RAM | |
953 | * - LCD framebuffer | |
954 | * - monitor code | |
955 | * - board info struct | |
956 | */ | |
957 | setup_dest_addr, | |
1938f4a5 SG |
958 | #ifdef CONFIG_PRAM |
959 | reserve_pram, | |
960 | #endif | |
961 | reserve_round_4k, | |
79926e4f | 962 | arch_reserve_mmu, |
5a541945 | 963 | reserve_video, |
8703ef3f | 964 | reserve_trace, |
1938f4a5 SG |
965 | reserve_uboot, |
966 | reserve_malloc, | |
967 | reserve_board, | |
968 | setup_machine, | |
969 | reserve_global_data, | |
970 | reserve_fdt, | |
25e7dc6a | 971 | reserve_bootstage, |
f0293d33 | 972 | reserve_bloblist, |
146251f8 | 973 | reserve_arch, |
1938f4a5 | 974 | reserve_stacks, |
76b00aca | 975 | dram_init_banksize, |
1938f4a5 | 976 | show_dram_config, |
e2099d78 VZ |
977 | #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ |
978 | defined(CONFIG_SH) | |
e4fef6cf | 979 | setup_board_part1, |
fb3db635 DS |
980 | #endif |
981 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) | |
e4fef6cf SG |
982 | INIT_FUNC_WATCHDOG_RESET |
983 | setup_board_part2, | |
984 | #endif | |
1938f4a5 | 985 | display_new_sp, |
2a792753 | 986 | #ifdef CONFIG_OF_BOARD_FIXUP |
987 | fix_fdt, | |
e4fef6cf SG |
988 | #endif |
989 | INIT_FUNC_WATCHDOG_RESET | |
1938f4a5 | 990 | reloc_fdt, |
25e7dc6a | 991 | reloc_bootstage, |
f0293d33 | 992 | reloc_bloblist, |
1938f4a5 | 993 | setup_reloc, |
3fb80163 | 994 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
313aef37 | 995 | copy_uboot_to_ram, |
313aef37 SG |
996 | do_elf_reloc_fixups, |
997 | #endif | |
de5e5cea | 998 | clear_bss, |
530f27ea SG |
999 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ |
1000 | !CONFIG_IS_ENABLED(X86_64) | |
1938f4a5 SG |
1001 | jump_to_copy, |
1002 | #endif | |
1003 | NULL, | |
1004 | }; | |
1005 | ||
1006 | void board_init_f(ulong boot_flags) | |
1007 | { | |
1938f4a5 | 1008 | gd->flags = boot_flags; |
9aed5a27 | 1009 | gd->have_console = 0; |
1938f4a5 SG |
1010 | |
1011 | if (initcall_run_list(init_sequence_f)) | |
1012 | hang(); | |
1013 | ||
9b217498 | 1014 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ |
264d298f AB |
1015 | !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \ |
1016 | !defined(CONFIG_ARC) | |
1938f4a5 SG |
1017 | /* NOTREACHED - jump_to_copy() does not return */ |
1018 | hang(); | |
1019 | #endif | |
1020 | } | |
1021 | ||
3fb80163 | 1022 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
1023 | /* |
1024 | * For now this code is only used on x86. | |
1025 | * | |
1026 | * init_sequence_f_r is the list of init functions which are run when | |
1027 | * U-Boot is executing from Flash with a semi-limited 'C' environment. | |
1028 | * The following limitations must be considered when implementing an | |
1029 | * '_f_r' function: | |
1030 | * - 'static' variables are read-only | |
1031 | * - Global Data (gd->xxx) is read/write | |
1032 | * | |
1033 | * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if | |
1034 | * supported). It _should_, if possible, copy global data to RAM and | |
1035 | * initialise the CPU caches (to speed up the relocation process) | |
1036 | * | |
1037 | * NOTE: At present only x86 uses this route, but it is intended that | |
1038 | * all archs will move to this when generic relocation is implemented. | |
1039 | */ | |
4acff452 | 1040 | static const init_fnc_t init_sequence_f_r[] = { |
530f27ea | 1041 | #if !CONFIG_IS_ENABLED(X86_64) |
48a33806 | 1042 | init_cache_f_r, |
530f27ea | 1043 | #endif |
48a33806 SG |
1044 | |
1045 | NULL, | |
1046 | }; | |
1047 | ||
1048 | void board_init_f_r(void) | |
1049 | { | |
1050 | if (initcall_run_list(init_sequence_f_r)) | |
1051 | hang(); | |
1052 | ||
e4d6ab0c SG |
1053 | /* |
1054 | * The pre-relocation drivers may be using memory that has now gone | |
1055 | * away. Mark serial as unavailable - this will fall back to the debug | |
1056 | * UART if available. | |
af1bc0cf SG |
1057 | * |
1058 | * Do the same with log drivers since the memory may not be available. | |
e4d6ab0c | 1059 | */ |
af1bc0cf | 1060 | gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); |
5ee94b4f SG |
1061 | #ifdef CONFIG_TIMER |
1062 | gd->timer = NULL; | |
1063 | #endif | |
e4d6ab0c | 1064 | |
48a33806 SG |
1065 | /* |
1066 | * U-Boot has been copied into SDRAM, the BSS has been cleared etc. | |
1067 | * Transfer execution from Flash to RAM by calculating the address | |
1068 | * of the in-RAM copy of board_init_r() and calling it | |
1069 | */ | |
7bf9f20d | 1070 | (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); |
48a33806 SG |
1071 | |
1072 | /* NOTREACHED - board_init_r() does not return */ | |
1073 | hang(); | |
1074 | } | |
5bcd19aa | 1075 | #endif /* CONFIG_X86 */ |