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Commit | Line | Data |
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1938f4a5 SG |
1 | /* |
2 | * Copyright (c) 2011 The Chromium OS Authors. | |
3 | * (C) Copyright 2002-2006 | |
4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 | * Marius Groeger <mgroeger@sysgo.de> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
1938f4a5 SG |
11 | */ |
12 | ||
13 | #include <common.h> | |
14 | #include <linux/compiler.h> | |
15 | #include <version.h> | |
24b852a7 | 16 | #include <console.h> |
1938f4a5 | 17 | #include <environment.h> |
ab7cd627 | 18 | #include <dm.h> |
1938f4a5 | 19 | #include <fdtdec.h> |
f828bf25 | 20 | #include <fs.h> |
e4fef6cf SG |
21 | #if defined(CONFIG_CMD_IDE) |
22 | #include <ide.h> | |
23 | #endif | |
24 | #include <i2c.h> | |
1938f4a5 SG |
25 | #include <initcall.h> |
26 | #include <logbuff.h> | |
fb5cf7f1 | 27 | #include <malloc.h> |
0eb25b61 | 28 | #include <mapmem.h> |
e4fef6cf SG |
29 | |
30 | /* TODO: Can we move these into arch/ headers? */ | |
31 | #ifdef CONFIG_8xx | |
32 | #include <mpc8xx.h> | |
33 | #endif | |
34 | #ifdef CONFIG_5xx | |
35 | #include <mpc5xx.h> | |
36 | #endif | |
37 | #ifdef CONFIG_MPC5xxx | |
38 | #include <mpc5xxx.h> | |
39 | #endif | |
ec3b4820 | 40 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
a76df709 GH |
41 | #include <asm/mp.h> |
42 | #endif | |
e4fef6cf | 43 | |
a733b06b | 44 | #include <os.h> |
1938f4a5 | 45 | #include <post.h> |
e4fef6cf | 46 | #include <spi.h> |
c5d4001a | 47 | #include <status_led.h> |
71c52dba | 48 | #include <trace.h> |
e4fef6cf | 49 | #include <watchdog.h> |
a733b06b | 50 | #include <asm/errno.h> |
1938f4a5 SG |
51 | #include <asm/io.h> |
52 | #include <asm/sections.h> | |
3fb80163 | 53 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
54 | #include <asm/init_helpers.h> |
55 | #include <asm/relocate.h> | |
56 | #endif | |
a733b06b SG |
57 | #ifdef CONFIG_SANDBOX |
58 | #include <asm/state.h> | |
59 | #endif | |
ab7cd627 | 60 | #include <dm/root.h> |
1938f4a5 SG |
61 | #include <linux/compiler.h> |
62 | ||
63 | /* | |
64 | * Pointer to initial global data area | |
65 | * | |
66 | * Here we initialize it if needed. | |
67 | */ | |
68 | #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR | |
69 | #undef XTRN_DECLARE_GLOBAL_DATA_PTR | |
70 | #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ | |
71 | DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); | |
72 | #else | |
73 | DECLARE_GLOBAL_DATA_PTR; | |
74 | #endif | |
75 | ||
76 | /* | |
4c509343 | 77 | * TODO(sjg@chromium.org): IMO this code should be |
1938f4a5 SG |
78 | * refactored to a single function, something like: |
79 | * | |
80 | * void led_set_state(enum led_colour_t colour, int on); | |
81 | */ | |
82 | /************************************************************************ | |
83 | * Coloured LED functionality | |
84 | ************************************************************************ | |
85 | * May be supplied by boards if desired | |
86 | */ | |
c5d4001a JH |
87 | __weak void coloured_LED_init(void) {} |
88 | __weak void red_led_on(void) {} | |
89 | __weak void red_led_off(void) {} | |
90 | __weak void green_led_on(void) {} | |
91 | __weak void green_led_off(void) {} | |
92 | __weak void yellow_led_on(void) {} | |
93 | __weak void yellow_led_off(void) {} | |
94 | __weak void blue_led_on(void) {} | |
95 | __weak void blue_led_off(void) {} | |
1938f4a5 SG |
96 | |
97 | /* | |
98 | * Why is gd allocated a register? Prior to reloc it might be better to | |
99 | * just pass it around to each function in this file? | |
100 | * | |
101 | * After reloc one could argue that it is hardly used and doesn't need | |
102 | * to be in a register. Or if it is it should perhaps hold pointers to all | |
103 | * global data for all modules, so that post-reloc we can avoid the massive | |
104 | * literal pool we get on ARM. Or perhaps just encourage each module to use | |
105 | * a structure... | |
106 | */ | |
107 | ||
108 | /* | |
109 | * Could the CONFIG_SPL_BUILD infection become a flag in gd? | |
110 | */ | |
111 | ||
d54d7eb9 | 112 | #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) |
e4fef6cf SG |
113 | static int init_func_watchdog_init(void) |
114 | { | |
d54d7eb9 SZ |
115 | # if defined(CONFIG_HW_WATCHDOG) && (defined(CONFIG_BLACKFIN) || \ |
116 | defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ | |
14a380a8 SR |
117 | defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ |
118 | defined(CONFIG_IMX_WATCHDOG)) | |
d54d7eb9 SZ |
119 | hw_watchdog_init(); |
120 | # endif | |
e4fef6cf SG |
121 | puts(" Watchdog enabled\n"); |
122 | WATCHDOG_RESET(); | |
123 | ||
124 | return 0; | |
125 | } | |
126 | ||
127 | int init_func_watchdog_reset(void) | |
128 | { | |
129 | WATCHDOG_RESET(); | |
130 | ||
131 | return 0; | |
132 | } | |
133 | #endif /* CONFIG_WATCHDOG */ | |
134 | ||
dd2a6cd0 | 135 | __weak void board_add_ram_info(int use_default) |
e4fef6cf SG |
136 | { |
137 | /* please define platform specific board_add_ram_info() */ | |
138 | } | |
139 | ||
1938f4a5 SG |
140 | static int init_baud_rate(void) |
141 | { | |
142 | gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); | |
143 | return 0; | |
144 | } | |
145 | ||
146 | static int display_text_info(void) | |
147 | { | |
9b217498 | 148 | #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) |
9fdee7d7 | 149 | ulong bss_start, bss_end, text_base; |
1938f4a5 | 150 | |
632efa74 SG |
151 | bss_start = (ulong)&__bss_start; |
152 | bss_end = (ulong)&__bss_end; | |
b60eff31 | 153 | |
d54d7eb9 | 154 | #ifdef CONFIG_SYS_TEXT_BASE |
9fdee7d7 | 155 | text_base = CONFIG_SYS_TEXT_BASE; |
d54d7eb9 | 156 | #else |
9fdee7d7 | 157 | text_base = CONFIG_SYS_MONITOR_BASE; |
d54d7eb9 | 158 | #endif |
9fdee7d7 DS |
159 | |
160 | debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", | |
161 | text_base, bss_start, bss_end); | |
a733b06b | 162 | #endif |
1938f4a5 SG |
163 | |
164 | #ifdef CONFIG_MODEM_SUPPORT | |
165 | debug("Modem Support enabled\n"); | |
166 | #endif | |
167 | #ifdef CONFIG_USE_IRQ | |
168 | debug("IRQ Stack: %08lx\n", IRQ_STACK_START); | |
169 | debug("FIQ Stack: %08lx\n", FIQ_STACK_START); | |
170 | #endif | |
171 | ||
172 | return 0; | |
173 | } | |
174 | ||
175 | static int announce_dram_init(void) | |
176 | { | |
177 | puts("DRAM: "); | |
178 | return 0; | |
179 | } | |
180 | ||
e310b93e | 181 | #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
182 | static int init_func_ram(void) |
183 | { | |
184 | #ifdef CONFIG_BOARD_TYPES | |
185 | int board_type = gd->board_type; | |
186 | #else | |
187 | int board_type = 0; /* use dummy arg */ | |
188 | #endif | |
189 | ||
190 | gd->ram_size = initdram(board_type); | |
191 | ||
192 | if (gd->ram_size > 0) | |
193 | return 0; | |
194 | ||
195 | puts("*** failed ***\n"); | |
196 | return 1; | |
197 | } | |
198 | #endif | |
199 | ||
1938f4a5 SG |
200 | static int show_dram_config(void) |
201 | { | |
fa39ffe5 | 202 | unsigned long long size; |
1938f4a5 SG |
203 | |
204 | #ifdef CONFIG_NR_DRAM_BANKS | |
205 | int i; | |
206 | ||
207 | debug("\nRAM Configuration:\n"); | |
208 | for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
209 | size += gd->bd->bi_dram[i].size; | |
715f599f BM |
210 | debug("Bank #%d: %llx ", i, |
211 | (unsigned long long)(gd->bd->bi_dram[i].start)); | |
1938f4a5 SG |
212 | #ifdef DEBUG |
213 | print_size(gd->bd->bi_dram[i].size, "\n"); | |
214 | #endif | |
215 | } | |
216 | debug("\nDRAM: "); | |
217 | #else | |
218 | size = gd->ram_size; | |
219 | #endif | |
220 | ||
e4fef6cf SG |
221 | print_size(size, ""); |
222 | board_add_ram_info(0); | |
223 | putc('\n'); | |
1938f4a5 SG |
224 | |
225 | return 0; | |
226 | } | |
227 | ||
dd2a6cd0 | 228 | __weak void dram_init_banksize(void) |
1938f4a5 SG |
229 | { |
230 | #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) | |
231 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
232 | gd->bd->bi_dram[0].size = get_effective_memsize(); | |
233 | #endif | |
234 | } | |
235 | ||
ea818dbb | 236 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
237 | static int init_func_i2c(void) |
238 | { | |
239 | puts("I2C: "); | |
815a76f2 | 240 | #ifdef CONFIG_SYS_I2C |
241 | i2c_init_all(); | |
242 | #else | |
e4fef6cf | 243 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
815a76f2 | 244 | #endif |
e4fef6cf SG |
245 | puts("ready\n"); |
246 | return 0; | |
247 | } | |
248 | #endif | |
249 | ||
250 | #if defined(CONFIG_HARD_SPI) | |
251 | static int init_func_spi(void) | |
252 | { | |
253 | puts("SPI: "); | |
254 | spi_init(); | |
255 | puts("ready\n"); | |
256 | return 0; | |
257 | } | |
258 | #endif | |
259 | ||
260 | __maybe_unused | |
1938f4a5 SG |
261 | static int zero_global_data(void) |
262 | { | |
263 | memset((void *)gd, '\0', sizeof(gd_t)); | |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
268 | static int setup_mon_len(void) | |
269 | { | |
e945f6dc | 270 | #if defined(__ARM__) || defined(__MICROBLAZE__) |
b60eff31 | 271 | gd->mon_len = (ulong)&__bss_end - (ulong)_start; |
9b217498 | 272 | #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) |
a733b06b | 273 | gd->mon_len = (ulong)&_end - (ulong)_init; |
5ff10aa7 | 274 | #elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) |
d54d7eb9 | 275 | gd->mon_len = CONFIG_SYS_MONITOR_LEN; |
2e88bb28 KHH |
276 | #elif defined(CONFIG_NDS32) |
277 | gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); | |
632efa74 | 278 | #else |
e4fef6cf SG |
279 | /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ |
280 | gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; | |
632efa74 | 281 | #endif |
1938f4a5 SG |
282 | return 0; |
283 | } | |
284 | ||
285 | __weak int arch_cpu_init(void) | |
286 | { | |
287 | return 0; | |
288 | } | |
289 | ||
a733b06b SG |
290 | #ifdef CONFIG_SANDBOX |
291 | static int setup_ram_buf(void) | |
292 | { | |
5c2859cd SG |
293 | struct sandbox_state *state = state_get_current(); |
294 | ||
295 | gd->arch.ram_buf = state->ram_buf; | |
296 | gd->ram_size = state->ram_size; | |
a733b06b SG |
297 | |
298 | return 0; | |
299 | } | |
300 | #endif | |
301 | ||
1938f4a5 SG |
302 | /* Get the top of usable RAM */ |
303 | __weak ulong board_get_usable_ram_top(ulong total_size) | |
304 | { | |
1e4d11a5 SW |
305 | #ifdef CONFIG_SYS_SDRAM_BASE |
306 | /* | |
4c509343 | 307 | * Detect whether we have so much RAM that it goes past the end of our |
1e4d11a5 SW |
308 | * 32-bit address space. If so, clip the usable RAM so it doesn't. |
309 | */ | |
310 | if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) | |
311 | /* | |
312 | * Will wrap back to top of 32-bit space when reservations | |
313 | * are made. | |
314 | */ | |
315 | return 0; | |
316 | #endif | |
1938f4a5 SG |
317 | return gd->ram_top; |
318 | } | |
319 | ||
320 | static int setup_dest_addr(void) | |
321 | { | |
322 | debug("Monitor len: %08lX\n", gd->mon_len); | |
323 | /* | |
324 | * Ram is setup, size stored in gd !! | |
325 | */ | |
326 | debug("Ram size: %08lX\n", (ulong)gd->ram_size); | |
327 | #if defined(CONFIG_SYS_MEM_TOP_HIDE) | |
328 | /* | |
329 | * Subtract specified amount of memory to hide so that it won't | |
330 | * get "touched" at all by U-Boot. By fixing up gd->ram_size | |
331 | * the Linux kernel should now get passed the now "corrected" | |
332 | * memory size and won't touch it either. This should work | |
333 | * for arch/ppc and arch/powerpc. Only Linux board ports in | |
334 | * arch/powerpc with bootwrapper support, that recalculate the | |
335 | * memory size from the SDRAM controller setup will have to | |
336 | * get fixed. | |
337 | */ | |
338 | gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; | |
339 | #endif | |
340 | #ifdef CONFIG_SYS_SDRAM_BASE | |
341 | gd->ram_top = CONFIG_SYS_SDRAM_BASE; | |
342 | #endif | |
e4fef6cf | 343 | gd->ram_top += get_effective_memsize(); |
1938f4a5 | 344 | gd->ram_top = board_get_usable_ram_top(gd->mon_len); |
a0ba279a | 345 | gd->relocaddr = gd->ram_top; |
1938f4a5 | 346 | debug("Ram top: %08lX\n", (ulong)gd->ram_top); |
ec3b4820 | 347 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
e4fef6cf SG |
348 | /* |
349 | * We need to make sure the location we intend to put secondary core | |
350 | * boot code is reserved and not used by any part of u-boot | |
351 | */ | |
a0ba279a MY |
352 | if (gd->relocaddr > determine_mp_bootpg(NULL)) { |
353 | gd->relocaddr = determine_mp_bootpg(NULL); | |
354 | debug("Reserving MP boot page to %08lx\n", gd->relocaddr); | |
e4fef6cf SG |
355 | } |
356 | #endif | |
1938f4a5 SG |
357 | return 0; |
358 | } | |
359 | ||
360 | #if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) | |
361 | static int reserve_logbuffer(void) | |
362 | { | |
363 | /* reserve kernel log buffer */ | |
a0ba279a | 364 | gd->relocaddr -= LOGBUFF_RESERVE; |
1938f4a5 | 365 | debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, |
a0ba279a | 366 | gd->relocaddr); |
1938f4a5 SG |
367 | return 0; |
368 | } | |
369 | #endif | |
370 | ||
371 | #ifdef CONFIG_PRAM | |
372 | /* reserve protected RAM */ | |
373 | static int reserve_pram(void) | |
374 | { | |
375 | ulong reg; | |
376 | ||
377 | reg = getenv_ulong("pram", 10, CONFIG_PRAM); | |
a0ba279a | 378 | gd->relocaddr -= (reg << 10); /* size is in kB */ |
1938f4a5 | 379 | debug("Reserving %ldk for protected RAM at %08lx\n", reg, |
a0ba279a | 380 | gd->relocaddr); |
1938f4a5 SG |
381 | return 0; |
382 | } | |
383 | #endif /* CONFIG_PRAM */ | |
384 | ||
385 | /* Round memory pointer down to next 4 kB limit */ | |
386 | static int reserve_round_4k(void) | |
387 | { | |
a0ba279a | 388 | gd->relocaddr &= ~(4096 - 1); |
1938f4a5 SG |
389 | return 0; |
390 | } | |
391 | ||
392 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ | |
393 | defined(CONFIG_ARM) | |
394 | static int reserve_mmu(void) | |
395 | { | |
396 | /* reserve TLB table */ | |
cce6be7f | 397 | gd->arch.tlb_size = PGTABLE_SIZE; |
a0ba279a | 398 | gd->relocaddr -= gd->arch.tlb_size; |
1938f4a5 SG |
399 | |
400 | /* round down to next 64 kB limit */ | |
a0ba279a | 401 | gd->relocaddr &= ~(0x10000 - 1); |
1938f4a5 | 402 | |
a0ba279a | 403 | gd->arch.tlb_addr = gd->relocaddr; |
1938f4a5 SG |
404 | debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, |
405 | gd->arch.tlb_addr + gd->arch.tlb_size); | |
406 | return 0; | |
407 | } | |
408 | #endif | |
409 | ||
410 | #ifdef CONFIG_LCD | |
411 | static int reserve_lcd(void) | |
412 | { | |
413 | #ifdef CONFIG_FB_ADDR | |
414 | gd->fb_base = CONFIG_FB_ADDR; | |
415 | #else | |
416 | /* reserve memory for LCD display (always full pages) */ | |
a0ba279a MY |
417 | gd->relocaddr = lcd_setmem(gd->relocaddr); |
418 | gd->fb_base = gd->relocaddr; | |
1938f4a5 SG |
419 | #endif /* CONFIG_FB_ADDR */ |
420 | return 0; | |
421 | } | |
422 | #endif /* CONFIG_LCD */ | |
423 | ||
71c52dba SG |
424 | static int reserve_trace(void) |
425 | { | |
426 | #ifdef CONFIG_TRACE | |
427 | gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; | |
428 | gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); | |
429 | debug("Reserving %dk for trace data at: %08lx\n", | |
430 | CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); | |
431 | #endif | |
432 | ||
433 | return 0; | |
434 | } | |
435 | ||
d54d7eb9 SZ |
436 | #if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ |
437 | !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ | |
944ab340 | 438 | !defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K) |
e4fef6cf SG |
439 | static int reserve_video(void) |
440 | { | |
441 | /* reserve memory for video display (always full pages) */ | |
a0ba279a MY |
442 | gd->relocaddr = video_setmem(gd->relocaddr); |
443 | gd->fb_base = gd->relocaddr; | |
e4fef6cf SG |
444 | |
445 | return 0; | |
446 | } | |
447 | #endif | |
448 | ||
1938f4a5 SG |
449 | static int reserve_uboot(void) |
450 | { | |
451 | /* | |
452 | * reserve memory for U-Boot code, data & bss | |
453 | * round down to next 4 kB limit | |
454 | */ | |
a0ba279a MY |
455 | gd->relocaddr -= gd->mon_len; |
456 | gd->relocaddr &= ~(4096 - 1); | |
e4fef6cf SG |
457 | #ifdef CONFIG_E500 |
458 | /* round down to next 64 kB limit so that IVPR stays aligned */ | |
a0ba279a | 459 | gd->relocaddr &= ~(65536 - 1); |
e4fef6cf | 460 | #endif |
1938f4a5 SG |
461 | |
462 | debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, | |
a0ba279a MY |
463 | gd->relocaddr); |
464 | ||
465 | gd->start_addr_sp = gd->relocaddr; | |
466 | ||
1938f4a5 SG |
467 | return 0; |
468 | } | |
469 | ||
8cae8a68 | 470 | #ifndef CONFIG_SPL_BUILD |
1938f4a5 SG |
471 | /* reserve memory for malloc() area */ |
472 | static int reserve_malloc(void) | |
473 | { | |
a0ba279a | 474 | gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; |
1938f4a5 | 475 | debug("Reserving %dk for malloc() at: %08lx\n", |
a0ba279a | 476 | TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); |
1938f4a5 SG |
477 | return 0; |
478 | } | |
479 | ||
480 | /* (permanently) allocate a Board Info struct */ | |
481 | static int reserve_board(void) | |
482 | { | |
d54d7eb9 SZ |
483 | if (!gd->bd) { |
484 | gd->start_addr_sp -= sizeof(bd_t); | |
485 | gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); | |
486 | memset(gd->bd, '\0', sizeof(bd_t)); | |
487 | debug("Reserving %zu Bytes for Board Info at: %08lx\n", | |
488 | sizeof(bd_t), gd->start_addr_sp); | |
489 | } | |
1938f4a5 SG |
490 | return 0; |
491 | } | |
8cae8a68 | 492 | #endif |
1938f4a5 SG |
493 | |
494 | static int setup_machine(void) | |
495 | { | |
496 | #ifdef CONFIG_MACH_TYPE | |
497 | gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ | |
498 | #endif | |
499 | return 0; | |
500 | } | |
501 | ||
502 | static int reserve_global_data(void) | |
503 | { | |
a0ba279a MY |
504 | gd->start_addr_sp -= sizeof(gd_t); |
505 | gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); | |
1938f4a5 | 506 | debug("Reserving %zu Bytes for Global Data at: %08lx\n", |
a0ba279a | 507 | sizeof(gd_t), gd->start_addr_sp); |
1938f4a5 SG |
508 | return 0; |
509 | } | |
510 | ||
511 | static int reserve_fdt(void) | |
512 | { | |
513 | /* | |
4c509343 | 514 | * If the device tree is sitting immediately above our image then we |
1938f4a5 SG |
515 | * must relocate it. If it is embedded in the data section, then it |
516 | * will be relocated with other data. | |
517 | */ | |
518 | if (gd->fdt_blob) { | |
519 | gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); | |
520 | ||
a0ba279a MY |
521 | gd->start_addr_sp -= gd->fdt_size; |
522 | gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); | |
a733b06b | 523 | debug("Reserving %lu Bytes for FDT at: %08lx\n", |
a0ba279a | 524 | gd->fdt_size, gd->start_addr_sp); |
1938f4a5 SG |
525 | } |
526 | ||
527 | return 0; | |
528 | } | |
529 | ||
68145d4c | 530 | int arch_reserve_stacks(void) |
1938f4a5 | 531 | { |
68145d4c AB |
532 | return 0; |
533 | } | |
8cae8a68 | 534 | |
68145d4c AB |
535 | static int reserve_stacks(void) |
536 | { | |
537 | /* make stack pointer 16-byte aligned */ | |
a0ba279a MY |
538 | gd->start_addr_sp -= 16; |
539 | gd->start_addr_sp &= ~0xf; | |
1938f4a5 SG |
540 | |
541 | /* | |
4c509343 | 542 | * let the architecture-specific code tailor gd->start_addr_sp and |
68145d4c | 543 | * gd->irq_sp |
1938f4a5 | 544 | */ |
68145d4c | 545 | return arch_reserve_stacks(); |
1938f4a5 SG |
546 | } |
547 | ||
548 | static int display_new_sp(void) | |
549 | { | |
a0ba279a | 550 | debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); |
1938f4a5 SG |
551 | |
552 | return 0; | |
553 | } | |
554 | ||
fb3db635 | 555 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS) |
e4fef6cf SG |
556 | static int setup_board_part1(void) |
557 | { | |
558 | bd_t *bd = gd->bd; | |
559 | ||
560 | /* | |
561 | * Save local variables to board info struct | |
562 | */ | |
e4fef6cf SG |
563 | bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ |
564 | bd->bi_memsize = gd->ram_size; /* size in bytes */ | |
565 | ||
566 | #ifdef CONFIG_SYS_SRAM_BASE | |
567 | bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ | |
568 | bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ | |
569 | #endif | |
570 | ||
58dac327 | 571 | #if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ |
e4fef6cf SG |
572 | defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
573 | bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ | |
574 | #endif | |
e310b93e | 575 | #if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) |
e4fef6cf SG |
576 | bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ |
577 | #endif | |
578 | #if defined(CONFIG_MPC83xx) | |
579 | bd->bi_immrbar = CONFIG_SYS_IMMR; | |
580 | #endif | |
e4fef6cf SG |
581 | |
582 | return 0; | |
583 | } | |
fb3db635 | 584 | #endif |
e4fef6cf | 585 | |
fb3db635 | 586 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
587 | static int setup_board_part2(void) |
588 | { | |
589 | bd_t *bd = gd->bd; | |
590 | ||
591 | bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ | |
592 | bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ | |
593 | #if defined(CONFIG_CPM2) | |
594 | bd->bi_cpmfreq = gd->arch.cpm_clk; | |
595 | bd->bi_brgfreq = gd->arch.brg_clk; | |
596 | bd->bi_sccfreq = gd->arch.scc_clk; | |
597 | bd->bi_vco = gd->arch.vco_out; | |
598 | #endif /* CONFIG_CPM2 */ | |
599 | #if defined(CONFIG_MPC512X) | |
600 | bd->bi_ipsfreq = gd->arch.ips_clk; | |
601 | #endif /* CONFIG_MPC512X */ | |
602 | #if defined(CONFIG_MPC5xxx) | |
603 | bd->bi_ipbfreq = gd->arch.ipb_clk; | |
604 | bd->bi_pcifreq = gd->pci_clk; | |
605 | #endif /* CONFIG_MPC5xxx */ | |
1313db48 AW |
606 | #if defined(CONFIG_M68K) && defined(CONFIG_PCI) |
607 | bd->bi_pcifreq = gd->pci_clk; | |
608 | #endif | |
609 | #if defined(CONFIG_EXTRA_CLOCK) | |
610 | bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ | |
611 | bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ | |
612 | bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ | |
613 | #endif | |
e4fef6cf SG |
614 | |
615 | return 0; | |
616 | } | |
617 | #endif | |
618 | ||
619 | #ifdef CONFIG_SYS_EXTBDINFO | |
620 | static int setup_board_extra(void) | |
621 | { | |
622 | bd_t *bd = gd->bd; | |
623 | ||
624 | strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); | |
625 | strncpy((char *) bd->bi_r_version, U_BOOT_VERSION, | |
626 | sizeof(bd->bi_r_version)); | |
627 | ||
628 | bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ | |
629 | bd->bi_plb_busfreq = gd->bus_clk; | |
630 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ | |
631 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | |
632 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
633 | bd->bi_pci_busfreq = get_PCI_freq(); | |
634 | bd->bi_opbfreq = get_OPB_freq(); | |
635 | #elif defined(CONFIG_XILINX_405) | |
636 | bd->bi_pci_busfreq = get_PCI_freq(); | |
637 | #endif | |
638 | ||
639 | return 0; | |
640 | } | |
641 | #endif | |
642 | ||
1938f4a5 SG |
643 | #ifdef CONFIG_POST |
644 | static int init_post(void) | |
645 | { | |
646 | post_bootmode_init(); | |
647 | post_run(NULL, POST_ROM | post_bootmode_get(0)); | |
648 | ||
649 | return 0; | |
650 | } | |
651 | #endif | |
652 | ||
1938f4a5 SG |
653 | static int setup_dram_config(void) |
654 | { | |
655 | /* Ram is board specific, so move it to board code ... */ | |
656 | dram_init_banksize(); | |
657 | ||
658 | return 0; | |
659 | } | |
660 | ||
661 | static int reloc_fdt(void) | |
662 | { | |
f05ad9ba SG |
663 | if (gd->flags & GD_FLG_SKIP_RELOC) |
664 | return 0; | |
1938f4a5 SG |
665 | if (gd->new_fdt) { |
666 | memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); | |
667 | gd->fdt_blob = gd->new_fdt; | |
668 | } | |
669 | ||
670 | return 0; | |
671 | } | |
672 | ||
673 | static int setup_reloc(void) | |
674 | { | |
f05ad9ba SG |
675 | if (gd->flags & GD_FLG_SKIP_RELOC) { |
676 | debug("Skipping relocation due to flag\n"); | |
677 | return 0; | |
678 | } | |
679 | ||
d54d7eb9 | 680 | #ifdef CONFIG_SYS_TEXT_BASE |
a0ba279a | 681 | gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; |
e310b93e | 682 | #ifdef CONFIG_M68K |
683 | /* | |
684 | * On all ColdFire arch cpu, monitor code starts always | |
685 | * just after the default vector table location, so at 0x400 | |
686 | */ | |
687 | gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); | |
688 | #endif | |
d54d7eb9 | 689 | #endif |
1938f4a5 SG |
690 | memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); |
691 | ||
692 | debug("Relocation Offset is: %08lx\n", gd->reloc_off); | |
a733b06b | 693 | debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", |
a0ba279a MY |
694 | gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), |
695 | gd->start_addr_sp); | |
1938f4a5 SG |
696 | |
697 | return 0; | |
698 | } | |
699 | ||
700 | /* ARM calls relocate_code from its crt0.S */ | |
808434cd | 701 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
702 | |
703 | static int jump_to_copy(void) | |
704 | { | |
f05ad9ba SG |
705 | if (gd->flags & GD_FLG_SKIP_RELOC) |
706 | return 0; | |
48a33806 SG |
707 | /* |
708 | * x86 is special, but in a nice way. It uses a trampoline which | |
709 | * enables the dcache if possible. | |
710 | * | |
711 | * For now, other archs use relocate_code(), which is implemented | |
712 | * similarly for all archs. When we do generic relocation, hopefully | |
713 | * we can make all archs enable the dcache prior to relocation. | |
714 | */ | |
3fb80163 | 715 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
716 | /* |
717 | * SDRAM and console are now initialised. The final stack can now | |
718 | * be setup in SDRAM. Code execution will continue in Flash, but | |
719 | * with the stack in SDRAM and Global Data in temporary memory | |
720 | * (CPU cache) | |
721 | */ | |
f0c7d9c7 | 722 | arch_setup_gd(gd->new_gd); |
48a33806 SG |
723 | board_init_f_r_trampoline(gd->start_addr_sp); |
724 | #else | |
a0ba279a | 725 | relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); |
48a33806 | 726 | #endif |
1938f4a5 SG |
727 | |
728 | return 0; | |
729 | } | |
730 | #endif | |
731 | ||
732 | /* Record the board_init_f() bootstage (after arch_cpu_init()) */ | |
733 | static int mark_bootstage(void) | |
734 | { | |
735 | bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); | |
736 | ||
737 | return 0; | |
738 | } | |
739 | ||
ab7cd627 SG |
740 | static int initf_dm(void) |
741 | { | |
742 | #if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN) | |
743 | int ret; | |
744 | ||
745 | ret = dm_init_and_scan(true); | |
746 | if (ret) | |
747 | return ret; | |
748 | #endif | |
749 | ||
750 | return 0; | |
751 | } | |
752 | ||
146251f8 SG |
753 | /* Architecture-specific memory reservation */ |
754 | __weak int reserve_arch(void) | |
755 | { | |
756 | return 0; | |
757 | } | |
758 | ||
d4c671cc SG |
759 | __weak int arch_cpu_init_dm(void) |
760 | { | |
761 | return 0; | |
762 | } | |
763 | ||
1938f4a5 | 764 | static init_fnc_t init_sequence_f[] = { |
a733b06b SG |
765 | #ifdef CONFIG_SANDBOX |
766 | setup_ram_buf, | |
e4fef6cf | 767 | #endif |
1938f4a5 | 768 | setup_mon_len, |
b45122fd | 769 | #ifdef CONFIG_OF_CONTROL |
0879361f | 770 | fdtdec_setup, |
b45122fd | 771 | #endif |
d210718d | 772 | #ifdef CONFIG_TRACE |
71c52dba | 773 | trace_early_init, |
d210718d | 774 | #endif |
768e0f52 | 775 | initf_malloc, |
e4fef6cf SG |
776 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) |
777 | /* TODO: can this go into arch_cpu_init()? */ | |
778 | probecpu, | |
a52a068e BM |
779 | #endif |
780 | #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP) | |
781 | x86_fsp_init, | |
e4fef6cf | 782 | #endif |
1938f4a5 | 783 | arch_cpu_init, /* basic arch cpu dependent setup */ |
3ea0953d | 784 | initf_dm, |
d4c671cc | 785 | arch_cpu_init_dm, |
67521957 | 786 | mark_bootstage, /* need timer, go after init dm */ |
1938f4a5 SG |
787 | #if defined(CONFIG_BOARD_EARLY_INIT_F) |
788 | board_early_init_f, | |
789 | #endif | |
e4fef6cf SG |
790 | /* TODO: can any of this go into arch_cpu_init()? */ |
791 | #if defined(CONFIG_PPC) && !defined(CONFIG_8xx_CPUCLK_DEFAULT) | |
792 | get_clocks, /* get CPU and bus clocks (etc.) */ | |
793 | #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ | |
794 | && !defined(CONFIG_TQM885D) | |
795 | adjust_sdram_tbs_8xx, | |
796 | #endif | |
797 | /* TODO: can we rename this to timer_init()? */ | |
798 | init_timebase, | |
799 | #endif | |
643b0f75 | 800 | #if defined(CONFIG_X86) || defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \ |
a54915d8 | 801 | defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) |
1938f4a5 | 802 | timer_init, /* initialize timer */ |
e4fef6cf | 803 | #endif |
e4fef6cf SG |
804 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
805 | #if !defined(CONFIG_CPM2) | |
806 | dpram_init, | |
807 | #endif | |
808 | #endif | |
809 | #if defined(CONFIG_BOARD_POSTCLK_INIT) | |
810 | board_postclk_init, | |
b8521b74 | 811 | #endif |
7664846b | 812 | #if defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) |
e310b93e | 813 | get_clocks, |
1938f4a5 SG |
814 | #endif |
815 | env_init, /* initialize environment */ | |
e4fef6cf SG |
816 | #if defined(CONFIG_8xx_CPUCLK_DEFAULT) |
817 | /* get CPU and bus clocks according to the environment variable */ | |
818 | get_clocks_866, | |
819 | /* adjust sdram refresh rate according to the new clock */ | |
820 | sdram_adjust_866, | |
821 | init_timebase, | |
822 | #endif | |
1938f4a5 SG |
823 | init_baud_rate, /* initialze baudrate settings */ |
824 | serial_init, /* serial communications setup */ | |
825 | console_init_f, /* stage 1 init of console */ | |
a733b06b SG |
826 | #ifdef CONFIG_SANDBOX |
827 | sandbox_early_getopt_check, | |
828 | #endif | |
829 | #ifdef CONFIG_OF_CONTROL | |
830 | fdtdec_prepare_fdt, | |
48a33806 | 831 | #endif |
1938f4a5 SG |
832 | display_options, /* say that we are here */ |
833 | display_text_info, /* show debugging info if required */ | |
58dac327 | 834 | #if defined(CONFIG_MPC8260) |
e4fef6cf SG |
835 | prt_8260_rsr, |
836 | prt_8260_clks, | |
58dac327 | 837 | #endif /* CONFIG_MPC8260 */ |
e4fef6cf SG |
838 | #if defined(CONFIG_MPC83xx) |
839 | prt_83xx_rsr, | |
840 | #endif | |
e310b93e | 841 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
842 | checkcpu, |
843 | #endif | |
1938f4a5 | 844 | print_cpuinfo, /* display cpu info (and speed) */ |
e4fef6cf SG |
845 | #if defined(CONFIG_MPC5xxx) |
846 | prt_mpc5xxx_clks, | |
847 | #endif /* CONFIG_MPC5xxx */ | |
1938f4a5 | 848 | #if defined(CONFIG_DISPLAY_BOARDINFO) |
0365ffcc | 849 | show_board_info, |
e4fef6cf SG |
850 | #endif |
851 | INIT_FUNC_WATCHDOG_INIT | |
852 | #if defined(CONFIG_MISC_INIT_F) | |
853 | misc_init_f, | |
854 | #endif | |
855 | INIT_FUNC_WATCHDOG_RESET | |
ea818dbb | 856 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
e4fef6cf SG |
857 | init_func_i2c, |
858 | #endif | |
859 | #if defined(CONFIG_HARD_SPI) | |
860 | init_func_spi, | |
1938f4a5 SG |
861 | #endif |
862 | announce_dram_init, | |
863 | /* TODO: unify all these dram functions? */ | |
2e88bb28 KHH |
864 | #if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_NDS32) || \ |
865 | defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) | |
1938f4a5 SG |
866 | dram_init, /* configure available RAM banks */ |
867 | #endif | |
e310b93e | 868 | #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K) |
e4fef6cf SG |
869 | init_func_ram, |
870 | #endif | |
871 | #ifdef CONFIG_POST | |
872 | post_init_f, | |
873 | #endif | |
874 | INIT_FUNC_WATCHDOG_RESET | |
875 | #if defined(CONFIG_SYS_DRAM_TEST) | |
876 | testdram, | |
877 | #endif /* CONFIG_SYS_DRAM_TEST */ | |
878 | INIT_FUNC_WATCHDOG_RESET | |
879 | ||
1938f4a5 SG |
880 | #ifdef CONFIG_POST |
881 | init_post, | |
882 | #endif | |
e4fef6cf | 883 | INIT_FUNC_WATCHDOG_RESET |
1938f4a5 SG |
884 | /* |
885 | * Now that we have DRAM mapped and working, we can | |
886 | * relocate the code and continue running from DRAM. | |
887 | * | |
888 | * Reserve memory at end of RAM for (top down in that order): | |
889 | * - area that won't get touched by U-Boot and Linux (optional) | |
890 | * - kernel log buffer | |
891 | * - protected RAM | |
892 | * - LCD framebuffer | |
893 | * - monitor code | |
894 | * - board info struct | |
895 | */ | |
896 | setup_dest_addr, | |
bbfdff31 | 897 | #if defined(CONFIG_BLACKFIN) |
d54d7eb9 SZ |
898 | /* Blackfin u-boot monitor should be on top of the ram */ |
899 | reserve_uboot, | |
900 | #endif | |
1938f4a5 SG |
901 | #if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) |
902 | reserve_logbuffer, | |
903 | #endif | |
904 | #ifdef CONFIG_PRAM | |
905 | reserve_pram, | |
906 | #endif | |
907 | reserve_round_4k, | |
908 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ | |
909 | defined(CONFIG_ARM) | |
910 | reserve_mmu, | |
911 | #endif | |
912 | #ifdef CONFIG_LCD | |
913 | reserve_lcd, | |
e4fef6cf | 914 | #endif |
71c52dba | 915 | reserve_trace, |
e4fef6cf | 916 | /* TODO: Why the dependency on CONFIG_8xx? */ |
d54d7eb9 SZ |
917 | #if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ |
918 | !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ | |
944ab340 | 919 | !defined(CONFIG_BLACKFIN) && !defined(CONFIG_M68K) |
e4fef6cf | 920 | reserve_video, |
1938f4a5 | 921 | #endif |
bbfdff31 | 922 | #if !defined(CONFIG_BLACKFIN) |
1938f4a5 | 923 | reserve_uboot, |
d54d7eb9 | 924 | #endif |
8cae8a68 | 925 | #ifndef CONFIG_SPL_BUILD |
1938f4a5 SG |
926 | reserve_malloc, |
927 | reserve_board, | |
8cae8a68 | 928 | #endif |
1938f4a5 SG |
929 | setup_machine, |
930 | reserve_global_data, | |
931 | reserve_fdt, | |
146251f8 | 932 | reserve_arch, |
1938f4a5 SG |
933 | reserve_stacks, |
934 | setup_dram_config, | |
935 | show_dram_config, | |
fb3db635 | 936 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_MIPS) |
e4fef6cf | 937 | setup_board_part1, |
fb3db635 DS |
938 | #endif |
939 | #if defined(CONFIG_PPC) || defined(CONFIG_M68K) | |
e4fef6cf SG |
940 | INIT_FUNC_WATCHDOG_RESET |
941 | setup_board_part2, | |
942 | #endif | |
1938f4a5 | 943 | display_new_sp, |
e4fef6cf SG |
944 | #ifdef CONFIG_SYS_EXTBDINFO |
945 | setup_board_extra, | |
946 | #endif | |
947 | INIT_FUNC_WATCHDOG_RESET | |
1938f4a5 SG |
948 | reloc_fdt, |
949 | setup_reloc, | |
3fb80163 | 950 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
313aef37 SG |
951 | copy_uboot_to_ram, |
952 | clear_bss, | |
953 | do_elf_reloc_fixups, | |
954 | #endif | |
808434cd | 955 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) |
1938f4a5 SG |
956 | jump_to_copy, |
957 | #endif | |
958 | NULL, | |
959 | }; | |
960 | ||
961 | void board_init_f(ulong boot_flags) | |
962 | { | |
2a1680e3 YS |
963 | #ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA |
964 | /* | |
965 | * For some archtectures, global data is initialized and used before | |
966 | * calling this function. The data should be preserved. For others, | |
967 | * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack | |
968 | * here to host global data until relocation. | |
969 | */ | |
1938f4a5 SG |
970 | gd_t data; |
971 | ||
972 | gd = &data; | |
973 | ||
cce6be7f DF |
974 | /* |
975 | * Clear global data before it is accessed at debug print | |
976 | * in initcall_run_list. Otherwise the debug print probably | |
977 | * get the wrong vaule of gd->have_console. | |
978 | */ | |
cce6be7f DF |
979 | zero_global_data(); |
980 | #endif | |
981 | ||
1938f4a5 | 982 | gd->flags = boot_flags; |
9aed5a27 | 983 | gd->have_console = 0; |
1938f4a5 SG |
984 | |
985 | if (initcall_run_list(init_sequence_f)) | |
986 | hang(); | |
987 | ||
9b217498 BS |
988 | #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ |
989 | !defined(CONFIG_EFI_APP) | |
1938f4a5 SG |
990 | /* NOTREACHED - jump_to_copy() does not return */ |
991 | hang(); | |
992 | #endif | |
993 | } | |
994 | ||
3fb80163 | 995 | #if defined(CONFIG_X86) || defined(CONFIG_ARC) |
48a33806 SG |
996 | /* |
997 | * For now this code is only used on x86. | |
998 | * | |
999 | * init_sequence_f_r is the list of init functions which are run when | |
1000 | * U-Boot is executing from Flash with a semi-limited 'C' environment. | |
1001 | * The following limitations must be considered when implementing an | |
1002 | * '_f_r' function: | |
1003 | * - 'static' variables are read-only | |
1004 | * - Global Data (gd->xxx) is read/write | |
1005 | * | |
1006 | * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if | |
1007 | * supported). It _should_, if possible, copy global data to RAM and | |
1008 | * initialise the CPU caches (to speed up the relocation process) | |
1009 | * | |
1010 | * NOTE: At present only x86 uses this route, but it is intended that | |
1011 | * all archs will move to this when generic relocation is implemented. | |
1012 | */ | |
1013 | static init_fnc_t init_sequence_f_r[] = { | |
1014 | init_cache_f_r, | |
48a33806 SG |
1015 | |
1016 | NULL, | |
1017 | }; | |
1018 | ||
1019 | void board_init_f_r(void) | |
1020 | { | |
1021 | if (initcall_run_list(init_sequence_f_r)) | |
1022 | hang(); | |
1023 | ||
1024 | /* | |
1025 | * U-Boot has been copied into SDRAM, the BSS has been cleared etc. | |
1026 | * Transfer execution from Flash to RAM by calculating the address | |
1027 | * of the in-RAM copy of board_init_r() and calling it | |
1028 | */ | |
7bf9f20d | 1029 | (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); |
48a33806 SG |
1030 | |
1031 | /* NOTREACHED - board_init_r() does not return */ | |
1032 | hang(); | |
1033 | } | |
5bcd19aa | 1034 | #endif /* CONFIG_X86 */ |