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3f85ce27 WD |
1 | /* |
2 | * Copyright (c) 2004 Picture Elements, Inc. | |
3 | * Stephen Williams (XXXXXXXXXXXXXXXX) | |
4 | * | |
5 | * This source code is free software; you can redistribute it | |
6 | * and/or modify it in source code form under the terms of the GNU | |
7 | * General Public License as published by the Free Software | |
8 | * Foundation; either version 2 of the License, or (at your option) | |
9 | * any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA | |
19 | */ | |
20 | #ident "$Id:$" | |
21 | ||
22 | /* | |
23 | * The Xilinx SystemACE chip support is activated by defining | |
24 | * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE | |
25 | * to set the base address of the device. This code currently | |
26 | * assumes that the chip is connected via a byte-wide bus. | |
27 | * | |
28 | * The CONFIG_SYSTEMACE also adds to fat support the device class | |
29 | * "ace" that allows the user to execute "fatls ace 0" and the | |
30 | * like. This works by making the systemace_get_dev function | |
31 | * available to cmd_fat.c:get_dev and filling in a block device | |
32 | * description that has all the bits needed for FAT support to | |
33 | * read sectors. | |
8f79e4c2 | 34 | * |
fe599e17 WD |
35 | * According to Xilinx technical support, before accessing the |
36 | * SystemACE CF you need to set the following control bits: | |
37 | * FORCECFGMODE : 1 | |
38 | * CFGMODE : 0 | |
39 | * CFGSTART : 0 | |
3f85ce27 WD |
40 | */ |
41 | ||
42 | # include <common.h> | |
43 | # include <command.h> | |
44 | # include <systemace.h> | |
45 | # include <part.h> | |
46 | # include <asm/io.h> | |
47 | ||
48 | #ifdef CONFIG_SYSTEMACE | |
49 | ||
50 | /* | |
51 | * The ace_readw and writew functions read/write 16bit words, but the | |
52 | * offset value is the BYTE offset as most used in the Xilinx | |
53 | * datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined | |
54 | * to be the base address for the chip, usually in the local | |
55 | * peripheral bus. | |
56 | */ | |
57 | static unsigned ace_readw(unsigned offset) | |
58 | { | |
a5bbcc3c WD |
59 | #if (CFG_SYSTEMACE_WIDTH == 8) |
60 | u16 temp; | |
61 | ||
62 | #if !defined(__BIG_ENDIAN) | |
63 | temp =((u16)readb(CFG_SYSTEMACE_BASE+offset) << 8); | |
64 | temp |= (u16)readb(CFG_SYSTEMACE_BASE+offset+1); | |
65 | #else | |
66 | temp = (u16)readb(CFG_SYSTEMACE_BASE+offset); | |
67 | temp |=((u16)readb(CFG_SYSTEMACE_BASE+offset+1) << 8); | |
68 | #endif | |
69 | return temp; | |
70 | #else | |
71 | return readw(CFG_SYSTEMACE_BASE+offset); | |
72 | #endif | |
3f85ce27 WD |
73 | } |
74 | ||
08f1080c | 75 | static void ace_writew(unsigned val, unsigned offset) |
3f85ce27 | 76 | { |
a5bbcc3c WD |
77 | #if (CFG_SYSTEMACE_WIDTH == 8) |
78 | #if !defined(__BIG_ENDIAN) | |
79 | writeb((u8)(val>>8), CFG_SYSTEMACE_BASE+offset); | |
80 | writeb((u8)val, CFG_SYSTEMACE_BASE+offset+1); | |
81 | #else | |
82 | writeb((u8)val, CFG_SYSTEMACE_BASE+offset); | |
83 | writeb((u8)(val>>8), CFG_SYSTEMACE_BASE+offset+1); | |
84 | #endif | |
85 | #else | |
86 | writew(val, CFG_SYSTEMACE_BASE+offset); | |
87 | #endif | |
3f85ce27 WD |
88 | } |
89 | ||
90 | /* */ | |
91 | ||
92 | static unsigned long systemace_read(int dev, | |
93 | unsigned long start, | |
94 | unsigned long blkcnt, | |
95 | unsigned long *buffer); | |
96 | ||
97 | static block_dev_desc_t systemace_dev = {0}; | |
98 | ||
99 | static int get_cf_lock(void) | |
100 | { | |
101 | int retry = 10; | |
102 | ||
103 | /* CONTROLREG = LOCKREG */ | |
fe599e17 WD |
104 | unsigned val=ace_readw(0x18); |
105 | val|=0x0002; | |
106 | ace_writew((val&0xffff), 0x18); | |
3f85ce27 WD |
107 | |
108 | /* Wait for MPULOCK in STATUSREG[15:0] */ | |
109 | while (! (ace_readw(0x04) & 0x0002)) { | |
110 | ||
111 | if (retry < 0) | |
112 | return -1; | |
113 | ||
114 | udelay(100000); | |
115 | retry -= 1; | |
116 | } | |
117 | ||
118 | return 0; | |
119 | } | |
120 | ||
121 | static void release_cf_lock(void) | |
122 | { | |
fe599e17 WD |
123 | unsigned val=ace_readw(0x18); |
124 | val&=~(0x0002); | |
125 | ace_writew((val&0xffff), 0x18); | |
3f85ce27 WD |
126 | } |
127 | ||
128 | block_dev_desc_t * systemace_get_dev(int dev) | |
129 | { | |
130 | /* The first time through this, the systemace_dev object is | |
131 | not yet initialized. In that case, fill it in. */ | |
132 | if (systemace_dev.blksz == 0) { | |
133 | systemace_dev.if_type = IF_TYPE_UNKNOWN; | |
29ca46c4 | 134 | systemace_dev.dev = 0; |
3f85ce27 WD |
135 | systemace_dev.part_type = PART_TYPE_UNKNOWN; |
136 | systemace_dev.type = DEV_TYPE_HARDDISK; | |
137 | systemace_dev.blksz = 512; | |
138 | systemace_dev.removable = 1; | |
139 | systemace_dev.block_read = systemace_read; | |
fe599e17 WD |
140 | |
141 | init_part(&systemace_dev); | |
142 | ||
3f85ce27 WD |
143 | } |
144 | ||
145 | return &systemace_dev; | |
146 | } | |
147 | ||
148 | /* | |
149 | * This function is called (by dereferencing the block_read pointer in | |
150 | * the dev_desc) to read blocks of data. The return value is the | |
151 | * number of blocks read. A zero return indicates an error. | |
152 | */ | |
153 | static unsigned long systemace_read(int dev, | |
154 | unsigned long start, | |
155 | unsigned long blkcnt, | |
156 | unsigned long *buffer) | |
157 | { | |
3f85ce27 | 158 | int retry; |
e7c85689 | 159 | unsigned blk_countdown; |
3f85ce27 | 160 | unsigned char*dp = (unsigned char*)buffer; |
fe599e17 | 161 | unsigned val; |
3f85ce27 WD |
162 | |
163 | if (get_cf_lock() < 0) { | |
164 | unsigned status = ace_readw(0x04); | |
165 | ||
166 | /* If CFDETECT is false, card is missing. */ | |
167 | if (! (status&0x0010)) { | |
168 | printf("** CompactFlash card not present. **\n"); | |
169 | return 0; | |
170 | } | |
171 | ||
172 | printf("**** ACE locked away from me (STATUSREG=%04x)\n", status); | |
173 | return 0; | |
174 | } | |
175 | ||
e7c85689 WD |
176 | #ifdef DEBUG_SYSTEMACE |
177 | printf("... systemace read %lu sectors at %lu\n", blkcnt, start); | |
178 | #endif | |
179 | ||
3f85ce27 WD |
180 | retry = 2000; |
181 | for (;;) { | |
fe599e17 | 182 | val = ace_readw(0x04); |
3f85ce27 WD |
183 | |
184 | /* If CFDETECT is false, card is missing. */ | |
185 | if (! (val & 0x0010)) { | |
186 | printf("**** ACE CompactFlash not found.\n"); | |
187 | release_cf_lock(); | |
188 | return 0; | |
189 | } | |
190 | ||
191 | /* If RDYFORCMD, then we are ready to go. */ | |
192 | if (val & 0x0100) | |
193 | break; | |
194 | ||
195 | if (retry < 0) { | |
196 | printf("**** SystemACE not ready.\n"); | |
197 | release_cf_lock(); | |
198 | return 0; | |
199 | } | |
200 | ||
201 | udelay(1000); | |
202 | retry -= 1; | |
203 | } | |
204 | ||
e7c85689 WD |
205 | /* The SystemACE can only transfer 256 sectors at a time, so |
206 | limit the current chunk of sectors. The blk_countdown | |
207 | variable is the number of sectors left to transfer. */ | |
3f85ce27 | 208 | |
e7c85689 WD |
209 | blk_countdown = blkcnt; |
210 | while (blk_countdown > 0) { | |
211 | unsigned trans = blk_countdown; | |
3f85ce27 | 212 | |
e7c85689 | 213 | if (trans > 256) trans = 256; |
3f85ce27 | 214 | |
e7c85689 WD |
215 | #ifdef DEBUG_SYSTEMACE |
216 | printf("... transfer %lu sector in a chunk\n", trans); | |
217 | #endif | |
218 | /* Write LBA block address */ | |
219 | ace_writew((start>> 0) & 0xffff, 0x10); | |
220 | ace_writew((start>>16) & 0x00ff, 0x12); | |
3f85ce27 | 221 | |
e7c85689 WD |
222 | /* NOTE: in the Write Sector count below, a count of 0 |
223 | causes a transfer of 256, so &0xff gives the right | |
224 | value for whatever transfer count we want. */ | |
225 | ||
226 | /* Write sector count | ReadMemCardData. */ | |
227 | ace_writew((trans&0xff) | 0x0300, 0x14); | |
3f85ce27 | 228 | |
fe599e17 WD |
229 | /* Reset the configruation controller */ |
230 | val = ace_readw(0x18); | |
231 | val|=0x0080; | |
232 | ace_writew(val, 0x18); | |
233 | ||
e7c85689 WD |
234 | retry = trans * 16; |
235 | while (retry > 0) { | |
236 | int idx; | |
237 | ||
238 | /* Wait for buffer to become ready. */ | |
239 | while (! (ace_readw(0x04) & 0x0020)) { | |
6fb6af6d | 240 | udelay(100); |
e7c85689 WD |
241 | } |
242 | ||
243 | /* Read 16 words of 2bytes from the sector buffer. */ | |
244 | for (idx = 0 ; idx < 16 ; idx += 1) { | |
245 | unsigned short val = ace_readw(0x40); | |
246 | *dp++ = val & 0xff; | |
247 | *dp++ = (val>>8) & 0xff; | |
248 | } | |
249 | ||
250 | retry -= 1; | |
3f85ce27 WD |
251 | } |
252 | ||
fe599e17 WD |
253 | /* Clear the configruation controller reset */ |
254 | val = ace_readw(0x18); | |
255 | val&=~0x0080; | |
256 | ace_writew(val, 0x18); | |
257 | ||
e7c85689 WD |
258 | /* Count the blocks we transfer this time. */ |
259 | start += trans; | |
260 | blk_countdown -= trans; | |
3f85ce27 WD |
261 | } |
262 | ||
263 | release_cf_lock(); | |
264 | ||
265 | return blkcnt; | |
266 | } | |
08f1080c | 267 | #endif /* CONFIG_SYSTEMACE */ |