[people/ms/u-boot.git] / common / cmd_ace.c

/*
 * Copyright (c) 2004 Picture Elements, Inc.
 *    Stephen Williams (XXXXXXXXXXXXXXXX)
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
 *    General Public License as published by the Free Software
 *    Foundation; either version 2 of the License, or (at your option)
 *    any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
#ident "$Id:$"

/*
 * The Xilinx SystemACE chip support is activated by defining
 * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE
 * to set the base address of the device. This code currently
 * assumes that the chip is connected via a byte-wide bus.
 *
 * The CONFIG_SYSTEMACE also adds to fat support the device class
 * "ace" that allows the user to execute "fatls ace 0" and the
 * like. This works by making the systemace_get_dev function
 * available to cmd_fat.c:get_dev and filling in a block device
 * description that has all the bits needed for FAT support to
 * read sectors.
 * 
 * According to Xilinx technical support, before accessing the
 * SystemACE CF you need to set the following control bits:
 * 	FORCECFGMODE : 1
 * 	CFGMODE : 0
 * 	CFGSTART : 0
 */

# include  <common.h>
# include  <command.h>
# include  <systemace.h>
# include  <part.h>
# include  <asm/io.h>

#ifdef CONFIG_SYSTEMACE

/*
 * The ace_readw and writew functions read/write 16bit words, but the
 * offset value is the BYTE offset as most used in the Xilinx
 * datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined
 * to be the base address for the chip, usually in the local
 * peripheral bus.
 */
static unsigned ace_readw(unsigned offset)
{
#if (CFG_SYSTEMACE_WIDTH == 8)
  u16 temp;

#if !defined(__BIG_ENDIAN)
  temp =((u16)readb(CFG_SYSTEMACE_BASE+offset) << 8);
  temp |= (u16)readb(CFG_SYSTEMACE_BASE+offset+1);
#else
  temp = (u16)readb(CFG_SYSTEMACE_BASE+offset);
  temp |=((u16)readb(CFG_SYSTEMACE_BASE+offset+1) << 8);
#endif
  return temp;
#else
  return readw(CFG_SYSTEMACE_BASE+offset);
#endif
}

static void ace_writew(unsigned val, unsigned offset)
{
#if (CFG_SYSTEMACE_WIDTH == 8)
#if !defined(__BIG_ENDIAN)
  writeb((u8)(val>>8), CFG_SYSTEMACE_BASE+offset);
  writeb((u8)val, CFG_SYSTEMACE_BASE+offset+1);
#else
  writeb((u8)val, CFG_SYSTEMACE_BASE+offset);
  writeb((u8)(val>>8), CFG_SYSTEMACE_BASE+offset+1);
#endif
#else
  writew(val, CFG_SYSTEMACE_BASE+offset);
#endif
}

/* */

static unsigned long systemace_read(int dev,
				    unsigned long start,
				    unsigned long blkcnt,
				    unsigned long *buffer);

static block_dev_desc_t systemace_dev = {0};

static int get_cf_lock(void)
{
      int retry = 10;

	/* CONTROLREG = LOCKREG */
      unsigned val=ace_readw(0x18);
      val|=0x0002;
      ace_writew((val&0xffff), 0x18);

	/* Wait for MPULOCK in STATUSREG[15:0] */
      while (! (ace_readw(0x04) & 0x0002)) {

	    if (retry < 0)
		  return -1;

	    udelay(100000);
	    retry -= 1;
      }

      return 0;
}

static void release_cf_lock(void)
{
	unsigned val=ace_readw(0x18);
	val&=~(0x0002);
	ace_writew((val&0xffff), 0x18);
}

block_dev_desc_t *  systemace_get_dev(int dev)
{
	/* The first time through this, the systemace_dev object is
	   not yet initialized. In that case, fill it in. */
      if (systemace_dev.blksz == 0) {
	    systemace_dev.if_type   = IF_TYPE_UNKNOWN;
	    systemace_dev.part_type = PART_TYPE_UNKNOWN;
	    systemace_dev.type      = DEV_TYPE_HARDDISK;
	    systemace_dev.blksz     = 512;
	    systemace_dev.removable = 1;
	    systemace_dev.block_read = systemace_read;

	    init_part(&systemace_dev);

      }

      return &systemace_dev;
}

/*
 * This function is called (by dereferencing the block_read pointer in
 * the dev_desc) to read blocks of data. The return value is the
 * number of blocks read. A zero return indicates an error.
 */
static unsigned long systemace_read(int dev,
				    unsigned long start,
				    unsigned long blkcnt,
				    unsigned long *buffer)
{
      int retry;
      unsigned blk_countdown;
      unsigned char*dp = (unsigned char*)buffer;
      unsigned val;

      if (get_cf_lock() < 0) {
	    unsigned status = ace_readw(0x04);

	      /* If CFDETECT is false, card is missing. */
	    if (! (status&0x0010)) {
		  printf("** CompactFlash card not present. **\n");
		  return 0;
	    }

	    printf("**** ACE locked away from me (STATUSREG=%04x)\n", status);
	    return 0;
      }

#ifdef DEBUG_SYSTEMACE
      printf("... systemace read %lu sectors at %lu\n", blkcnt, start);
#endif

      retry = 2000;
      for (;;) {
	    val = ace_readw(0x04);

	      /* If CFDETECT is false, card is missing. */
	    if (! (val & 0x0010)) {
		  printf("**** ACE CompactFlash not found.\n");
		  release_cf_lock();
		  return 0;
	    }

	      /* If RDYFORCMD, then we are ready to go. */
	    if (val & 0x0100)
		  break;

	    if (retry < 0) {
		  printf("**** SystemACE not ready.\n");
		  release_cf_lock();
		  return 0;
	    }

	    udelay(1000);
	    retry -= 1;
      }

	/* The SystemACE can only transfer 256 sectors at a time, so
	   limit the current chunk of sectors. The blk_countdown
	   variable is the number of sectors left to transfer. */

      blk_countdown = blkcnt;
      while (blk_countdown > 0) {
	    unsigned trans = blk_countdown;

	    if (trans > 256) trans = 256;

#ifdef DEBUG_SYSTEMACE
	    printf("... transfer %lu sector in a chunk\n", trans);
#endif
	      /* Write LBA block address */
	    ace_writew((start>> 0) & 0xffff, 0x10);
	    ace_writew((start>>16) & 0x00ff, 0x12);

	      /* NOTE: in the Write Sector count below, a count of 0
		 causes a transfer of 256, so &0xff gives the right
		 value for whatever transfer count we want. */

	      /* Write sector count | ReadMemCardData. */
	    ace_writew((trans&0xff) | 0x0300, 0x14);

	    /* Reset the configruation controller */
	    val = ace_readw(0x18);
	    val|=0x0080;
	    ace_writew(val, 0x18);

	    retry = trans * 16;
	    while (retry > 0) {
		  int idx;

		    /* Wait for buffer to become ready. */
		  while (! (ace_readw(0x04) & 0x0020)) {
			udelay(100);
		  }

		    /* Read 16 words of 2bytes from the sector buffer. */
		  for (idx = 0 ;  idx < 16 ;  idx += 1) {
			unsigned short val = ace_readw(0x40);
			*dp++ = val & 0xff;
			*dp++ = (val>>8) & 0xff;
		  }

		  retry -= 1;
	    }

	    /* Clear the configruation controller reset */
	    val = ace_readw(0x18);
	    val&=~0x0080;
	    ace_writew(val, 0x18);

	      /* Count the blocks we transfer this time. */
	    start += trans;
	    blk_countdown -= trans;
      }

      release_cf_lock();

      return blkcnt;
}
#endif	/* CONFIG_SYSTEMACE */
Commit	Line	Data
3f85ce27 WD	1	/*
	2	* Copyright (c) 2004 Picture Elements, Inc.
	3	* Stephen Williams (XXXXXXXXXXXXXXXX)
	4	*
	5	* This source code is free software; you can redistribute it
	6	* and/or modify it in source code form under the terms of the GNU
	7	* General Public License as published by the Free Software
	8	* Foundation; either version 2 of the License, or (at your option)
	9	* any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
	19	*/
	20	#ident "$Id:$"
	21
	22	/*
	23	* The Xilinx SystemACE chip support is activated by defining
	24	* CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE
	25	* to set the base address of the device. This code currently
	26	* assumes that the chip is connected via a byte-wide bus.
	27	*
	28	* The CONFIG_SYSTEMACE also adds to fat support the device class
	29	* "ace" that allows the user to execute "fatls ace 0" and the
	30	* like. This works by making the systemace_get_dev function
	31	* available to cmd_fat.c:get_dev and filling in a block device
	32	* description that has all the bits needed for FAT support to
	33	* read sectors.
fe599e17 WD	34	*
	35	* According to Xilinx technical support, before accessing the
	36	* SystemACE CF you need to set the following control bits:
	37	* FORCECFGMODE : 1
	38	* CFGMODE : 0
	39	* CFGSTART : 0
3f85ce27 WD	40	*/
	41
	42	# include <common.h>
	43	# include <command.h>
	44	# include <systemace.h>
	45	# include <part.h>
	46	# include <asm/io.h>
	47
	48	#ifdef CONFIG_SYSTEMACE
	49
	50	/*
	51	* The ace_readw and writew functions read/write 16bit words, but the
	52	* offset value is the BYTE offset as most used in the Xilinx
	53	* datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined
	54	* to be the base address for the chip, usually in the local
	55	* peripheral bus.
	56	*/
	57	static unsigned ace_readw(unsigned offset)
	58	{
a5bbcc3c WD	59	#if (CFG_SYSTEMACE_WIDTH == 8)
	60	u16 temp;
	61
	62	#if !defined(__BIG_ENDIAN)
	63	temp =((u16)readb(CFG_SYSTEMACE_BASE+offset) << 8);
	64	temp \|= (u16)readb(CFG_SYSTEMACE_BASE+offset+1);
	65	#else
	66	temp = (u16)readb(CFG_SYSTEMACE_BASE+offset);
	67	temp \|=((u16)readb(CFG_SYSTEMACE_BASE+offset+1) << 8);
	68	#endif
	69	return temp;
	70	#else
	71	return readw(CFG_SYSTEMACE_BASE+offset);
	72	#endif
3f85ce27 WD	73	}
3f85ce27 WD	74
08f1080c	75	static void ace_writew(unsigned val, unsigned offset)
3f85ce27	76	{
a5bbcc3c WD	77	#if (CFG_SYSTEMACE_WIDTH == 8)
	78	#if !defined(__BIG_ENDIAN)
	79	writeb((u8)(val>>8), CFG_SYSTEMACE_BASE+offset);
	80	writeb((u8)val, CFG_SYSTEMACE_BASE+offset+1);
	81	#else
	82	writeb((u8)val, CFG_SYSTEMACE_BASE+offset);
	83	writeb((u8)(val>>8), CFG_SYSTEMACE_BASE+offset+1);
	84	#endif
	85	#else
	86	writew(val, CFG_SYSTEMACE_BASE+offset);
	87	#endif
3f85ce27 WD	88	}
	89
	90	/* */
	91
	92	static unsigned long systemace_read(int dev,
	93	unsigned long start,
	94	unsigned long blkcnt,
	95	unsigned long *buffer);
	96
	97	static block_dev_desc_t systemace_dev = {0};
	98
	99	static int get_cf_lock(void)
	100	{
	101	int retry = 10;
	102
	103	/* CONTROLREG = LOCKREG */
fe599e17 WD	104	unsigned val=ace_readw(0x18);
	105	val\|=0x0002;
	106	ace_writew((val&0xffff), 0x18);
3f85ce27 WD	107
	108	/* Wait for MPULOCK in STATUSREG[15:0] */
	109	while (! (ace_readw(0x04) & 0x0002)) {
	110
	111	if (retry < 0)
	112	return -1;
	113
	114	udelay(100000);
	115	retry -= 1;
	116	}
	117
	118	return 0;
	119	}
	120
	121	static void release_cf_lock(void)
	122	{
fe599e17 WD	123	unsigned val=ace_readw(0x18);
	124	val&=~(0x0002);
	125	ace_writew((val&0xffff), 0x18);
3f85ce27 WD	126	}
	127
	128	block_dev_desc_t * systemace_get_dev(int dev)
	129	{
	130	/* The first time through this, the systemace_dev object is
	131	not yet initialized. In that case, fill it in. */
	132	if (systemace_dev.blksz == 0) {
	133	systemace_dev.if_type = IF_TYPE_UNKNOWN;
	134	systemace_dev.part_type = PART_TYPE_UNKNOWN;
	135	systemace_dev.type = DEV_TYPE_HARDDISK;
	136	systemace_dev.blksz = 512;
	137	systemace_dev.removable = 1;
	138	systemace_dev.block_read = systemace_read;
fe599e17 WD	139
	140	init_part(&systemace_dev);
	141
3f85ce27 WD	142	}
	143
	144	return &systemace_dev;
	145	}
	146
	147	/*
	148	* This function is called (by dereferencing the block_read pointer in
	149	* the dev_desc) to read blocks of data. The return value is the
	150	* number of blocks read. A zero return indicates an error.
	151	*/
	152	static unsigned long systemace_read(int dev,
	153	unsigned long start,
	154	unsigned long blkcnt,
	155	unsigned long *buffer)
	156	{
3f85ce27	157	int retry;
e7c85689	158	unsigned blk_countdown;
3f85ce27	159	unsigned chardp = (unsigned char)buffer;
fe599e17	160	unsigned val;
3f85ce27 WD	161
	162	if (get_cf_lock() < 0) {
	163	unsigned status = ace_readw(0x04);
	164
	165	/* If CFDETECT is false, card is missing. */
	166	if (! (status&0x0010)) {
	167	printf(" CompactFlash card not present. \n");
	168	return 0;
	169	}
	170
	171	printf("**** ACE locked away from me (STATUSREG=%04x)\n", status);
	172	return 0;
	173	}
	174
e7c85689 WD	175	#ifdef DEBUG_SYSTEMACE
	176	printf("... systemace read %lu sectors at %lu\n", blkcnt, start);
	177	#endif
	178
3f85ce27 WD	179	retry = 2000;
3f85ce27 WD	180	for (;;) {
fe599e17	181	val = ace_readw(0x04);
3f85ce27 WD	182
	183	/* If CFDETECT is false, card is missing. */
	184	if (! (val & 0x0010)) {
	185	printf("**** ACE CompactFlash not found.\n");
	186	release_cf_lock();
	187	return 0;
	188	}
	189
	190	/* If RDYFORCMD, then we are ready to go. */
	191	if (val & 0x0100)
	192	break;
	193
	194	if (retry < 0) {
	195	printf("**** SystemACE not ready.\n");
	196	release_cf_lock();
	197	return 0;
	198	}
	199
	200	udelay(1000);
	201	retry -= 1;
	202	}
	203
e7c85689 WD	204	/* The SystemACE can only transfer 256 sectors at a time, so
	205	limit the current chunk of sectors. The blk_countdown
	206	variable is the number of sectors left to transfer. */
3f85ce27	207
e7c85689 WD	208	blk_countdown = blkcnt;
	209	while (blk_countdown > 0) {
	210	unsigned trans = blk_countdown;
3f85ce27	211
e7c85689	212	if (trans > 256) trans = 256;
3f85ce27	213
e7c85689 WD	214	#ifdef DEBUG_SYSTEMACE
	215	printf("... transfer %lu sector in a chunk\n", trans);
	216	#endif
	217	/* Write LBA block address */
	218	ace_writew((start>> 0) & 0xffff, 0x10);
	219	ace_writew((start>>16) & 0x00ff, 0x12);
3f85ce27	220
e7c85689 WD	221	/* NOTE: in the Write Sector count below, a count of 0
	222	causes a transfer of 256, so &0xff gives the right
	223	value for whatever transfer count we want. */
	224
	225	/* Write sector count \| ReadMemCardData. */
	226	ace_writew((trans&0xff) \| 0x0300, 0x14);
3f85ce27	227
fe599e17 WD	228	/* Reset the configruation controller */
	229	val = ace_readw(0x18);
	230	val\|=0x0080;
	231	ace_writew(val, 0x18);
	232
e7c85689 WD	233	retry = trans * 16;
	234	while (retry > 0) {
	235	int idx;
	236
	237	/* Wait for buffer to become ready. */
	238	while (! (ace_readw(0x04) & 0x0020)) {
6fb6af6d	239	udelay(100);
e7c85689 WD	240	}
	241
	242	/* Read 16 words of 2bytes from the sector buffer. */
	243	for (idx = 0 ; idx < 16 ; idx += 1) {
	244	unsigned short val = ace_readw(0x40);
	245	*dp++ = val & 0xff;
	246	*dp++ = (val>>8) & 0xff;
	247	}
	248
	249	retry -= 1;
3f85ce27 WD	250	}
3f85ce27 WD	251
fe599e17 WD	252	/* Clear the configruation controller reset */
	253	val = ace_readw(0x18);
	254	val&=~0x0080;
	255	ace_writew(val, 0x18);
	256
e7c85689 WD	257	/* Count the blocks we transfer this time. */
	258	start += trans;
	259	blk_countdown -= trans;
3f85ce27 WD	260	}
	261
	262	release_cf_lock();
	263
	264	return blkcnt;
	265	}
08f1080c	266	#endif /* CONFIG_SYSTEMACE */