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4a9cbbe8 WD |
1 | /* |
2 | * (C) Copyright 2000, 2001 | |
3 | * Rich Ireland, Enterasys Networks, rireland@enterasys.com. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | /* | |
26 | * FPGA support | |
27 | */ | |
28 | #include <common.h> | |
29 | #include <command.h> | |
8bde7f77 | 30 | #include <fpga.h> |
c3d2b4b4 | 31 | #include <malloc.h> |
4a9cbbe8 | 32 | |
4a9cbbe8 | 33 | /* Local functions */ |
fc598412 | 34 | static int fpga_get_op(char *opstr); |
4a9cbbe8 WD |
35 | |
36 | /* Local defines */ | |
37 | #define FPGA_NONE -1 | |
38 | #define FPGA_INFO 0 | |
39 | #define FPGA_LOAD 1 | |
30ce5ab0 | 40 | #define FPGA_LOADB 2 |
4a9cbbe8 | 41 | #define FPGA_DUMP 3 |
f0ff4692 | 42 | #define FPGA_LOADMK 4 |
4a9cbbe8 WD |
43 | |
44 | /* ------------------------------------------------------------------------- */ | |
45 | /* command form: | |
46 | * fpga <op> <device number> <data addr> <datasize> | |
47 | * where op is 'load', 'dump', or 'info' | |
48 | * If there is no device number field, the fpga environment variable is used. | |
49 | * If there is no data addr field, the fpgadata environment variable is used. | |
50 | * The info command requires no data address field. | |
51 | */ | |
fc598412 | 52 | int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) |
4a9cbbe8 | 53 | { |
d4ca31c4 WD |
54 | int op, dev = FPGA_INVALID_DEVICE; |
55 | size_t data_size = 0; | |
56 | void *fpga_data = NULL; | |
fc598412 MS |
57 | char *devstr = getenv("fpga"); |
58 | char *datastr = getenv("fpgadata"); | |
d4ca31c4 | 59 | int rc = FPGA_FAIL; |
a790b5b2 | 60 | int wrong_parms = 0; |
fc598412 | 61 | #if defined(CONFIG_FIT) |
c28c4d19 MB |
62 | const char *fit_uname = NULL; |
63 | ulong fit_addr; | |
64 | #endif | |
d4ca31c4 WD |
65 | |
66 | if (devstr) | |
fc598412 | 67 | dev = (int) simple_strtoul(devstr, NULL, 16); |
d4ca31c4 | 68 | if (datastr) |
fc598412 | 69 | fpga_data = (void *)simple_strtoul(datastr, NULL, 16); |
d4ca31c4 WD |
70 | |
71 | switch (argc) { | |
72 | case 5: /* fpga <op> <dev> <data> <datasize> */ | |
fc598412 | 73 | data_size = simple_strtoul(argv[4], NULL, 16); |
c28c4d19 | 74 | |
d4ca31c4 | 75 | case 4: /* fpga <op> <dev> <data> */ |
c28c4d19 | 76 | #if defined(CONFIG_FIT) |
fc598412 MS |
77 | if (fit_parse_subimage(argv[3], (ulong)fpga_data, |
78 | &fit_addr, &fit_uname)) { | |
c28c4d19 | 79 | fpga_data = (void *)fit_addr; |
fc598412 MS |
80 | debug("* fpga: subimage '%s' from FIT image ", |
81 | fit_uname); | |
82 | debug("at 0x%08lx\n", fit_addr); | |
c28c4d19 MB |
83 | } else |
84 | #endif | |
85 | { | |
fc598412 | 86 | fpga_data = (void *)simple_strtoul(argv[3], NULL, 16); |
06297db0 | 87 | debug("* fpga: cmdline image address = 0x%08lx\n", |
fc598412 | 88 | (ulong)fpga_data); |
c28c4d19 | 89 | } |
fc598412 | 90 | debug("%s: fpga_data = 0x%x\n", __func__, (uint)fpga_data); |
c28c4d19 | 91 | |
d4ca31c4 | 92 | case 3: /* fpga <op> <dev | data addr> */ |
fc598412 | 93 | dev = (int)simple_strtoul(argv[2], NULL, 16); |
06297db0 | 94 | debug("%s: device = %d\n", __func__, dev); |
d4ca31c4 | 95 | /* FIXME - this is a really weak test */ |
fc598412 MS |
96 | if ((argc == 3) && (dev > fpga_count())) { |
97 | /* must be buffer ptr */ | |
06297db0 | 98 | debug("%s: Assuming buffer pointer in arg 3\n", |
fc598412 | 99 | __func__); |
c28c4d19 MB |
100 | |
101 | #if defined(CONFIG_FIT) | |
fc598412 MS |
102 | if (fit_parse_subimage(argv[2], (ulong)fpga_data, |
103 | &fit_addr, &fit_uname)) { | |
c28c4d19 | 104 | fpga_data = (void *)fit_addr; |
fc598412 MS |
105 | debug("* fpga: subimage '%s' from FIT image ", |
106 | fit_uname); | |
107 | debug("at 0x%08lx\n", fit_addr); | |
c28c4d19 MB |
108 | } else |
109 | #endif | |
110 | { | |
fc598412 MS |
111 | fpga_data = (void *)dev; |
112 | debug("* fpga: cmdline image addr = 0x%08lx\n", | |
113 | (ulong)fpga_data); | |
c28c4d19 MB |
114 | } |
115 | ||
06297db0 | 116 | debug("%s: fpga_data = 0x%x\n", |
fc598412 | 117 | __func__, (uint)fpga_data); |
d4ca31c4 WD |
118 | dev = FPGA_INVALID_DEVICE; /* reset device num */ |
119 | } | |
c28c4d19 | 120 | |
d4ca31c4 | 121 | case 2: /* fpga <op> */ |
fc598412 | 122 | op = (int)fpga_get_op(argv[1]); |
d4ca31c4 | 123 | break; |
c28c4d19 | 124 | |
d4ca31c4 | 125 | default: |
fc598412 | 126 | debug("%s: Too many or too few args (%d)\n", __func__, argc); |
d4ca31c4 WD |
127 | op = FPGA_NONE; /* force usage display */ |
128 | break; | |
129 | } | |
130 | ||
a790b5b2 SB |
131 | if (dev == FPGA_INVALID_DEVICE) { |
132 | puts("FPGA device not specified\n"); | |
133 | op = FPGA_NONE; | |
134 | } | |
135 | ||
136 | switch (op) { | |
137 | case FPGA_NONE: | |
138 | case FPGA_INFO: | |
139 | break; | |
140 | case FPGA_LOAD: | |
141 | case FPGA_LOADB: | |
142 | case FPGA_DUMP: | |
143 | if (!fpga_data || !data_size) | |
144 | wrong_parms = 1; | |
145 | break; | |
146 | case FPGA_LOADMK: | |
147 | if (!fpga_data) | |
148 | wrong_parms = 1; | |
149 | break; | |
150 | } | |
151 | ||
152 | if (wrong_parms) { | |
153 | puts("Wrong parameters for FPGA request\n"); | |
154 | op = FPGA_NONE; | |
155 | } | |
156 | ||
d4ca31c4 WD |
157 | switch (op) { |
158 | case FPGA_NONE: | |
4c12eeb8 | 159 | return CMD_RET_USAGE; |
d4ca31c4 WD |
160 | |
161 | case FPGA_INFO: | |
fc598412 | 162 | rc = fpga_info(dev); |
d4ca31c4 WD |
163 | break; |
164 | ||
165 | case FPGA_LOAD: | |
fc598412 | 166 | rc = fpga_load(dev, fpga_data, data_size); |
d4ca31c4 WD |
167 | break; |
168 | ||
30ce5ab0 WD |
169 | case FPGA_LOADB: |
170 | rc = fpga_loadbitstream(dev, fpga_data, data_size); | |
171 | break; | |
172 | ||
f0ff4692 | 173 | case FPGA_LOADMK: |
fc598412 | 174 | switch (genimg_get_format(fpga_data)) { |
d5934ad7 MB |
175 | case IMAGE_FORMAT_LEGACY: |
176 | { | |
fc598412 MS |
177 | image_header_t *hdr = |
178 | (image_header_t *)fpga_data; | |
179 | ulong data; | |
d5934ad7 | 180 | |
fc598412 MS |
181 | data = (ulong)image_get_data(hdr); |
182 | data_size = image_get_data_size(hdr); | |
183 | rc = fpga_load(dev, (void *)data, data_size); | |
f0ff4692 | 184 | } |
d5934ad7 MB |
185 | break; |
186 | #if defined(CONFIG_FIT) | |
187 | case IMAGE_FORMAT_FIT: | |
c28c4d19 MB |
188 | { |
189 | const void *fit_hdr = (const void *)fpga_data; | |
190 | int noffset; | |
e6a857da | 191 | const void *fit_data; |
c28c4d19 MB |
192 | |
193 | if (fit_uname == NULL) { | |
fc598412 | 194 | puts("No FIT subimage unit name\n"); |
c28c4d19 MB |
195 | return 1; |
196 | } | |
197 | ||
fc598412 MS |
198 | if (!fit_check_format(fit_hdr)) { |
199 | puts("Bad FIT image format\n"); | |
c28c4d19 MB |
200 | return 1; |
201 | } | |
202 | ||
203 | /* get fpga component image node offset */ | |
fc598412 MS |
204 | noffset = fit_image_get_node(fit_hdr, |
205 | fit_uname); | |
c28c4d19 | 206 | if (noffset < 0) { |
fc598412 MS |
207 | printf("Can't find '%s' FIT subimage\n", |
208 | fit_uname); | |
c28c4d19 MB |
209 | return 1; |
210 | } | |
211 | ||
212 | /* verify integrity */ | |
b8da8366 | 213 | if (!fit_image_verify(fit_hdr, noffset)) { |
c28c4d19 MB |
214 | puts ("Bad Data Hash\n"); |
215 | return 1; | |
216 | } | |
217 | ||
218 | /* get fpga subimage data address and length */ | |
fc598412 MS |
219 | if (fit_image_get_data(fit_hdr, noffset, |
220 | &fit_data, &data_size)) { | |
221 | puts("Fpga subimage data not found\n"); | |
c28c4d19 MB |
222 | return 1; |
223 | } | |
224 | ||
fc598412 | 225 | rc = fpga_load(dev, fit_data, data_size); |
c28c4d19 | 226 | } |
d5934ad7 MB |
227 | break; |
228 | #endif | |
229 | default: | |
fc598412 | 230 | puts("** Unknown image type\n"); |
d5934ad7 MB |
231 | rc = FPGA_FAIL; |
232 | break; | |
f0ff4692 SR |
233 | } |
234 | break; | |
235 | ||
d4ca31c4 | 236 | case FPGA_DUMP: |
fc598412 | 237 | rc = fpga_dump(dev, fpga_data, data_size); |
d4ca31c4 WD |
238 | break; |
239 | ||
240 | default: | |
fc598412 | 241 | printf("Unknown operation\n"); |
4c12eeb8 | 242 | return CMD_RET_USAGE; |
d4ca31c4 | 243 | } |
fc598412 | 244 | return rc; |
4a9cbbe8 WD |
245 | } |
246 | ||
4a9cbbe8 WD |
247 | /* |
248 | * Map op to supported operations. We don't use a table since we | |
249 | * would just have to relocate it from flash anyway. | |
250 | */ | |
fc598412 | 251 | static int fpga_get_op(char *opstr) |
4a9cbbe8 WD |
252 | { |
253 | int op = FPGA_NONE; | |
254 | ||
fc598412 | 255 | if (!strcmp("info", opstr)) |
4a9cbbe8 | 256 | op = FPGA_INFO; |
fc598412 | 257 | else if (!strcmp("loadb", opstr)) |
30ce5ab0 | 258 | op = FPGA_LOADB; |
fc598412 | 259 | else if (!strcmp("load", opstr)) |
4a9cbbe8 | 260 | op = FPGA_LOAD; |
fc598412 | 261 | else if (!strcmp("loadmk", opstr)) |
f0ff4692 | 262 | op = FPGA_LOADMK; |
fc598412 | 263 | else if (!strcmp("dump", opstr)) |
4a9cbbe8 | 264 | op = FPGA_DUMP; |
4a9cbbe8 | 265 | |
fc598412 MS |
266 | if (op == FPGA_NONE) |
267 | printf("Unknown fpga operation \"%s\"\n", opstr); | |
268 | ||
4a9cbbe8 WD |
269 | return op; |
270 | } | |
271 | ||
fc598412 MS |
272 | U_BOOT_CMD(fpga, 6, 1, do_fpga, |
273 | "loadable FPGA image support", | |
274 | "[operation type] [device number] [image address] [image size]\n" | |
275 | "fpga operations:\n" | |
276 | " dump\t[dev]\t\t\tLoad device to memory buffer\n" | |
277 | " info\t[dev]\t\t\tlist known device information\n" | |
278 | " load\t[dev] [address] [size]\tLoad device from memory buffer\n" | |
279 | " loadb\t[dev] [address] [size]\t" | |
280 | "Load device from bitstream buffer (Xilinx only)\n" | |
281 | " loadmk [dev] [address]\tLoad device generated with mkimage" | |
c28c4d19 | 282 | #if defined(CONFIG_FIT) |
fc598412 MS |
283 | "\n" |
284 | "\tFor loadmk operating on FIT format uImage address must include\n" | |
285 | "\tsubimage unit name in the form of addr:<subimg_uname>" | |
c28c4d19 MB |
286 | #endif |
287 | ); |