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Commit | Line | Data |
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4a9cbbe8 WD |
1 | /* |
2 | * (C) Copyright 2000, 2001 | |
3 | * Rich Ireland, Enterasys Networks, rireland@enterasys.com. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
4a9cbbe8 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * FPGA support | |
10 | */ | |
11 | #include <common.h> | |
12 | #include <command.h> | |
8bde7f77 | 13 | #include <fpga.h> |
1a897668 | 14 | #include <fs.h> |
c3d2b4b4 | 15 | #include <malloc.h> |
4a9cbbe8 | 16 | |
4a9cbbe8 | 17 | /* Local functions */ |
fc598412 | 18 | static int fpga_get_op(char *opstr); |
4a9cbbe8 WD |
19 | |
20 | /* Local defines */ | |
21 | #define FPGA_NONE -1 | |
22 | #define FPGA_INFO 0 | |
23 | #define FPGA_LOAD 1 | |
30ce5ab0 | 24 | #define FPGA_LOADB 2 |
4a9cbbe8 | 25 | #define FPGA_DUMP 3 |
f0ff4692 | 26 | #define FPGA_LOADMK 4 |
67193864 MS |
27 | #define FPGA_LOADP 5 |
28 | #define FPGA_LOADBP 6 | |
1a897668 | 29 | #define FPGA_LOADFS 7 |
4a9cbbe8 WD |
30 | |
31 | /* ------------------------------------------------------------------------- */ | |
32 | /* command form: | |
33 | * fpga <op> <device number> <data addr> <datasize> | |
34 | * where op is 'load', 'dump', or 'info' | |
35 | * If there is no device number field, the fpga environment variable is used. | |
36 | * If there is no data addr field, the fpgadata environment variable is used. | |
37 | * The info command requires no data address field. | |
38 | */ | |
fc598412 | 39 | int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) |
4a9cbbe8 | 40 | { |
d4ca31c4 WD |
41 | int op, dev = FPGA_INVALID_DEVICE; |
42 | size_t data_size = 0; | |
43 | void *fpga_data = NULL; | |
fc598412 MS |
44 | char *devstr = getenv("fpga"); |
45 | char *datastr = getenv("fpgadata"); | |
d4ca31c4 | 46 | int rc = FPGA_FAIL; |
a790b5b2 | 47 | int wrong_parms = 0; |
fc598412 | 48 | #if defined(CONFIG_FIT) |
c28c4d19 MB |
49 | const char *fit_uname = NULL; |
50 | ulong fit_addr; | |
51 | #endif | |
1a897668 SDPP |
52 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
53 | fpga_fs_info fpga_fsinfo; | |
54 | fpga_fsinfo.fstype = FS_TYPE_ANY; | |
55 | #endif | |
d4ca31c4 WD |
56 | |
57 | if (devstr) | |
fc598412 | 58 | dev = (int) simple_strtoul(devstr, NULL, 16); |
d4ca31c4 | 59 | if (datastr) |
fc598412 | 60 | fpga_data = (void *)simple_strtoul(datastr, NULL, 16); |
d4ca31c4 WD |
61 | |
62 | switch (argc) { | |
1a897668 SDPP |
63 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
64 | case 9: | |
65 | fpga_fsinfo.blocksize = (unsigned int) | |
66 | simple_strtoul(argv[5], NULL, 16); | |
67 | fpga_fsinfo.interface = argv[6]; | |
68 | fpga_fsinfo.dev_part = argv[7]; | |
69 | fpga_fsinfo.filename = argv[8]; | |
70 | #endif | |
d4ca31c4 | 71 | case 5: /* fpga <op> <dev> <data> <datasize> */ |
fc598412 | 72 | data_size = simple_strtoul(argv[4], NULL, 16); |
c28c4d19 | 73 | |
d4ca31c4 | 74 | case 4: /* fpga <op> <dev> <data> */ |
c28c4d19 | 75 | #if defined(CONFIG_FIT) |
fc598412 MS |
76 | if (fit_parse_subimage(argv[3], (ulong)fpga_data, |
77 | &fit_addr, &fit_uname)) { | |
c28c4d19 | 78 | fpga_data = (void *)fit_addr; |
fc598412 MS |
79 | debug("* fpga: subimage '%s' from FIT image ", |
80 | fit_uname); | |
81 | debug("at 0x%08lx\n", fit_addr); | |
c28c4d19 MB |
82 | } else |
83 | #endif | |
84 | { | |
fc598412 | 85 | fpga_data = (void *)simple_strtoul(argv[3], NULL, 16); |
06297db0 | 86 | debug("* fpga: cmdline image address = 0x%08lx\n", |
fc598412 | 87 | (ulong)fpga_data); |
c28c4d19 | 88 | } |
fc598412 | 89 | debug("%s: fpga_data = 0x%x\n", __func__, (uint)fpga_data); |
c28c4d19 | 90 | |
d4ca31c4 | 91 | case 3: /* fpga <op> <dev | data addr> */ |
fc598412 | 92 | dev = (int)simple_strtoul(argv[2], NULL, 16); |
06297db0 | 93 | debug("%s: device = %d\n", __func__, dev); |
d4ca31c4 | 94 | /* FIXME - this is a really weak test */ |
fc598412 MS |
95 | if ((argc == 3) && (dev > fpga_count())) { |
96 | /* must be buffer ptr */ | |
06297db0 | 97 | debug("%s: Assuming buffer pointer in arg 3\n", |
fc598412 | 98 | __func__); |
c28c4d19 MB |
99 | |
100 | #if defined(CONFIG_FIT) | |
fc598412 MS |
101 | if (fit_parse_subimage(argv[2], (ulong)fpga_data, |
102 | &fit_addr, &fit_uname)) { | |
c28c4d19 | 103 | fpga_data = (void *)fit_addr; |
fc598412 MS |
104 | debug("* fpga: subimage '%s' from FIT image ", |
105 | fit_uname); | |
106 | debug("at 0x%08lx\n", fit_addr); | |
c28c4d19 MB |
107 | } else |
108 | #endif | |
109 | { | |
fc598412 MS |
110 | fpga_data = (void *)dev; |
111 | debug("* fpga: cmdline image addr = 0x%08lx\n", | |
112 | (ulong)fpga_data); | |
c28c4d19 MB |
113 | } |
114 | ||
06297db0 | 115 | debug("%s: fpga_data = 0x%x\n", |
fc598412 | 116 | __func__, (uint)fpga_data); |
d4ca31c4 WD |
117 | dev = FPGA_INVALID_DEVICE; /* reset device num */ |
118 | } | |
c28c4d19 | 119 | |
d4ca31c4 | 120 | case 2: /* fpga <op> */ |
fc598412 | 121 | op = (int)fpga_get_op(argv[1]); |
d4ca31c4 | 122 | break; |
c28c4d19 | 123 | |
d4ca31c4 | 124 | default: |
fc598412 | 125 | debug("%s: Too many or too few args (%d)\n", __func__, argc); |
d4ca31c4 WD |
126 | op = FPGA_NONE; /* force usage display */ |
127 | break; | |
128 | } | |
129 | ||
a790b5b2 SB |
130 | if (dev == FPGA_INVALID_DEVICE) { |
131 | puts("FPGA device not specified\n"); | |
132 | op = FPGA_NONE; | |
133 | } | |
134 | ||
135 | switch (op) { | |
136 | case FPGA_NONE: | |
137 | case FPGA_INFO: | |
138 | break; | |
1a897668 SDPP |
139 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
140 | case FPGA_LOADFS: | |
141 | /* Blocksize can be zero */ | |
142 | if (!fpga_fsinfo.interface || !fpga_fsinfo.dev_part || | |
143 | !fpga_fsinfo.filename) | |
144 | wrong_parms = 1; | |
145 | #endif | |
a790b5b2 | 146 | case FPGA_LOAD: |
67193864 | 147 | case FPGA_LOADP: |
a790b5b2 | 148 | case FPGA_LOADB: |
67193864 | 149 | case FPGA_LOADBP: |
a790b5b2 SB |
150 | case FPGA_DUMP: |
151 | if (!fpga_data || !data_size) | |
152 | wrong_parms = 1; | |
153 | break; | |
64e809af | 154 | #if defined(CONFIG_CMD_FPGA_LOADMK) |
a790b5b2 SB |
155 | case FPGA_LOADMK: |
156 | if (!fpga_data) | |
157 | wrong_parms = 1; | |
158 | break; | |
64e809af | 159 | #endif |
a790b5b2 SB |
160 | } |
161 | ||
162 | if (wrong_parms) { | |
163 | puts("Wrong parameters for FPGA request\n"); | |
164 | op = FPGA_NONE; | |
165 | } | |
166 | ||
d4ca31c4 WD |
167 | switch (op) { |
168 | case FPGA_NONE: | |
4c12eeb8 | 169 | return CMD_RET_USAGE; |
d4ca31c4 WD |
170 | |
171 | case FPGA_INFO: | |
fc598412 | 172 | rc = fpga_info(dev); |
d4ca31c4 WD |
173 | break; |
174 | ||
175 | case FPGA_LOAD: | |
7a78bd26 | 176 | rc = fpga_load(dev, fpga_data, data_size, BIT_FULL); |
d4ca31c4 WD |
177 | break; |
178 | ||
67193864 MS |
179 | #if defined(CONFIG_CMD_FPGA_LOADP) |
180 | case FPGA_LOADP: | |
181 | rc = fpga_load(dev, fpga_data, data_size, BIT_PARTIAL); | |
182 | break; | |
183 | #endif | |
184 | ||
30ce5ab0 | 185 | case FPGA_LOADB: |
7a78bd26 | 186 | rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_FULL); |
30ce5ab0 WD |
187 | break; |
188 | ||
67193864 MS |
189 | #if defined(CONFIG_CMD_FPGA_LOADBP) |
190 | case FPGA_LOADBP: | |
191 | rc = fpga_loadbitstream(dev, fpga_data, data_size, BIT_PARTIAL); | |
192 | break; | |
193 | #endif | |
194 | ||
1a897668 SDPP |
195 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
196 | case FPGA_LOADFS: | |
197 | rc = fpga_fsload(dev, fpga_data, data_size, &fpga_fsinfo); | |
198 | break; | |
199 | #endif | |
200 | ||
64e809af | 201 | #if defined(CONFIG_CMD_FPGA_LOADMK) |
f0ff4692 | 202 | case FPGA_LOADMK: |
fc598412 | 203 | switch (genimg_get_format(fpga_data)) { |
21d29f7f | 204 | #if defined(CONFIG_IMAGE_FORMAT_LEGACY) |
d5934ad7 MB |
205 | case IMAGE_FORMAT_LEGACY: |
206 | { | |
fc598412 MS |
207 | image_header_t *hdr = |
208 | (image_header_t *)fpga_data; | |
209 | ulong data; | |
32d7cdd3 MS |
210 | uint8_t comp; |
211 | ||
212 | comp = image_get_comp(hdr); | |
213 | if (comp == IH_COMP_GZIP) { | |
1b63aaa5 | 214 | #if defined(CONFIG_GZIP) |
32d7cdd3 MS |
215 | ulong image_buf = image_get_data(hdr); |
216 | data = image_get_load(hdr); | |
217 | ulong image_size = ~0UL; | |
218 | ||
219 | if (gunzip((void *)data, ~0UL, | |
220 | (void *)image_buf, | |
221 | &image_size) != 0) { | |
222 | puts("GUNZIP: error\n"); | |
223 | return 1; | |
224 | } | |
225 | data_size = image_size; | |
1b63aaa5 MS |
226 | #else |
227 | puts("Gunzip image is not supported\n"); | |
228 | return 1; | |
229 | #endif | |
32d7cdd3 MS |
230 | } else { |
231 | data = (ulong)image_get_data(hdr); | |
232 | data_size = image_get_data_size(hdr); | |
233 | } | |
7a78bd26 MS |
234 | rc = fpga_load(dev, (void *)data, data_size, |
235 | BIT_FULL); | |
f0ff4692 | 236 | } |
d5934ad7 | 237 | break; |
21d29f7f | 238 | #endif |
d5934ad7 MB |
239 | #if defined(CONFIG_FIT) |
240 | case IMAGE_FORMAT_FIT: | |
c28c4d19 MB |
241 | { |
242 | const void *fit_hdr = (const void *)fpga_data; | |
243 | int noffset; | |
e6a857da | 244 | const void *fit_data; |
c28c4d19 MB |
245 | |
246 | if (fit_uname == NULL) { | |
fc598412 | 247 | puts("No FIT subimage unit name\n"); |
c28c4d19 MB |
248 | return 1; |
249 | } | |
250 | ||
fc598412 MS |
251 | if (!fit_check_format(fit_hdr)) { |
252 | puts("Bad FIT image format\n"); | |
c28c4d19 MB |
253 | return 1; |
254 | } | |
255 | ||
256 | /* get fpga component image node offset */ | |
fc598412 MS |
257 | noffset = fit_image_get_node(fit_hdr, |
258 | fit_uname); | |
c28c4d19 | 259 | if (noffset < 0) { |
fc598412 MS |
260 | printf("Can't find '%s' FIT subimage\n", |
261 | fit_uname); | |
c28c4d19 MB |
262 | return 1; |
263 | } | |
264 | ||
265 | /* verify integrity */ | |
b8da8366 | 266 | if (!fit_image_verify(fit_hdr, noffset)) { |
c28c4d19 MB |
267 | puts ("Bad Data Hash\n"); |
268 | return 1; | |
269 | } | |
270 | ||
271 | /* get fpga subimage data address and length */ | |
fc598412 MS |
272 | if (fit_image_get_data(fit_hdr, noffset, |
273 | &fit_data, &data_size)) { | |
274 | puts("Fpga subimage data not found\n"); | |
c28c4d19 MB |
275 | return 1; |
276 | } | |
277 | ||
7a78bd26 MS |
278 | rc = fpga_load(dev, fit_data, data_size, |
279 | BIT_FULL); | |
c28c4d19 | 280 | } |
d5934ad7 MB |
281 | break; |
282 | #endif | |
283 | default: | |
fc598412 | 284 | puts("** Unknown image type\n"); |
d5934ad7 MB |
285 | rc = FPGA_FAIL; |
286 | break; | |
f0ff4692 SR |
287 | } |
288 | break; | |
64e809af | 289 | #endif |
f0ff4692 | 290 | |
d4ca31c4 | 291 | case FPGA_DUMP: |
fc598412 | 292 | rc = fpga_dump(dev, fpga_data, data_size); |
d4ca31c4 WD |
293 | break; |
294 | ||
295 | default: | |
fc598412 | 296 | printf("Unknown operation\n"); |
4c12eeb8 | 297 | return CMD_RET_USAGE; |
d4ca31c4 | 298 | } |
fc598412 | 299 | return rc; |
4a9cbbe8 WD |
300 | } |
301 | ||
4a9cbbe8 WD |
302 | /* |
303 | * Map op to supported operations. We don't use a table since we | |
304 | * would just have to relocate it from flash anyway. | |
305 | */ | |
fc598412 | 306 | static int fpga_get_op(char *opstr) |
4a9cbbe8 WD |
307 | { |
308 | int op = FPGA_NONE; | |
309 | ||
fc598412 | 310 | if (!strcmp("info", opstr)) |
4a9cbbe8 | 311 | op = FPGA_INFO; |
fc598412 | 312 | else if (!strcmp("loadb", opstr)) |
30ce5ab0 | 313 | op = FPGA_LOADB; |
fc598412 | 314 | else if (!strcmp("load", opstr)) |
4a9cbbe8 | 315 | op = FPGA_LOAD; |
67193864 MS |
316 | #if defined(CONFIG_CMD_FPGA_LOADP) |
317 | else if (!strcmp("loadp", opstr)) | |
318 | op = FPGA_LOADP; | |
319 | #endif | |
320 | #if defined(CONFIG_CMD_FPGA_LOADBP) | |
321 | else if (!strcmp("loadbp", opstr)) | |
322 | op = FPGA_LOADBP; | |
323 | #endif | |
1a897668 SDPP |
324 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
325 | else if (!strcmp("loadfs", opstr)) | |
326 | op = FPGA_LOADFS; | |
327 | #endif | |
64e809af | 328 | #if defined(CONFIG_CMD_FPGA_LOADMK) |
fc598412 | 329 | else if (!strcmp("loadmk", opstr)) |
f0ff4692 | 330 | op = FPGA_LOADMK; |
64e809af | 331 | #endif |
fc598412 | 332 | else if (!strcmp("dump", opstr)) |
4a9cbbe8 | 333 | op = FPGA_DUMP; |
4a9cbbe8 | 334 | |
fc598412 MS |
335 | if (op == FPGA_NONE) |
336 | printf("Unknown fpga operation \"%s\"\n", opstr); | |
337 | ||
4a9cbbe8 WD |
338 | return op; |
339 | } | |
340 | ||
1a897668 SDPP |
341 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
342 | U_BOOT_CMD(fpga, 9, 1, do_fpga, | |
343 | #else | |
fc598412 | 344 | U_BOOT_CMD(fpga, 6, 1, do_fpga, |
1a897668 | 345 | #endif |
fc598412 MS |
346 | "loadable FPGA image support", |
347 | "[operation type] [device number] [image address] [image size]\n" | |
348 | "fpga operations:\n" | |
2d73f0d6 | 349 | " dump\t[dev] [address] [size]\tLoad device to memory buffer\n" |
fc598412 MS |
350 | " info\t[dev]\t\t\tlist known device information\n" |
351 | " load\t[dev] [address] [size]\tLoad device from memory buffer\n" | |
67193864 MS |
352 | #if defined(CONFIG_CMD_FPGA_LOADP) |
353 | " loadp\t[dev] [address] [size]\t" | |
354 | "Load device from memory buffer with partial bitstream\n" | |
355 | #endif | |
fc598412 MS |
356 | " loadb\t[dev] [address] [size]\t" |
357 | "Load device from bitstream buffer (Xilinx only)\n" | |
67193864 MS |
358 | #if defined(CONFIG_CMD_FPGA_LOADBP) |
359 | " loadbp\t[dev] [address] [size]\t" | |
360 | "Load device from bitstream buffer with partial bitstream" | |
361 | "(Xilinx only)\n" | |
362 | #endif | |
1a897668 SDPP |
363 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
364 | "Load device from filesystem (FAT by default) (Xilinx only)\n" | |
365 | " loadfs [dev] [address] [image size] [blocksize] <interface>\n" | |
366 | " [<dev[:part]>] <filename>\n" | |
367 | #endif | |
64e809af | 368 | #if defined(CONFIG_CMD_FPGA_LOADMK) |
fc598412 | 369 | " loadmk [dev] [address]\tLoad device generated with mkimage" |
c28c4d19 | 370 | #if defined(CONFIG_FIT) |
fc598412 MS |
371 | "\n" |
372 | "\tFor loadmk operating on FIT format uImage address must include\n" | |
373 | "\tsubimage unit name in the form of addr:<subimg_uname>" | |
c28c4d19 | 374 | #endif |
64e809af | 375 | #endif |
c28c4d19 | 376 | ); |