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81a8824f 1/*
3f4978c7
HS
2 * (C) Copyright 2009
3 * Sergey Kubushyn, himself, ksi@koi8.net
4 *
5 * Changes for unified multibus/multiadapter I2C support.
6 *
81a8824f
WD
7 * (C) Copyright 2001
8 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/*
30 * I2C Functions similar to the standard memory functions.
31 *
32 * There are several parameters in many of the commands that bear further
33 * explanations:
34 *
81a8824f
WD
35 * {i2c_chip} is the I2C chip address (the first byte sent on the bus).
36 * Each I2C chip on the bus has a unique address. On the I2C data bus,
37 * the address is the upper seven bits and the LSB is the "read/write"
38 * bit. Note that the {i2c_chip} address specified on the command
39 * line is not shifted up: e.g. a typical EEPROM memory chip may have
40 * an I2C address of 0x50, but the data put on the bus will be 0xA0
41 * for write and 0xA1 for read. This "non shifted" address notation
42 * matches at least half of the data sheets :-/.
43 *
44 * {addr} is the address (or offset) within the chip. Small memory
45 * chips have 8 bit addresses. Large memory chips have 16 bit
46 * addresses. Other memory chips have 9, 10, or 11 bit addresses.
47 * Many non-memory chips have multiple registers and {addr} is used
48 * as the register index. Some non-memory chips have only one register
49 * and therefore don't need any {addr} parameter.
50 *
51 * The default {addr} parameter is one byte (.1) which works well for
52 * memories and registers with 8 bits of address space.
53 *
54 * You can specify the length of the {addr} field with the optional .0,
55 * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are
56 * manipulating a single register device which doesn't use an address
57 * field, use "0.0" for the address and the ".0" length field will
58 * suppress the address in the I2C data stream. This also works for
59 * successive reads using the I2C auto-incrementing memory pointer.
60 *
61 * If you are manipulating a large memory with 2-byte addresses, use
62 * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal).
63 *
64 * Then there are the unfortunate memory chips that spill the most
65 * significant 1, 2, or 3 bits of address into the chip address byte.
66 * This effectively makes one chip (logically) look like 2, 4, or
67 * 8 chips. This is handled (awkwardly) by #defining
6d0f6bcf 68 * CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
81a8824f
WD
69 * {addr} field (since .1 is the default, it doesn't actually have to
70 * be specified). Examples: given a memory chip at I2C chip address
71 * 0x50, the following would happen...
0f89c54b 72 * i2c md 50 0 10 display 16 bytes starting at 0x000
81a8824f 73 * On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd>
0f89c54b 74 * i2c md 50 100 10 display 16 bytes starting at 0x100
81a8824f 75 * On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd>
0f89c54b 76 * i2c md 50 210 10 display 16 bytes starting at 0x210
81a8824f
WD
77 * On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd>
78 * This is awfully ugly. It would be nice if someone would think up
79 * a better way of handling this.
80 *
81 * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de).
82 */
83
84#include <common.h>
85#include <command.h>
735987c5 86#include <edid.h>
67b23a32 87#include <environment.h>
81a8824f 88#include <i2c.h>
67b23a32 89#include <malloc.h>
81a8824f 90#include <asm/byteorder.h>
2515d843 91#include <linux/compiler.h>
81a8824f 92
3f4978c7
HS
93DECLARE_GLOBAL_DATA_PTR;
94
81a8824f
WD
95/* Display values from last command.
96 * Memory modify remembered values are different from display memory.
97 */
98static uchar i2c_dp_last_chip;
99static uint i2c_dp_last_addr;
100static uint i2c_dp_last_alen;
101static uint i2c_dp_last_length = 0x10;
102
103static uchar i2c_mm_last_chip;
104static uint i2c_mm_last_addr;
105static uint i2c_mm_last_alen;
106
bb99ad6d
BW
107/* If only one I2C bus is present, the list of devices to ignore when
108 * the probe command is issued is represented by a 1D array of addresses.
109 * When multiple buses are present, the list is an array of bus-address
110 * pairs. The following macros take care of this */
111
6d0f6bcf 112#if defined(CONFIG_SYS_I2C_NOPROBES)
9a2accb4 113#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
bb99ad6d
BW
114static struct
115{
116 uchar bus;
117 uchar addr;
6d0f6bcf 118} i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
bb99ad6d
BW
119#define GET_BUS_NUM i2c_get_bus_num()
120#define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
121#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
122#define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
123#else /* single bus */
6d0f6bcf 124static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
bb99ad6d
BW
125#define GET_BUS_NUM 0
126#define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
127#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
128#define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
3f4978c7 129#endif /* defined(CONFIG_SYS_I2C) */
bb99ad6d
BW
130
131#define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0]))
81a8824f
WD
132#endif
133
a266fe95
FM
134#define DISP_LINE_LEN 16
135
06afa388
MV
136/**
137 * i2c_init_board() - Board-specific I2C bus init
138 *
139 * This function is the default no-op implementation of I2C bus
140 * initialization. This function can be overriden by board-specific
141 * implementation if needed.
142 */
2515d843
MV
143__weak
144void i2c_init_board(void)
c649dda5 145{
c649dda5 146}
c649dda5 147
655b34a7 148/* TODO: Implement architecture-specific get/set functions */
06afa388
MV
149
150/**
151 * i2c_get_bus_speed() - Return I2C bus speed
152 *
153 * This function is the default implementation of function for retrieveing
154 * the current I2C bus speed in Hz.
155 *
156 * A driver implementing runtime switching of I2C bus speed must override
157 * this function to report the speed correctly. Simple or legacy drivers
158 * can use this fallback.
159 *
160 * Returns I2C bus speed in Hz.
161 */
3f4978c7
HS
162#if !defined(CONFIG_SYS_I2C)
163/*
164 * TODO: Implement architecture-specific get/set functions
165 * Should go away, if we switched completely to new multibus support
166 */
2515d843
MV
167__weak
168unsigned int i2c_get_bus_speed(void)
655b34a7
PT
169{
170 return CONFIG_SYS_I2C_SPEED;
171}
655b34a7 172
06afa388
MV
173/**
174 * i2c_set_bus_speed() - Configure I2C bus speed
175 * @speed: Newly set speed of the I2C bus in Hz
176 *
177 * This function is the default implementation of function for setting
178 * the I2C bus speed in Hz.
179 *
180 * A driver implementing runtime switching of I2C bus speed must override
181 * this function to report the speed correctly. Simple or legacy drivers
182 * can use this fallback.
183 *
184 * Returns zero on success, negative value on error.
185 */
2515d843
MV
186__weak
187int i2c_set_bus_speed(unsigned int speed)
655b34a7
PT
188{
189 if (speed != CONFIG_SYS_I2C_SPEED)
190 return -1;
191
192 return 0;
193}
3f4978c7 194#endif
655b34a7 195
06afa388
MV
196/**
197 * get_alen() - Small parser helper function to get address length
198 *
199 * Returns the address length.
2c0dc990
FM
200 */
201static uint get_alen(char *arg)
202{
203 int j;
204 int alen;
205
206 alen = 1;
207 for (j = 0; j < 8; j++) {
208 if (arg[j] == '.') {
209 alen = arg[j+1] - '0';
2c0dc990
FM
210 break;
211 } else if (arg[j] == '\0')
212 break;
213 }
214 return alen;
215}
216
06afa388
MV
217/**
218 * do_i2c_read() - Handle the "i2c read" command-line command
219 * @cmdtp: Command data struct pointer
220 * @flag: Command flag
221 * @argc: Command-line argument count
222 * @argv: Array of command-line arguments
223 *
224 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
225 * on error.
226 *
652e5354
FM
227 * Syntax:
228 * i2c read {i2c_chip} {devaddr}{.0, .1, .2} {len} {memaddr}
229 */
54841ab5 230static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
652e5354
FM
231{
232 u_char chip;
233 uint devaddr, alen, length;
234 u_char *memaddr;
652e5354 235
47e26b1b 236 if (argc != 5)
4c12eeb8 237 return CMD_RET_USAGE;
652e5354
FM
238
239 /*
240 * I2C chip address
241 */
242 chip = simple_strtoul(argv[1], NULL, 16);
243
244 /*
245 * I2C data address within the chip. This can be 1 or
246 * 2 bytes long. Some day it might be 3 bytes long :-).
247 */
248 devaddr = simple_strtoul(argv[2], NULL, 16);
2c0dc990 249 alen = get_alen(argv[2]);
7a92e53c 250 if (alen > 3)
4c12eeb8 251 return CMD_RET_USAGE;
652e5354
FM
252
253 /*
254 * Length is the number of objects, not number of bytes.
255 */
256 length = simple_strtoul(argv[3], NULL, 16);
257
258 /*
259 * memaddr is the address where to store things in memory
260 */
261 memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
262
263 if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) {
264 puts ("Error reading the chip.\n");
265 return 1;
266 }
267 return 0;
268}
269
ff5d2dce
YS
270static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
271{
272 u_char chip;
273 uint devaddr, alen, length;
274 u_char *memaddr;
275
276 if (argc != 5)
277 return cmd_usage(cmdtp);
278
279 /*
280 * memaddr is the address where to store things in memory
281 */
282 memaddr = (u_char *)simple_strtoul(argv[1], NULL, 16);
283
284 /*
285 * I2C chip address
286 */
287 chip = simple_strtoul(argv[2], NULL, 16);
288
289 /*
290 * I2C data address within the chip. This can be 1 or
291 * 2 bytes long. Some day it might be 3 bytes long :-).
292 */
293 devaddr = simple_strtoul(argv[3], NULL, 16);
294 alen = get_alen(argv[3]);
295 if (alen > 3)
296 return cmd_usage(cmdtp);
297
298 /*
299 * Length is the number of objects, not number of bytes.
300 */
301 length = simple_strtoul(argv[4], NULL, 16);
302
303 while (length-- > 0) {
304 if (i2c_write(chip, devaddr++, alen, memaddr++, 1) != 0) {
305 puts("Error writing to the chip.\n");
306 return 1;
307 }
308/*
309 * No write delay with FRAM devices.
310 */
311#if !defined(CONFIG_SYS_I2C_FRAM)
312 udelay(11000);
313#endif
314 }
315 return 0;
316}
317
06afa388
MV
318/**
319 * do_i2c_md() - Handle the "i2c md" command-line command
320 * @cmdtp: Command data struct pointer
321 * @flag: Command flag
322 * @argc: Command-line argument count
323 * @argv: Array of command-line arguments
324 *
325 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
326 * on error.
327 *
4a8cf338
FM
328 * Syntax:
329 * i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
330 */
54841ab5 331static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f
WD
332{
333 u_char chip;
334 uint addr, alen, length;
335 int j, nbytes, linebytes;
336
337 /* We use the last specified parameters, unless new ones are
338 * entered.
339 */
340 chip = i2c_dp_last_chip;
341 addr = i2c_dp_last_addr;
342 alen = i2c_dp_last_alen;
343 length = i2c_dp_last_length;
344
47e26b1b 345 if (argc < 3)
4c12eeb8 346 return CMD_RET_USAGE;
81a8824f
WD
347
348 if ((flag & CMD_FLAG_REPEAT) == 0) {
349 /*
350 * New command specified.
351 */
81a8824f
WD
352
353 /*
354 * I2C chip address
355 */
356 chip = simple_strtoul(argv[1], NULL, 16);
357
358 /*
359 * I2C data address within the chip. This can be 1 or
360 * 2 bytes long. Some day it might be 3 bytes long :-).
361 */
362 addr = simple_strtoul(argv[2], NULL, 16);
2c0dc990 363 alen = get_alen(argv[2]);
7a92e53c 364 if (alen > 3)
4c12eeb8 365 return CMD_RET_USAGE;
81a8824f
WD
366
367 /*
368 * If another parameter, it is the length to display.
369 * Length is the number of objects, not number of bytes.
370 */
371 if (argc > 3)
372 length = simple_strtoul(argv[3], NULL, 16);
373 }
374
375 /*
376 * Print the lines.
377 *
378 * We buffer all read data, so we can make sure data is read only
379 * once.
380 */
381 nbytes = length;
382 do {
383 unsigned char linebuf[DISP_LINE_LEN];
384 unsigned char *cp;
385
386 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
387
e857a5bd 388 if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0)
4b9206ed 389 puts ("Error reading the chip.\n");
e857a5bd 390 else {
81a8824f
WD
391 printf("%04x:", addr);
392 cp = linebuf;
393 for (j=0; j<linebytes; j++) {
394 printf(" %02x", *cp++);
395 addr++;
396 }
4b9206ed 397 puts (" ");
81a8824f
WD
398 cp = linebuf;
399 for (j=0; j<linebytes; j++) {
400 if ((*cp < 0x20) || (*cp > 0x7e))
4b9206ed 401 puts (".");
81a8824f
WD
402 else
403 printf("%c", *cp);
404 cp++;
405 }
4b9206ed 406 putc ('\n');
81a8824f
WD
407 }
408 nbytes -= linebytes;
409 } while (nbytes > 0);
410
411 i2c_dp_last_chip = chip;
412 i2c_dp_last_addr = addr;
413 i2c_dp_last_alen = alen;
414 i2c_dp_last_length = length;
415
416 return 0;
417}
418
06afa388
MV
419/**
420 * do_i2c_mw() - Handle the "i2c mw" command-line command
421 * @cmdtp: Command data struct pointer
422 * @flag: Command flag
423 * @argc: Command-line argument count
424 * @argv: Array of command-line arguments
425 *
426 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
427 * on error.
81a8824f
WD
428 *
429 * Syntax:
0f89c54b 430 * i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
81a8824f 431 */
54841ab5 432static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f
WD
433{
434 uchar chip;
435 ulong addr;
436 uint alen;
437 uchar byte;
438 int count;
81a8824f 439
47e26b1b 440 if ((argc < 4) || (argc > 5))
4c12eeb8 441 return CMD_RET_USAGE;
81a8824f
WD
442
443 /*
53677ef1
WD
444 * Chip is always specified.
445 */
81a8824f
WD
446 chip = simple_strtoul(argv[1], NULL, 16);
447
448 /*
449 * Address is always specified.
450 */
451 addr = simple_strtoul(argv[2], NULL, 16);
2c0dc990 452 alen = get_alen(argv[2]);
7a92e53c 453 if (alen > 3)
4c12eeb8 454 return CMD_RET_USAGE;
81a8824f
WD
455
456 /*
457 * Value to write is always specified.
458 */
459 byte = simple_strtoul(argv[3], NULL, 16);
460
461 /*
462 * Optional count
463 */
e857a5bd 464 if (argc == 5)
81a8824f 465 count = simple_strtoul(argv[4], NULL, 16);
e857a5bd 466 else
81a8824f 467 count = 1;
81a8824f
WD
468
469 while (count-- > 0) {
e857a5bd 470 if (i2c_write(chip, addr++, alen, &byte, 1) != 0)
4b9206ed 471 puts ("Error writing the chip.\n");
81a8824f
WD
472 /*
473 * Wait for the write to complete. The write can take
474 * up to 10mSec (we allow a little more time).
81a8824f 475 */
d4f5c728 476/*
477 * No write delay with FRAM devices.
478 */
6d0f6bcf 479#if !defined(CONFIG_SYS_I2C_FRAM)
81a8824f 480 udelay(11000);
d4f5c728 481#endif
81a8824f
WD
482 }
483
06afa388 484 return 0;
81a8824f
WD
485}
486
06afa388
MV
487/**
488 * do_i2c_crc() - Handle the "i2c crc32" command-line command
489 * @cmdtp: Command data struct pointer
490 * @flag: Command flag
491 * @argc: Command-line argument count
492 * @argv: Array of command-line arguments
493 *
494 * Calculate a CRC on memory
495 *
496 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
497 * on error.
81a8824f
WD
498 *
499 * Syntax:
0f89c54b 500 * i2c crc32 {i2c_chip} {addr}{.0, .1, .2} {count}
81a8824f 501 */
54841ab5 502static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f
WD
503{
504 uchar chip;
505 ulong addr;
506 uint alen;
507 int count;
508 uchar byte;
509 ulong crc;
510 ulong err;
81a8824f 511
47e26b1b 512 if (argc < 4)
4c12eeb8 513 return CMD_RET_USAGE;
81a8824f
WD
514
515 /*
53677ef1
WD
516 * Chip is always specified.
517 */
81a8824f
WD
518 chip = simple_strtoul(argv[1], NULL, 16);
519
520 /*
521 * Address is always specified.
522 */
523 addr = simple_strtoul(argv[2], NULL, 16);
2c0dc990 524 alen = get_alen(argv[2]);
7a92e53c 525 if (alen > 3)
4c12eeb8 526 return CMD_RET_USAGE;
81a8824f
WD
527
528 /*
529 * Count is always specified
530 */
531 count = simple_strtoul(argv[3], NULL, 16);
532
533 printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1);
534 /*
535 * CRC a byte at a time. This is going to be slooow, but hey, the
536 * memories are small and slow too so hopefully nobody notices.
537 */
538 crc = 0;
539 err = 0;
e857a5bd
TT
540 while (count-- > 0) {
541 if (i2c_read(chip, addr, alen, &byte, 1) != 0)
81a8824f 542 err++;
81a8824f
WD
543 crc = crc32 (crc, &byte, 1);
544 addr++;
545 }
e857a5bd 546 if (err > 0)
4b9206ed 547 puts ("Error reading the chip,\n");
e857a5bd 548 else
81a8824f 549 printf ("%08lx\n", crc);
81a8824f
WD
550
551 return 0;
552}
553
06afa388
MV
554/**
555 * mod_i2c_mem() - Handle the "i2c mm" and "i2c nm" command-line command
556 * @cmdtp: Command data struct pointer
557 * @flag: Command flag
558 * @argc: Command-line argument count
559 * @argv: Array of command-line arguments
560 *
561 * Modify memory.
562 *
563 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
564 * on error.
81a8824f
WD
565 *
566 * Syntax:
0f89c54b
PT
567 * i2c mm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
568 * i2c nm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
81a8824f 569 */
81a8824f 570static int
54841ab5 571mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
81a8824f
WD
572{
573 uchar chip;
574 ulong addr;
575 uint alen;
576 ulong data;
577 int size = 1;
578 int nbytes;
81a8824f 579
47e26b1b 580 if (argc != 3)
4c12eeb8 581 return CMD_RET_USAGE;
81a8824f
WD
582
583#ifdef CONFIG_BOOT_RETRY_TIME
584 reset_cmd_timeout(); /* got a good command to get here */
585#endif
586 /*
587 * We use the last specified parameters, unless new ones are
588 * entered.
589 */
590 chip = i2c_mm_last_chip;
591 addr = i2c_mm_last_addr;
592 alen = i2c_mm_last_alen;
593
594 if ((flag & CMD_FLAG_REPEAT) == 0) {
595 /*
596 * New command specified. Check for a size specification.
597 * Defaults to byte if no or incorrect specification.
598 */
599 size = cmd_get_data_size(argv[0], 1);
600
601 /*
53677ef1
WD
602 * Chip is always specified.
603 */
81a8824f
WD
604 chip = simple_strtoul(argv[1], NULL, 16);
605
606 /*
607 * Address is always specified.
608 */
609 addr = simple_strtoul(argv[2], NULL, 16);
2c0dc990 610 alen = get_alen(argv[2]);
7a92e53c 611 if (alen > 3)
4c12eeb8 612 return CMD_RET_USAGE;
81a8824f
WD
613 }
614
615 /*
616 * Print the address, followed by value. Then accept input for
617 * the next value. A non-converted value exits.
618 */
619 do {
620 printf("%08lx:", addr);
e857a5bd 621 if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0)
4b9206ed 622 puts ("\nError reading the chip,\n");
e857a5bd 623 else {
81a8824f 624 data = cpu_to_be32(data);
e857a5bd 625 if (size == 1)
81a8824f 626 printf(" %02lx", (data >> 24) & 0x000000FF);
e857a5bd 627 else if (size == 2)
81a8824f 628 printf(" %04lx", (data >> 16) & 0x0000FFFF);
e857a5bd 629 else
81a8824f 630 printf(" %08lx", data);
81a8824f
WD
631 }
632
633 nbytes = readline (" ? ");
634 if (nbytes == 0) {
635 /*
636 * <CR> pressed as only input, don't modify current
637 * location and move to next.
638 */
639 if (incrflag)
640 addr += size;
641 nbytes = size;
642#ifdef CONFIG_BOOT_RETRY_TIME
643 reset_cmd_timeout(); /* good enough to not time out */
644#endif
645 }
646#ifdef CONFIG_BOOT_RETRY_TIME
e857a5bd 647 else if (nbytes == -2)
81a8824f 648 break; /* timed out, exit the command */
81a8824f
WD
649#endif
650 else {
651 char *endp;
652
653 data = simple_strtoul(console_buffer, &endp, 16);
e857a5bd 654 if (size == 1)
81a8824f 655 data = data << 24;
e857a5bd 656 else if (size == 2)
81a8824f 657 data = data << 16;
81a8824f
WD
658 data = be32_to_cpu(data);
659 nbytes = endp - console_buffer;
660 if (nbytes) {
661#ifdef CONFIG_BOOT_RETRY_TIME
662 /*
663 * good enough to not time out
664 */
665 reset_cmd_timeout();
666#endif
e857a5bd 667 if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0)
4b9206ed 668 puts ("Error writing the chip.\n");
6d0f6bcf
JCPV
669#ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
670 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
2535d602 671#endif
81a8824f
WD
672 if (incrflag)
673 addr += size;
674 }
675 }
676 } while (nbytes);
677
0800707b
PT
678 i2c_mm_last_chip = chip;
679 i2c_mm_last_addr = addr;
680 i2c_mm_last_alen = alen;
81a8824f
WD
681
682 return 0;
683}
684
06afa388
MV
685/**
686 * do_i2c_probe() - Handle the "i2c probe" command-line command
687 * @cmdtp: Command data struct pointer
688 * @flag: Command flag
689 * @argc: Command-line argument count
690 * @argv: Array of command-line arguments
691 *
692 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
693 * on error.
694 *
81a8824f 695 * Syntax:
54b99e51
EN
696 * i2c probe {addr}
697 *
698 * Returns zero (success) if one or more I2C devices was found
81a8824f 699 */
54841ab5 700static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f
WD
701{
702 int j;
54b99e51
EN
703 int addr = -1;
704 int found = 0;
6d0f6bcf 705#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 706 int k, skip;
3f4978c7 707 unsigned int bus = GET_BUS_NUM;
bb99ad6d 708#endif /* NOPROBES */
81a8824f 709
54b99e51
EN
710 if (argc == 2)
711 addr = simple_strtol(argv[1], 0, 16);
712
4b9206ed 713 puts ("Valid chip addresses:");
e857a5bd 714 for (j = 0; j < 128; j++) {
54b99e51
EN
715 if ((0 <= addr) && (j != addr))
716 continue;
717
6d0f6bcf 718#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 719 skip = 0;
e857a5bd
TT
720 for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
721 if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
81a8824f
WD
722 skip = 1;
723 break;
724 }
725 }
726 if (skip)
727 continue;
728#endif
54b99e51 729 if (i2c_probe(j) == 0) {
81a8824f 730 printf(" %02X", j);
54b99e51
EN
731 found++;
732 }
81a8824f 733 }
4b9206ed 734 putc ('\n');
81a8824f 735
6d0f6bcf 736#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 737 puts ("Excluded chip addresses:");
e857a5bd
TT
738 for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
739 if (COMPARE_BUS(bus,k))
bb99ad6d
BW
740 printf(" %02X", NO_PROBE_ADDR(k));
741 }
4b9206ed 742 putc ('\n');
81a8824f
WD
743#endif
744
54b99e51 745 return (0 == found);
81a8824f
WD
746}
747
06afa388
MV
748/**
749 * do_i2c_loop() - Handle the "i2c loop" command-line command
750 * @cmdtp: Command data struct pointer
751 * @flag: Command flag
752 * @argc: Command-line argument count
753 * @argv: Array of command-line arguments
754 *
755 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
756 * on error.
757 *
81a8824f 758 * Syntax:
0f89c54b 759 * i2c loop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
81a8824f
WD
760 * {length} - Number of bytes to read
761 * {delay} - A DECIMAL number and defaults to 1000 uSec
762 */
54841ab5 763static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f
WD
764{
765 u_char chip;
766 ulong alen;
767 uint addr;
768 uint length;
769 u_char bytes[16];
770 int delay;
81a8824f 771
47e26b1b 772 if (argc < 3)
4c12eeb8 773 return CMD_RET_USAGE;
81a8824f
WD
774
775 /*
776 * Chip is always specified.
777 */
778 chip = simple_strtoul(argv[1], NULL, 16);
779
780 /*
781 * Address is always specified.
782 */
783 addr = simple_strtoul(argv[2], NULL, 16);
2c0dc990 784 alen = get_alen(argv[2]);
7a92e53c 785 if (alen > 3)
4c12eeb8 786 return CMD_RET_USAGE;
81a8824f
WD
787
788 /*
789 * Length is the number of objects, not number of bytes.
790 */
791 length = 1;
792 length = simple_strtoul(argv[3], NULL, 16);
e857a5bd 793 if (length > sizeof(bytes))
81a8824f 794 length = sizeof(bytes);
81a8824f
WD
795
796 /*
797 * The delay time (uSec) is optional.
798 */
799 delay = 1000;
e857a5bd 800 if (argc > 3)
81a8824f 801 delay = simple_strtoul(argv[4], NULL, 10);
81a8824f
WD
802 /*
803 * Run the loop...
804 */
e857a5bd
TT
805 while (1) {
806 if (i2c_read(chip, addr, alen, bytes, length) != 0)
4b9206ed 807 puts ("Error reading the chip.\n");
81a8824f
WD
808 udelay(delay);
809 }
810
811 /* NOTREACHED */
812 return 0;
813}
814
81a8824f
WD
815/*
816 * The SDRAM command is separately configured because many
817 * (most?) embedded boards don't use SDRAM DIMMs.
06afa388
MV
818 *
819 * FIXME: Document and probably move elsewhere!
81a8824f 820 */
c76fe474 821#if defined(CONFIG_CMD_SDRAM)
632de067
LJ
822static void print_ddr2_tcyc (u_char const b)
823{
824 printf ("%d.", (b >> 4) & 0x0F);
825 switch (b & 0x0F) {
826 case 0x0:
827 case 0x1:
828 case 0x2:
829 case 0x3:
830 case 0x4:
831 case 0x5:
832 case 0x6:
833 case 0x7:
834 case 0x8:
835 case 0x9:
836 printf ("%d ns\n", b & 0x0F);
837 break;
838 case 0xA:
839 puts ("25 ns\n");
840 break;
841 case 0xB:
842 puts ("33 ns\n");
843 break;
844 case 0xC:
845 puts ("66 ns\n");
846 break;
847 case 0xD:
848 puts ("75 ns\n");
849 break;
850 default:
851 puts ("?? ns\n");
852 break;
853 }
854}
855
856static void decode_bits (u_char const b, char const *str[], int const do_once)
857{
858 u_char mask;
859
860 for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
861 if (b & mask) {
862 puts (*str);
863 if (do_once)
864 return;
865 }
866 }
867}
81a8824f
WD
868
869/*
870 * Syntax:
0f89c54b 871 * i2c sdram {i2c_chip}
81a8824f 872 */
54841ab5 873static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
81a8824f 874{
632de067
LJ
875 enum { unknown, EDO, SDRAM, DDR2 } type;
876
81a8824f
WD
877 u_char chip;
878 u_char data[128];
879 u_char cksum;
880 int j;
881
632de067
LJ
882 static const char *decode_CAS_DDR2[] = {
883 " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
884 };
885
886 static const char *decode_CAS_default[] = {
887 " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
888 };
889
890 static const char *decode_CS_WE_default[] = {
891 " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
892 };
893
894 static const char *decode_byte21_default[] = {
895 " TBD (bit 7)\n",
896 " Redundant row address\n",
897 " Differential clock input\n",
898 " Registerd DQMB inputs\n",
899 " Buffered DQMB inputs\n",
900 " On-card PLL\n",
901 " Registered address/control lines\n",
902 " Buffered address/control lines\n"
903 };
904
905 static const char *decode_byte22_DDR2[] = {
906 " TBD (bit 7)\n",
907 " TBD (bit 6)\n",
908 " TBD (bit 5)\n",
909 " TBD (bit 4)\n",
910 " TBD (bit 3)\n",
911 " Supports partial array self refresh\n",
912 " Supports 50 ohm ODT\n",
913 " Supports weak driver\n"
914 };
915
916 static const char *decode_row_density_DDR2[] = {
917 "512 MiB", "256 MiB", "128 MiB", "16 GiB",
918 "8 GiB", "4 GiB", "2 GiB", "1 GiB"
919 };
920
921 static const char *decode_row_density_default[] = {
922 "512 MiB", "256 MiB", "128 MiB", "64 MiB",
923 "32 MiB", "16 MiB", "8 MiB", "4 MiB"
924 };
925
47e26b1b 926 if (argc < 2)
4c12eeb8 927 return CMD_RET_USAGE;
47e26b1b 928
81a8824f
WD
929 /*
930 * Chip is always specified.
632de067
LJ
931 */
932 chip = simple_strtoul (argv[1], NULL, 16);
81a8824f 933
632de067 934 if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
4b9206ed 935 puts ("No SDRAM Serial Presence Detect found.\n");
81a8824f
WD
936 return 1;
937 }
938
939 cksum = 0;
940 for (j = 0; j < 63; j++) {
941 cksum += data[j];
942 }
e857a5bd 943 if (cksum != data[63]) {
81a8824f 944 printf ("WARNING: Configuration data checksum failure:\n"
632de067 945 " is 0x%02x, calculated 0x%02x\n", data[63], cksum);
81a8824f 946 }
632de067 947 printf ("SPD data revision %d.%d\n",
81a8824f 948 (data[62] >> 4) & 0x0F, data[62] & 0x0F);
632de067
LJ
949 printf ("Bytes used 0x%02X\n", data[0]);
950 printf ("Serial memory size 0x%02X\n", 1 << data[1]);
951
4b9206ed 952 puts ("Memory type ");
632de067 953 switch (data[2]) {
0df6b844
LJ
954 case 2:
955 type = EDO;
956 puts ("EDO\n");
957 break;
958 case 4:
959 type = SDRAM;
960 puts ("SDRAM\n");
961 break;
962 case 8:
963 type = DDR2;
964 puts ("DDR2\n");
965 break;
966 default:
967 type = unknown;
968 puts ("unknown\n");
969 break;
81a8824f 970 }
632de067 971
4b9206ed 972 puts ("Row address bits ");
e857a5bd 973 if ((data[3] & 0x00F0) == 0)
632de067 974 printf ("%d\n", data[3] & 0x0F);
e857a5bd 975 else
632de067
LJ
976 printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
977
4b9206ed 978 puts ("Column address bits ");
e857a5bd 979 if ((data[4] & 0x00F0) == 0)
632de067 980 printf ("%d\n", data[4] & 0x0F);
e857a5bd 981 else
632de067 982 printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
0df6b844
LJ
983
984 switch (type) {
985 case DDR2:
632de067
LJ
986 printf ("Number of ranks %d\n",
987 (data[5] & 0x07) + 1);
0df6b844
LJ
988 break;
989 default:
632de067 990 printf ("Module rows %d\n", data[5]);
0df6b844
LJ
991 break;
992 }
993
994 switch (type) {
995 case DDR2:
632de067 996 printf ("Module data width %d bits\n", data[6]);
0df6b844
LJ
997 break;
998 default:
632de067
LJ
999 printf ("Module data width %d bits\n",
1000 (data[7] << 8) | data[6]);
0df6b844
LJ
1001 break;
1002 }
1003
4b9206ed 1004 puts ("Interface signal levels ");
81a8824f 1005 switch(data[8]) {
0df6b844 1006 case 0: puts ("TTL 5.0 V\n"); break;
4b9206ed 1007 case 1: puts ("LVTTL\n"); break;
0df6b844
LJ
1008 case 2: puts ("HSTL 1.5 V\n"); break;
1009 case 3: puts ("SSTL 3.3 V\n"); break;
1010 case 4: puts ("SSTL 2.5 V\n"); break;
1011 case 5: puts ("SSTL 1.8 V\n"); break;
4b9206ed 1012 default: puts ("unknown\n"); break;
81a8824f 1013 }
0df6b844
LJ
1014
1015 switch (type) {
1016 case DDR2:
632de067
LJ
1017 printf ("SDRAM cycle time ");
1018 print_ddr2_tcyc (data[9]);
0df6b844
LJ
1019 break;
1020 default:
632de067
LJ
1021 printf ("SDRAM cycle time %d.%d ns\n",
1022 (data[9] >> 4) & 0x0F, data[9] & 0x0F);
0df6b844
LJ
1023 break;
1024 }
1025
1026 switch (type) {
1027 case DDR2:
632de067
LJ
1028 printf ("SDRAM access time 0.%d%d ns\n",
1029 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
0df6b844
LJ
1030 break;
1031 default:
632de067
LJ
1032 printf ("SDRAM access time %d.%d ns\n",
1033 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
0df6b844
LJ
1034 break;
1035 }
1036
4b9206ed 1037 puts ("EDC configuration ");
632de067 1038 switch (data[11]) {
4b9206ed
WD
1039 case 0: puts ("None\n"); break;
1040 case 1: puts ("Parity\n"); break;
1041 case 2: puts ("ECC\n"); break;
1042 default: puts ("unknown\n"); break;
81a8824f 1043 }
632de067 1044
e857a5bd 1045 if ((data[12] & 0x80) == 0)
4b9206ed 1046 puts ("No self refresh, rate ");
e857a5bd 1047 else
4b9206ed 1048 puts ("Self refresh, rate ");
632de067 1049
81a8824f 1050 switch(data[12] & 0x7F) {
632de067
LJ
1051 case 0: puts ("15.625 us\n"); break;
1052 case 1: puts ("3.9 us\n"); break;
1053 case 2: puts ("7.8 us\n"); break;
1054 case 3: puts ("31.3 us\n"); break;
1055 case 4: puts ("62.5 us\n"); break;
1056 case 5: puts ("125 us\n"); break;
4b9206ed 1057 default: puts ("unknown\n"); break;
81a8824f 1058 }
0df6b844
LJ
1059
1060 switch (type) {
1061 case DDR2:
632de067 1062 printf ("SDRAM width (primary) %d\n", data[13]);
0df6b844
LJ
1063 break;
1064 default:
632de067 1065 printf ("SDRAM width (primary) %d\n", data[13] & 0x7F);
0df6b844 1066 if ((data[13] & 0x80) != 0) {
632de067
LJ
1067 printf (" (second bank) %d\n",
1068 2 * (data[13] & 0x7F));
0df6b844
LJ
1069 }
1070 break;
1071 }
1072
1073 switch (type) {
1074 case DDR2:
1075 if (data[14] != 0)
632de067 1076 printf ("EDC width %d\n", data[14]);
0df6b844
LJ
1077 break;
1078 default:
1079 if (data[14] != 0) {
632de067
LJ
1080 printf ("EDC width %d\n",
1081 data[14] & 0x7F);
0df6b844
LJ
1082
1083 if ((data[14] & 0x80) != 0) {
632de067
LJ
1084 printf (" (second bank) %d\n",
1085 2 * (data[14] & 0x7F));
0df6b844
LJ
1086 }
1087 }
1088 break;
81a8824f 1089 }
0df6b844 1090
632de067
LJ
1091 if (DDR2 != type) {
1092 printf ("Min clock delay, back-to-back random column addresses "
1093 "%d\n", data[15]);
0df6b844
LJ
1094 }
1095
4b9206ed
WD
1096 puts ("Burst length(s) ");
1097 if (data[16] & 0x80) puts (" Page");
1098 if (data[16] & 0x08) puts (" 8");
1099 if (data[16] & 0x04) puts (" 4");
1100 if (data[16] & 0x02) puts (" 2");
1101 if (data[16] & 0x01) puts (" 1");
1102 putc ('\n');
632de067 1103 printf ("Number of banks %d\n", data[17]);
0df6b844
LJ
1104
1105 switch (type) {
1106 case DDR2:
1107 puts ("CAS latency(s) ");
632de067 1108 decode_bits (data[18], decode_CAS_DDR2, 0);
0df6b844
LJ
1109 putc ('\n');
1110 break;
1111 default:
1112 puts ("CAS latency(s) ");
632de067 1113 decode_bits (data[18], decode_CAS_default, 0);
0df6b844
LJ
1114 putc ('\n');
1115 break;
1116 }
1117
1118 if (DDR2 != type) {
1119 puts ("CS latency(s) ");
632de067 1120 decode_bits (data[19], decode_CS_WE_default, 0);
0df6b844
LJ
1121 putc ('\n');
1122 }
1123
1124 if (DDR2 != type) {
1125 puts ("WE latency(s) ");
632de067 1126 decode_bits (data[20], decode_CS_WE_default, 0);
0df6b844
LJ
1127 putc ('\n');
1128 }
1129
1130 switch (type) {
1131 case DDR2:
1132 puts ("Module attributes:\n");
1133 if (data[21] & 0x80)
1134 puts (" TBD (bit 7)\n");
1135 if (data[21] & 0x40)
1136 puts (" Analysis probe installed\n");
1137 if (data[21] & 0x20)
1138 puts (" TBD (bit 5)\n");
1139 if (data[21] & 0x10)
1140 puts (" FET switch external enable\n");
632de067 1141 printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
0df6b844 1142 if (data[20] & 0x11) {
632de067
LJ
1143 printf (" %d active registers on DIMM\n",
1144 (data[21] & 0x03) + 1);
0df6b844
LJ
1145 }
1146 break;
1147 default:
1148 puts ("Module attributes:\n");
1149 if (!data[21])
1150 puts (" (none)\n");
632de067
LJ
1151 else
1152 decode_bits (data[21], decode_byte21_default, 0);
0df6b844
LJ
1153 break;
1154 }
1155
1156 switch (type) {
1157 case DDR2:
632de067 1158 decode_bits (data[22], decode_byte22_DDR2, 0);
0df6b844
LJ
1159 break;
1160 default:
1161 puts ("Device attributes:\n");
1162 if (data[22] & 0x80) puts (" TBD (bit 7)\n");
1163 if (data[22] & 0x40) puts (" TBD (bit 6)\n");
1164 if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
1165 else puts (" Upper Vcc tolerance 10%\n");
1166 if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
1167 else puts (" Lower Vcc tolerance 10%\n");
1168 if (data[22] & 0x08) puts (" Supports write1/read burst\n");
1169 if (data[22] & 0x04) puts (" Supports precharge all\n");
1170 if (data[22] & 0x02) puts (" Supports auto precharge\n");
1171 if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
1172 break;
1173 }
1174
1175 switch (type) {
1176 case DDR2:
632de067
LJ
1177 printf ("SDRAM cycle time (2nd highest CAS latency) ");
1178 print_ddr2_tcyc (data[23]);
0df6b844
LJ
1179 break;
1180 default:
632de067
LJ
1181 printf ("SDRAM cycle time (2nd highest CAS latency) %d."
1182 "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
0df6b844
LJ
1183 break;
1184 }
1185
1186 switch (type) {
1187 case DDR2:
632de067
LJ
1188 printf ("SDRAM access from clock (2nd highest CAS latency) 0."
1189 "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
0df6b844
LJ
1190 break;
1191 default:
632de067
LJ
1192 printf ("SDRAM access from clock (2nd highest CAS latency) %d."
1193 "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
0df6b844
LJ
1194 break;
1195 }
1196
1197 switch (type) {
1198 case DDR2:
632de067
LJ
1199 printf ("SDRAM cycle time (3rd highest CAS latency) ");
1200 print_ddr2_tcyc (data[25]);
0df6b844
LJ
1201 break;
1202 default:
632de067
LJ
1203 printf ("SDRAM cycle time (3rd highest CAS latency) %d."
1204 "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
0df6b844
LJ
1205 break;
1206 }
1207
1208 switch (type) {
1209 case DDR2:
632de067
LJ
1210 printf ("SDRAM access from clock (3rd highest CAS latency) 0."
1211 "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
0df6b844
LJ
1212 break;
1213 default:
632de067
LJ
1214 printf ("SDRAM access from clock (3rd highest CAS latency) %d."
1215 "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
0df6b844
LJ
1216 break;
1217 }
1218
1219 switch (type) {
1220 case DDR2:
632de067
LJ
1221 printf ("Minimum row precharge %d.%02d ns\n",
1222 (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
0df6b844
LJ
1223 break;
1224 default:
632de067 1225 printf ("Minimum row precharge %d ns\n", data[27]);
0df6b844
LJ
1226 break;
1227 }
1228
1229 switch (type) {
1230 case DDR2:
632de067
LJ
1231 printf ("Row active to row active min %d.%02d ns\n",
1232 (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
0df6b844
LJ
1233 break;
1234 default:
632de067 1235 printf ("Row active to row active min %d ns\n", data[28]);
0df6b844
LJ
1236 break;
1237 }
1238
1239 switch (type) {
1240 case DDR2:
632de067
LJ
1241 printf ("RAS to CAS delay min %d.%02d ns\n",
1242 (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
0df6b844
LJ
1243 break;
1244 default:
632de067 1245 printf ("RAS to CAS delay min %d ns\n", data[29]);
0df6b844
LJ
1246 break;
1247 }
1248
632de067 1249 printf ("Minimum RAS pulse width %d ns\n", data[30]);
0df6b844
LJ
1250
1251 switch (type) {
1252 case DDR2:
632de067
LJ
1253 puts ("Density of each row ");
1254 decode_bits (data[31], decode_row_density_DDR2, 1);
1255 putc ('\n');
0df6b844
LJ
1256 break;
1257 default:
632de067
LJ
1258 puts ("Density of each row ");
1259 decode_bits (data[31], decode_row_density_default, 1);
1260 putc ('\n');
0df6b844
LJ
1261 break;
1262 }
1263
1264 switch (type) {
1265 case DDR2:
632de067 1266 puts ("Command and Address setup ");
0df6b844 1267 if (data[32] >= 0xA0) {
632de067
LJ
1268 printf ("1.%d%d ns\n",
1269 ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
0df6b844 1270 } else {
632de067
LJ
1271 printf ("0.%d%d ns\n",
1272 ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
0df6b844
LJ
1273 }
1274 break;
1275 default:
632de067
LJ
1276 printf ("Command and Address setup %c%d.%d ns\n",
1277 (data[32] & 0x80) ? '-' : '+',
1278 (data[32] >> 4) & 0x07, data[32] & 0x0F);
0df6b844
LJ
1279 break;
1280 }
1281
1282 switch (type) {
1283 case DDR2:
632de067 1284 puts ("Command and Address hold ");
0df6b844 1285 if (data[33] >= 0xA0) {
632de067
LJ
1286 printf ("1.%d%d ns\n",
1287 ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
0df6b844 1288 } else {
632de067
LJ
1289 printf ("0.%d%d ns\n",
1290 ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
0df6b844
LJ
1291 }
1292 break;
1293 default:
632de067
LJ
1294 printf ("Command and Address hold %c%d.%d ns\n",
1295 (data[33] & 0x80) ? '-' : '+',
1296 (data[33] >> 4) & 0x07, data[33] & 0x0F);
0df6b844
LJ
1297 break;
1298 }
1299
1300 switch (type) {
1301 case DDR2:
632de067
LJ
1302 printf ("Data signal input setup 0.%d%d ns\n",
1303 (data[34] >> 4) & 0x0F, data[34] & 0x0F);
0df6b844
LJ
1304 break;
1305 default:
632de067
LJ
1306 printf ("Data signal input setup %c%d.%d ns\n",
1307 (data[34] & 0x80) ? '-' : '+',
1308 (data[34] >> 4) & 0x07, data[34] & 0x0F);
0df6b844
LJ
1309 break;
1310 }
1311
1312 switch (type) {
1313 case DDR2:
632de067
LJ
1314 printf ("Data signal input hold 0.%d%d ns\n",
1315 (data[35] >> 4) & 0x0F, data[35] & 0x0F);
0df6b844
LJ
1316 break;
1317 default:
632de067
LJ
1318 printf ("Data signal input hold %c%d.%d ns\n",
1319 (data[35] & 0x80) ? '-' : '+',
1320 (data[35] >> 4) & 0x07, data[35] & 0x0F);
0df6b844
LJ
1321 break;
1322 }
1323
4b9206ed 1324 puts ("Manufacturer's JEDEC ID ");
e857a5bd 1325 for (j = 64; j <= 71; j++)
632de067 1326 printf ("%02X ", data[j]);
4b9206ed 1327 putc ('\n');
632de067 1328 printf ("Manufacturing Location %02X\n", data[72]);
4b9206ed 1329 puts ("Manufacturer's Part Number ");
e857a5bd 1330 for (j = 73; j <= 90; j++)
632de067 1331 printf ("%02X ", data[j]);
4b9206ed 1332 putc ('\n');
632de067
LJ
1333 printf ("Revision Code %02X %02X\n", data[91], data[92]);
1334 printf ("Manufacturing Date %02X %02X\n", data[93], data[94]);
4b9206ed 1335 puts ("Assembly Serial Number ");
e857a5bd 1336 for (j = 95; j <= 98; j++)
632de067 1337 printf ("%02X ", data[j]);
4b9206ed 1338 putc ('\n');
81a8824f 1339
0df6b844 1340 if (DDR2 != type) {
632de067
LJ
1341 printf ("Speed rating PC%d\n",
1342 data[126] == 0x66 ? 66 : data[126]);
0df6b844 1343 }
81a8824f
WD
1344 return 0;
1345}
90253178 1346#endif
81a8824f 1347
735987c5
TWHT
1348/*
1349 * Syntax:
1350 * i2c edid {i2c_chip}
1351 */
1352#if defined(CONFIG_I2C_EDID)
1353int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1354{
1355 u_char chip;
1356 struct edid1_info edid;
1357
1358 if (argc < 2) {
1359 cmd_usage(cmdtp);
1360 return 1;
1361 }
1362
1363 chip = simple_strtoul(argv[1], NULL, 16);
1364 if (i2c_read(chip, 0, 1, (uchar *)&edid, sizeof(edid)) != 0) {
1365 puts("Error reading EDID content.\n");
1366 return 1;
1367 }
1368
1369 if (edid_check_info(&edid)) {
1370 puts("Content isn't valid EDID.\n");
1371 return 1;
1372 }
1373
1374 edid_print_info(&edid);
1375 return 0;
1376
1377}
1378#endif /* CONFIG_I2C_EDID */
1379
06afa388 1380/**
3f4978c7 1381 * do_i2c_show_bus() - Handle the "i2c bus" command-line command
06afa388
MV
1382 * @cmdtp: Command data struct pointer
1383 * @flag: Command flag
1384 * @argc: Command-line argument count
1385 * @argv: Array of command-line arguments
1386 *
1387 * Returns zero always.
1388 */
3f4978c7
HS
1389#if defined(CONFIG_SYS_I2C)
1390int do_i2c_show_bus(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
67b23a32 1391{
3f4978c7
HS
1392 int i;
1393#ifndef CONFIG_SYS_I2C_DIRECT_BUS
1394 int j;
1395#endif
67b23a32
HS
1396
1397 if (argc == 1) {
1398 /* show all busses */
3f4978c7
HS
1399 for (i = 0; i < CONFIG_SYS_NUM_I2C_BUSES; i++) {
1400 printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
1401#ifndef CONFIG_SYS_I2C_DIRECT_BUS
1402 for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
1403 if (i2c_bus[i].next_hop[j].chip == 0)
1404 break;
1405 printf("->%s@0x%2x:%d",
1406 i2c_bus[i].next_hop[j].mux.name,
1407 i2c_bus[i].next_hop[j].chip,
1408 i2c_bus[i].next_hop[j].channel);
67b23a32 1409 }
3f4978c7
HS
1410#endif
1411 printf("\n");
67b23a32
HS
1412 }
1413 } else {
3f4978c7
HS
1414 /* show specific bus */
1415 i = simple_strtoul(argv[1], NULL, 10);
1416 if (i >= CONFIG_SYS_NUM_I2C_BUSES) {
1417 printf("Invalid bus %d\n", i);
1418 return -1;
1419 }
1420 printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name);
1421#ifndef CONFIG_SYS_I2C_DIRECT_BUS
1422 for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) {
1423 if (i2c_bus[i].next_hop[j].chip == 0)
1424 break;
1425 printf("->%s@0x%2x:%d",
1426 i2c_bus[i].next_hop[j].mux.name,
1427 i2c_bus[i].next_hop[j].chip,
1428 i2c_bus[i].next_hop[j].channel);
1429 }
1430#endif
1431 printf("\n");
67b23a32 1432 }
3f4978c7
HS
1433
1434 return 0;
67b23a32 1435}
3f4978c7 1436#endif
67b23a32 1437
06afa388
MV
1438/**
1439 * do_i2c_bus_num() - Handle the "i2c dev" command-line command
1440 * @cmdtp: Command data struct pointer
1441 * @flag: Command flag
1442 * @argc: Command-line argument count
1443 * @argv: Array of command-line arguments
1444 *
1445 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1446 * on error.
1447 */
3f4978c7
HS
1448#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
1449int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
bb99ad6d 1450{
3f4978c7
HS
1451 int ret = 0;
1452 unsigned int bus_no;
bb99ad6d 1453
e857a5bd
TT
1454 if (argc == 1)
1455 /* querying current setting */
bb99ad6d 1456 printf("Current bus is %d\n", i2c_get_bus_num());
e857a5bd 1457 else {
3f4978c7
HS
1458 bus_no = simple_strtoul(argv[1], NULL, 10);
1459 if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) {
1460 printf("Invalid bus %d\n", bus_no);
1461 return -1;
1462 }
1463 printf("Setting bus to %d\n", bus_no);
1464 ret = i2c_set_bus_num(bus_no);
e857a5bd 1465 if (ret)
bb99ad6d 1466 printf("Failure changing bus number (%d)\n", ret);
bb99ad6d
BW
1467 }
1468 return ret;
1469}
3f4978c7 1470#endif /* defined(CONFIG_SYS_I2C) */
bb99ad6d 1471
06afa388
MV
1472/**
1473 * do_i2c_bus_speed() - Handle the "i2c speed" command-line command
1474 * @cmdtp: Command data struct pointer
1475 * @flag: Command flag
1476 * @argc: Command-line argument count
1477 * @argv: Array of command-line arguments
1478 *
1479 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1480 * on error.
1481 */
54841ab5 1482static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bb99ad6d
BW
1483{
1484 int speed, ret=0;
1485
e857a5bd
TT
1486 if (argc == 1)
1487 /* querying current speed */
bb99ad6d 1488 printf("Current bus speed=%d\n", i2c_get_bus_speed());
e857a5bd 1489 else {
bb99ad6d
BW
1490 speed = simple_strtoul(argv[1], NULL, 10);
1491 printf("Setting bus speed to %d Hz\n", speed);
1492 ret = i2c_set_bus_speed(speed);
e857a5bd 1493 if (ret)
bb99ad6d 1494 printf("Failure changing bus speed (%d)\n", ret);
bb99ad6d
BW
1495 }
1496 return ret;
1497}
1498
06afa388
MV
1499/**
1500 * do_i2c_mm() - Handle the "i2c mm" command-line command
1501 * @cmdtp: Command data struct pointer
1502 * @flag: Command flag
1503 * @argc: Command-line argument count
1504 * @argv: Array of command-line arguments
1505 *
1506 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1507 * on error.
1508 */
54841ab5 1509static int do_i2c_mm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bb99ad6d 1510{
bfc3b77e
FM
1511 return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
1512}
1513
06afa388
MV
1514/**
1515 * do_i2c_nm() - Handle the "i2c nm" command-line command
1516 * @cmdtp: Command data struct pointer
1517 * @flag: Command flag
1518 * @argc: Command-line argument count
1519 * @argv: Array of command-line arguments
1520 *
1521 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1522 * on error.
1523 */
54841ab5 1524static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bfc3b77e
FM
1525{
1526 return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
1527}
e96ad5d3 1528
06afa388
MV
1529/**
1530 * do_i2c_reset() - Handle the "i2c reset" command-line command
1531 * @cmdtp: Command data struct pointer
1532 * @flag: Command flag
1533 * @argc: Command-line argument count
1534 * @argv: Array of command-line arguments
1535 *
1536 * Returns zero always.
1537 */
54841ab5 1538static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bfc3b77e 1539{
3f4978c7
HS
1540#if defined(CONFIG_SYS_I2C)
1541 i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr);
1542#else
bfc3b77e 1543 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
3f4978c7 1544#endif
bfc3b77e
FM
1545 return 0;
1546}
1547
1548static cmd_tbl_t cmd_i2c_sub[] = {
3f4978c7
HS
1549#if defined(CONFIG_SYS_I2C)
1550 U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""),
9a2accb4 1551#endif
bfc3b77e 1552 U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
3f4978c7
HS
1553#if defined(CONFIG_SYS_I2C) || \
1554 defined(CONFIG_I2C_MULTI_BUS)
bfc3b77e 1555 U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
bb99ad6d 1556#endif /* CONFIG_I2C_MULTI_BUS */
735987c5
TWHT
1557#if defined(CONFIG_I2C_EDID)
1558 U_BOOT_CMD_MKENT(edid, 1, 1, do_edid, "", ""),
1559#endif /* CONFIG_I2C_EDID */
bfc3b77e
FM
1560 U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""),
1561 U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""),
1562 U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""),
1563 U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""),
1564 U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
1565 U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
652e5354 1566 U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
ff5d2dce 1567 U_BOOT_CMD_MKENT(write, 5, 0, do_i2c_write, "", ""),
bfc3b77e 1568 U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
c76fe474 1569#if defined(CONFIG_CMD_SDRAM)
bfc3b77e 1570 U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
90253178 1571#endif
bfc3b77e
FM
1572 U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
1573};
1574
2e5167cc 1575#ifdef CONFIG_NEEDS_MANUAL_RELOC
f1d2b313
HS
1576void i2c_reloc(void) {
1577 fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
1578}
1579#endif
1580
06afa388
MV
1581/**
1582 * do_i2c() - Handle the "i2c" command-line command
1583 * @cmdtp: Command data struct pointer
1584 * @flag: Command flag
1585 * @argc: Command-line argument count
1586 * @argv: Array of command-line arguments
1587 *
1588 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
1589 * on error.
1590 */
54841ab5 1591static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bfc3b77e
FM
1592{
1593 cmd_tbl_t *c;
1594
4444b221 1595 if (argc < 2)
4c12eeb8 1596 return CMD_RET_USAGE;
4444b221 1597
bfc3b77e
FM
1598 /* Strip off leading 'i2c' command argument */
1599 argc--;
1600 argv++;
1601
1602 c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub));
1603
47e26b1b 1604 if (c)
4c12eeb8 1605 return c->cmd(cmdtp, flag, argc, argv);
47e26b1b 1606 else
4c12eeb8 1607 return CMD_RET_USAGE;
bb99ad6d 1608}
8bde7f77
WD
1609
1610/***************************************************/
088f1b19
KP
1611#ifdef CONFIG_SYS_LONGHELP
1612static char i2c_help_text[] =
3f4978c7
HS
1613#if defined(CONFIG_SYS_I2C)
1614 "bus [muxtype:muxaddr:muxchannel] - show I2C bus info\n"
9a2accb4 1615#endif
fb0070e9 1616 "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
3f4978c7
HS
1617#if defined(CONFIG_SYS_I2C) || \
1618 defined(CONFIG_I2C_MULTI_BUS)
9bc2e4ee 1619 "i2c dev [dev] - show or set current I2C bus\n"
d9fc7032 1620#endif /* CONFIG_I2C_MULTI_BUS */
735987c5
TWHT
1621#if defined(CONFIG_I2C_EDID)
1622 "i2c edid chip - print EDID configuration information\n"
1623#endif /* CONFIG_I2C_EDID */
fb0070e9 1624 "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
d9fc7032
MF
1625 "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
1626 "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
1627 "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
1628 "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
54b99e51 1629 "i2c probe [address] - test for and show device(s) on the I2C bus\n"
652e5354 1630 "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n"
ff5d2dce 1631 "i2c write memaddress chip address[.0, .1, .2] length - write memory to i2c\n"
e43a27c4 1632 "i2c reset - re-init the I2C Controller\n"
c76fe474 1633#if defined(CONFIG_CMD_SDRAM)
fb0070e9 1634 "i2c sdram chip - print SDRAM configuration information\n"
90253178 1635#endif
088f1b19
KP
1636 "i2c speed [speed] - show or set I2C bus speed";
1637#endif
1638
1639U_BOOT_CMD(
1640 i2c, 6, 1, do_i2c,
1641 "I2C sub-system",
1642 i2c_help_text
d9fc7032 1643);