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i2c: Staticize local functions in mxc i2c driver
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81a8824f
WD
1/*
2 * (C) Copyright 2001
3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * I2C Functions similar to the standard memory functions.
26 *
27 * There are several parameters in many of the commands that bear further
28 * explanations:
29 *
81a8824f
WD
30 * {i2c_chip} is the I2C chip address (the first byte sent on the bus).
31 * Each I2C chip on the bus has a unique address. On the I2C data bus,
32 * the address is the upper seven bits and the LSB is the "read/write"
33 * bit. Note that the {i2c_chip} address specified on the command
34 * line is not shifted up: e.g. a typical EEPROM memory chip may have
35 * an I2C address of 0x50, but the data put on the bus will be 0xA0
36 * for write and 0xA1 for read. This "non shifted" address notation
37 * matches at least half of the data sheets :-/.
38 *
39 * {addr} is the address (or offset) within the chip. Small memory
40 * chips have 8 bit addresses. Large memory chips have 16 bit
41 * addresses. Other memory chips have 9, 10, or 11 bit addresses.
42 * Many non-memory chips have multiple registers and {addr} is used
43 * as the register index. Some non-memory chips have only one register
44 * and therefore don't need any {addr} parameter.
45 *
46 * The default {addr} parameter is one byte (.1) which works well for
47 * memories and registers with 8 bits of address space.
48 *
49 * You can specify the length of the {addr} field with the optional .0,
50 * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are
51 * manipulating a single register device which doesn't use an address
52 * field, use "0.0" for the address and the ".0" length field will
53 * suppress the address in the I2C data stream. This also works for
54 * successive reads using the I2C auto-incrementing memory pointer.
55 *
56 * If you are manipulating a large memory with 2-byte addresses, use
57 * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal).
58 *
59 * Then there are the unfortunate memory chips that spill the most
60 * significant 1, 2, or 3 bits of address into the chip address byte.
61 * This effectively makes one chip (logically) look like 2, 4, or
62 * 8 chips. This is handled (awkwardly) by #defining
6d0f6bcf 63 * CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
81a8824f
WD
64 * {addr} field (since .1 is the default, it doesn't actually have to
65 * be specified). Examples: given a memory chip at I2C chip address
66 * 0x50, the following would happen...
0f89c54b 67 * i2c md 50 0 10 display 16 bytes starting at 0x000
81a8824f 68 * On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd>
0f89c54b 69 * i2c md 50 100 10 display 16 bytes starting at 0x100
81a8824f 70 * On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd>
0f89c54b 71 * i2c md 50 210 10 display 16 bytes starting at 0x210
81a8824f
WD
72 * On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd>
73 * This is awfully ugly. It would be nice if someone would think up
74 * a better way of handling this.
75 *
76 * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de).
77 */
78
79#include <common.h>
80#include <command.h>
67b23a32 81#include <environment.h>
81a8824f 82#include <i2c.h>
67b23a32 83#include <malloc.h>
81a8824f 84#include <asm/byteorder.h>
2515d843 85#include <linux/compiler.h>
81a8824f 86
81a8824f
WD
87/* Display values from last command.
88 * Memory modify remembered values are different from display memory.
89 */
90static uchar i2c_dp_last_chip;
91static uint i2c_dp_last_addr;
92static uint i2c_dp_last_alen;
93static uint i2c_dp_last_length = 0x10;
94
95static uchar i2c_mm_last_chip;
96static uint i2c_mm_last_addr;
97static uint i2c_mm_last_alen;
98
bb99ad6d
BW
99/* If only one I2C bus is present, the list of devices to ignore when
100 * the probe command is issued is represented by a 1D array of addresses.
101 * When multiple buses are present, the list is an array of bus-address
102 * pairs. The following macros take care of this */
103
6d0f6bcf 104#if defined(CONFIG_SYS_I2C_NOPROBES)
bb99ad6d
BW
105#if defined(CONFIG_I2C_MULTI_BUS)
106static struct
107{
108 uchar bus;
109 uchar addr;
6d0f6bcf 110} i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
bb99ad6d
BW
111#define GET_BUS_NUM i2c_get_bus_num()
112#define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
113#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
114#define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
115#else /* single bus */
6d0f6bcf 116static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
bb99ad6d
BW
117#define GET_BUS_NUM 0
118#define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
119#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
120#define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
121#endif /* CONFIG_MULTI_BUS */
122
123#define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0]))
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WD
124#endif
125
67b23a32
HS
126#if defined(CONFIG_I2C_MUX)
127static I2C_MUX_DEVICE *i2c_mux_devices = NULL;
6d0f6bcf 128static int i2c_mux_busid = CONFIG_SYS_MAX_I2C_BUS;
67b23a32
HS
129
130DECLARE_GLOBAL_DATA_PTR;
131
132#endif
133
a266fe95
FM
134#define DISP_LINE_LEN 16
135
c649dda5 136/* implement possible board specific board init */
2515d843
MV
137__weak
138void i2c_init_board(void)
c649dda5
SB
139{
140 return;
141}
c649dda5 142
655b34a7 143/* TODO: Implement architecture-specific get/set functions */
2515d843
MV
144__weak
145unsigned int i2c_get_bus_speed(void)
655b34a7
PT
146{
147 return CONFIG_SYS_I2C_SPEED;
148}
655b34a7 149
2515d843
MV
150__weak
151int i2c_set_bus_speed(unsigned int speed)
655b34a7
PT
152{
153 if (speed != CONFIG_SYS_I2C_SPEED)
154 return -1;
155
156 return 0;
157}
655b34a7 158
2c0dc990
FM
159/*
160 * get_alen: small parser helper function to get address length
7a92e53c 161 * returns the address length
2c0dc990
FM
162 */
163static uint get_alen(char *arg)
164{
165 int j;
166 int alen;
167
168 alen = 1;
169 for (j = 0; j < 8; j++) {
170 if (arg[j] == '.') {
171 alen = arg[j+1] - '0';
2c0dc990
FM
172 break;
173 } else if (arg[j] == '\0')
174 break;
175 }
176 return alen;
177}
178
652e5354
FM
179/*
180 * Syntax:
181 * i2c read {i2c_chip} {devaddr}{.0, .1, .2} {len} {memaddr}
182 */
183
54841ab5 184static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
652e5354
FM
185{
186 u_char chip;
187 uint devaddr, alen, length;
188 u_char *memaddr;
652e5354 189
47e26b1b 190 if (argc != 5)
4c12eeb8 191 return CMD_RET_USAGE;
652e5354
FM
192
193 /*
194 * I2C chip address
195 */
196 chip = simple_strtoul(argv[1], NULL, 16);
197
198 /*
199 * I2C data address within the chip. This can be 1 or
200 * 2 bytes long. Some day it might be 3 bytes long :-).
201 */
202 devaddr = simple_strtoul(argv[2], NULL, 16);
2c0dc990 203 alen = get_alen(argv[2]);
7a92e53c 204 if (alen > 3)
4c12eeb8 205 return CMD_RET_USAGE;
652e5354
FM
206
207 /*
208 * Length is the number of objects, not number of bytes.
209 */
210 length = simple_strtoul(argv[3], NULL, 16);
211
212 /*
213 * memaddr is the address where to store things in memory
214 */
215 memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
216
217 if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) {
218 puts ("Error reading the chip.\n");
219 return 1;
220 }
221 return 0;
222}
223
ff5d2dce
YS
224static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
225{
226 u_char chip;
227 uint devaddr, alen, length;
228 u_char *memaddr;
229
230 if (argc != 5)
231 return cmd_usage(cmdtp);
232
233 /*
234 * memaddr is the address where to store things in memory
235 */
236 memaddr = (u_char *)simple_strtoul(argv[1], NULL, 16);
237
238 /*
239 * I2C chip address
240 */
241 chip = simple_strtoul(argv[2], NULL, 16);
242
243 /*
244 * I2C data address within the chip. This can be 1 or
245 * 2 bytes long. Some day it might be 3 bytes long :-).
246 */
247 devaddr = simple_strtoul(argv[3], NULL, 16);
248 alen = get_alen(argv[3]);
249 if (alen > 3)
250 return cmd_usage(cmdtp);
251
252 /*
253 * Length is the number of objects, not number of bytes.
254 */
255 length = simple_strtoul(argv[4], NULL, 16);
256
257 while (length-- > 0) {
258 if (i2c_write(chip, devaddr++, alen, memaddr++, 1) != 0) {
259 puts("Error writing to the chip.\n");
260 return 1;
261 }
262/*
263 * No write delay with FRAM devices.
264 */
265#if !defined(CONFIG_SYS_I2C_FRAM)
266 udelay(11000);
267#endif
268 }
269 return 0;
270}
271
4a8cf338
FM
272/*
273 * Syntax:
274 * i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
275 */
54841ab5 276static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f
WD
277{
278 u_char chip;
279 uint addr, alen, length;
280 int j, nbytes, linebytes;
281
282 /* We use the last specified parameters, unless new ones are
283 * entered.
284 */
285 chip = i2c_dp_last_chip;
286 addr = i2c_dp_last_addr;
287 alen = i2c_dp_last_alen;
288 length = i2c_dp_last_length;
289
47e26b1b 290 if (argc < 3)
4c12eeb8 291 return CMD_RET_USAGE;
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292
293 if ((flag & CMD_FLAG_REPEAT) == 0) {
294 /*
295 * New command specified.
296 */
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WD
297
298 /*
299 * I2C chip address
300 */
301 chip = simple_strtoul(argv[1], NULL, 16);
302
303 /*
304 * I2C data address within the chip. This can be 1 or
305 * 2 bytes long. Some day it might be 3 bytes long :-).
306 */
307 addr = simple_strtoul(argv[2], NULL, 16);
2c0dc990 308 alen = get_alen(argv[2]);
7a92e53c 309 if (alen > 3)
4c12eeb8 310 return CMD_RET_USAGE;
81a8824f
WD
311
312 /*
313 * If another parameter, it is the length to display.
314 * Length is the number of objects, not number of bytes.
315 */
316 if (argc > 3)
317 length = simple_strtoul(argv[3], NULL, 16);
318 }
319
320 /*
321 * Print the lines.
322 *
323 * We buffer all read data, so we can make sure data is read only
324 * once.
325 */
326 nbytes = length;
327 do {
328 unsigned char linebuf[DISP_LINE_LEN];
329 unsigned char *cp;
330
331 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
332
e857a5bd 333 if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0)
4b9206ed 334 puts ("Error reading the chip.\n");
e857a5bd 335 else {
81a8824f
WD
336 printf("%04x:", addr);
337 cp = linebuf;
338 for (j=0; j<linebytes; j++) {
339 printf(" %02x", *cp++);
340 addr++;
341 }
4b9206ed 342 puts (" ");
81a8824f
WD
343 cp = linebuf;
344 for (j=0; j<linebytes; j++) {
345 if ((*cp < 0x20) || (*cp > 0x7e))
4b9206ed 346 puts (".");
81a8824f
WD
347 else
348 printf("%c", *cp);
349 cp++;
350 }
4b9206ed 351 putc ('\n');
81a8824f
WD
352 }
353 nbytes -= linebytes;
354 } while (nbytes > 0);
355
356 i2c_dp_last_chip = chip;
357 i2c_dp_last_addr = addr;
358 i2c_dp_last_alen = alen;
359 i2c_dp_last_length = length;
360
361 return 0;
362}
363
81a8824f
WD
364
365/* Write (fill) memory
366 *
367 * Syntax:
0f89c54b 368 * i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
81a8824f 369 */
54841ab5 370static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f
WD
371{
372 uchar chip;
373 ulong addr;
374 uint alen;
375 uchar byte;
376 int count;
81a8824f 377
47e26b1b 378 if ((argc < 4) || (argc > 5))
4c12eeb8 379 return CMD_RET_USAGE;
81a8824f
WD
380
381 /*
53677ef1
WD
382 * Chip is always specified.
383 */
81a8824f
WD
384 chip = simple_strtoul(argv[1], NULL, 16);
385
386 /*
387 * Address is always specified.
388 */
389 addr = simple_strtoul(argv[2], NULL, 16);
2c0dc990 390 alen = get_alen(argv[2]);
7a92e53c 391 if (alen > 3)
4c12eeb8 392 return CMD_RET_USAGE;
81a8824f
WD
393
394 /*
395 * Value to write is always specified.
396 */
397 byte = simple_strtoul(argv[3], NULL, 16);
398
399 /*
400 * Optional count
401 */
e857a5bd 402 if (argc == 5)
81a8824f 403 count = simple_strtoul(argv[4], NULL, 16);
e857a5bd 404 else
81a8824f 405 count = 1;
81a8824f
WD
406
407 while (count-- > 0) {
e857a5bd 408 if (i2c_write(chip, addr++, alen, &byte, 1) != 0)
4b9206ed 409 puts ("Error writing the chip.\n");
81a8824f
WD
410 /*
411 * Wait for the write to complete. The write can take
412 * up to 10mSec (we allow a little more time).
81a8824f 413 */
d4f5c728 414/*
415 * No write delay with FRAM devices.
416 */
6d0f6bcf 417#if !defined(CONFIG_SYS_I2C_FRAM)
81a8824f 418 udelay(11000);
d4f5c728 419#endif
81a8824f
WD
420 }
421
422 return (0);
423}
424
81a8824f
WD
425/* Calculate a CRC on memory
426 *
427 * Syntax:
0f89c54b 428 * i2c crc32 {i2c_chip} {addr}{.0, .1, .2} {count}
81a8824f 429 */
54841ab5 430static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f
WD
431{
432 uchar chip;
433 ulong addr;
434 uint alen;
435 int count;
436 uchar byte;
437 ulong crc;
438 ulong err;
81a8824f 439
47e26b1b 440 if (argc < 4)
4c12eeb8 441 return CMD_RET_USAGE;
81a8824f
WD
442
443 /*
53677ef1
WD
444 * Chip is always specified.
445 */
81a8824f
WD
446 chip = simple_strtoul(argv[1], NULL, 16);
447
448 /*
449 * Address is always specified.
450 */
451 addr = simple_strtoul(argv[2], NULL, 16);
2c0dc990 452 alen = get_alen(argv[2]);
7a92e53c 453 if (alen > 3)
4c12eeb8 454 return CMD_RET_USAGE;
81a8824f
WD
455
456 /*
457 * Count is always specified
458 */
459 count = simple_strtoul(argv[3], NULL, 16);
460
461 printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1);
462 /*
463 * CRC a byte at a time. This is going to be slooow, but hey, the
464 * memories are small and slow too so hopefully nobody notices.
465 */
466 crc = 0;
467 err = 0;
e857a5bd
TT
468 while (count-- > 0) {
469 if (i2c_read(chip, addr, alen, &byte, 1) != 0)
81a8824f 470 err++;
81a8824f
WD
471 crc = crc32 (crc, &byte, 1);
472 addr++;
473 }
e857a5bd 474 if (err > 0)
4b9206ed 475 puts ("Error reading the chip,\n");
e857a5bd 476 else
81a8824f 477 printf ("%08lx\n", crc);
81a8824f
WD
478
479 return 0;
480}
481
81a8824f
WD
482/* Modify memory.
483 *
484 * Syntax:
0f89c54b
PT
485 * i2c mm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
486 * i2c nm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
81a8824f
WD
487 */
488
489static int
54841ab5 490mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
81a8824f
WD
491{
492 uchar chip;
493 ulong addr;
494 uint alen;
495 ulong data;
496 int size = 1;
497 int nbytes;
81a8824f 498
47e26b1b 499 if (argc != 3)
4c12eeb8 500 return CMD_RET_USAGE;
81a8824f
WD
501
502#ifdef CONFIG_BOOT_RETRY_TIME
503 reset_cmd_timeout(); /* got a good command to get here */
504#endif
505 /*
506 * We use the last specified parameters, unless new ones are
507 * entered.
508 */
509 chip = i2c_mm_last_chip;
510 addr = i2c_mm_last_addr;
511 alen = i2c_mm_last_alen;
512
513 if ((flag & CMD_FLAG_REPEAT) == 0) {
514 /*
515 * New command specified. Check for a size specification.
516 * Defaults to byte if no or incorrect specification.
517 */
518 size = cmd_get_data_size(argv[0], 1);
519
520 /*
53677ef1
WD
521 * Chip is always specified.
522 */
81a8824f
WD
523 chip = simple_strtoul(argv[1], NULL, 16);
524
525 /*
526 * Address is always specified.
527 */
528 addr = simple_strtoul(argv[2], NULL, 16);
2c0dc990 529 alen = get_alen(argv[2]);
7a92e53c 530 if (alen > 3)
4c12eeb8 531 return CMD_RET_USAGE;
81a8824f
WD
532 }
533
534 /*
535 * Print the address, followed by value. Then accept input for
536 * the next value. A non-converted value exits.
537 */
538 do {
539 printf("%08lx:", addr);
e857a5bd 540 if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0)
4b9206ed 541 puts ("\nError reading the chip,\n");
e857a5bd 542 else {
81a8824f 543 data = cpu_to_be32(data);
e857a5bd 544 if (size == 1)
81a8824f 545 printf(" %02lx", (data >> 24) & 0x000000FF);
e857a5bd 546 else if (size == 2)
81a8824f 547 printf(" %04lx", (data >> 16) & 0x0000FFFF);
e857a5bd 548 else
81a8824f 549 printf(" %08lx", data);
81a8824f
WD
550 }
551
552 nbytes = readline (" ? ");
553 if (nbytes == 0) {
554 /*
555 * <CR> pressed as only input, don't modify current
556 * location and move to next.
557 */
558 if (incrflag)
559 addr += size;
560 nbytes = size;
561#ifdef CONFIG_BOOT_RETRY_TIME
562 reset_cmd_timeout(); /* good enough to not time out */
563#endif
564 }
565#ifdef CONFIG_BOOT_RETRY_TIME
e857a5bd 566 else if (nbytes == -2)
81a8824f 567 break; /* timed out, exit the command */
81a8824f
WD
568#endif
569 else {
570 char *endp;
571
572 data = simple_strtoul(console_buffer, &endp, 16);
e857a5bd 573 if (size == 1)
81a8824f 574 data = data << 24;
e857a5bd 575 else if (size == 2)
81a8824f 576 data = data << 16;
81a8824f
WD
577 data = be32_to_cpu(data);
578 nbytes = endp - console_buffer;
579 if (nbytes) {
580#ifdef CONFIG_BOOT_RETRY_TIME
581 /*
582 * good enough to not time out
583 */
584 reset_cmd_timeout();
585#endif
e857a5bd 586 if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0)
4b9206ed 587 puts ("Error writing the chip.\n");
6d0f6bcf
JCPV
588#ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
589 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
2535d602 590#endif
81a8824f
WD
591 if (incrflag)
592 addr += size;
593 }
594 }
595 } while (nbytes);
596
0800707b
PT
597 i2c_mm_last_chip = chip;
598 i2c_mm_last_addr = addr;
599 i2c_mm_last_alen = alen;
81a8824f
WD
600
601 return 0;
602}
603
604/*
605 * Syntax:
54b99e51
EN
606 * i2c probe {addr}
607 *
608 * Returns zero (success) if one or more I2C devices was found
81a8824f 609 */
54841ab5 610static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f
WD
611{
612 int j;
54b99e51
EN
613 int addr = -1;
614 int found = 0;
6d0f6bcf 615#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 616 int k, skip;
bb99ad6d
BW
617 uchar bus = GET_BUS_NUM;
618#endif /* NOPROBES */
81a8824f 619
54b99e51
EN
620 if (argc == 2)
621 addr = simple_strtol(argv[1], 0, 16);
622
4b9206ed 623 puts ("Valid chip addresses:");
e857a5bd 624 for (j = 0; j < 128; j++) {
54b99e51
EN
625 if ((0 <= addr) && (j != addr))
626 continue;
627
6d0f6bcf 628#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 629 skip = 0;
e857a5bd
TT
630 for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
631 if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
81a8824f
WD
632 skip = 1;
633 break;
634 }
635 }
636 if (skip)
637 continue;
638#endif
54b99e51 639 if (i2c_probe(j) == 0) {
81a8824f 640 printf(" %02X", j);
54b99e51
EN
641 found++;
642 }
81a8824f 643 }
4b9206ed 644 putc ('\n');
81a8824f 645
6d0f6bcf 646#if defined(CONFIG_SYS_I2C_NOPROBES)
81a8824f 647 puts ("Excluded chip addresses:");
e857a5bd
TT
648 for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
649 if (COMPARE_BUS(bus,k))
bb99ad6d
BW
650 printf(" %02X", NO_PROBE_ADDR(k));
651 }
4b9206ed 652 putc ('\n');
81a8824f
WD
653#endif
654
54b99e51 655 return (0 == found);
81a8824f
WD
656}
657
81a8824f
WD
658/*
659 * Syntax:
0f89c54b 660 * i2c loop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
81a8824f
WD
661 * {length} - Number of bytes to read
662 * {delay} - A DECIMAL number and defaults to 1000 uSec
663 */
54841ab5 664static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81a8824f
WD
665{
666 u_char chip;
667 ulong alen;
668 uint addr;
669 uint length;
670 u_char bytes[16];
671 int delay;
81a8824f 672
47e26b1b 673 if (argc < 3)
4c12eeb8 674 return CMD_RET_USAGE;
81a8824f
WD
675
676 /*
677 * Chip is always specified.
678 */
679 chip = simple_strtoul(argv[1], NULL, 16);
680
681 /*
682 * Address is always specified.
683 */
684 addr = simple_strtoul(argv[2], NULL, 16);
2c0dc990 685 alen = get_alen(argv[2]);
7a92e53c 686 if (alen > 3)
4c12eeb8 687 return CMD_RET_USAGE;
81a8824f
WD
688
689 /*
690 * Length is the number of objects, not number of bytes.
691 */
692 length = 1;
693 length = simple_strtoul(argv[3], NULL, 16);
e857a5bd 694 if (length > sizeof(bytes))
81a8824f 695 length = sizeof(bytes);
81a8824f
WD
696
697 /*
698 * The delay time (uSec) is optional.
699 */
700 delay = 1000;
e857a5bd 701 if (argc > 3)
81a8824f 702 delay = simple_strtoul(argv[4], NULL, 10);
81a8824f
WD
703 /*
704 * Run the loop...
705 */
e857a5bd
TT
706 while (1) {
707 if (i2c_read(chip, addr, alen, bytes, length) != 0)
4b9206ed 708 puts ("Error reading the chip.\n");
81a8824f
WD
709 udelay(delay);
710 }
711
712 /* NOTREACHED */
713 return 0;
714}
715
81a8824f
WD
716/*
717 * The SDRAM command is separately configured because many
718 * (most?) embedded boards don't use SDRAM DIMMs.
719 */
c76fe474 720#if defined(CONFIG_CMD_SDRAM)
632de067
LJ
721static void print_ddr2_tcyc (u_char const b)
722{
723 printf ("%d.", (b >> 4) & 0x0F);
724 switch (b & 0x0F) {
725 case 0x0:
726 case 0x1:
727 case 0x2:
728 case 0x3:
729 case 0x4:
730 case 0x5:
731 case 0x6:
732 case 0x7:
733 case 0x8:
734 case 0x9:
735 printf ("%d ns\n", b & 0x0F);
736 break;
737 case 0xA:
738 puts ("25 ns\n");
739 break;
740 case 0xB:
741 puts ("33 ns\n");
742 break;
743 case 0xC:
744 puts ("66 ns\n");
745 break;
746 case 0xD:
747 puts ("75 ns\n");
748 break;
749 default:
750 puts ("?? ns\n");
751 break;
752 }
753}
754
755static void decode_bits (u_char const b, char const *str[], int const do_once)
756{
757 u_char mask;
758
759 for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
760 if (b & mask) {
761 puts (*str);
762 if (do_once)
763 return;
764 }
765 }
766}
81a8824f
WD
767
768/*
769 * Syntax:
0f89c54b 770 * i2c sdram {i2c_chip}
81a8824f 771 */
54841ab5 772static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
81a8824f 773{
632de067
LJ
774 enum { unknown, EDO, SDRAM, DDR2 } type;
775
81a8824f
WD
776 u_char chip;
777 u_char data[128];
778 u_char cksum;
779 int j;
780
632de067
LJ
781 static const char *decode_CAS_DDR2[] = {
782 " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
783 };
784
785 static const char *decode_CAS_default[] = {
786 " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
787 };
788
789 static const char *decode_CS_WE_default[] = {
790 " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
791 };
792
793 static const char *decode_byte21_default[] = {
794 " TBD (bit 7)\n",
795 " Redundant row address\n",
796 " Differential clock input\n",
797 " Registerd DQMB inputs\n",
798 " Buffered DQMB inputs\n",
799 " On-card PLL\n",
800 " Registered address/control lines\n",
801 " Buffered address/control lines\n"
802 };
803
804 static const char *decode_byte22_DDR2[] = {
805 " TBD (bit 7)\n",
806 " TBD (bit 6)\n",
807 " TBD (bit 5)\n",
808 " TBD (bit 4)\n",
809 " TBD (bit 3)\n",
810 " Supports partial array self refresh\n",
811 " Supports 50 ohm ODT\n",
812 " Supports weak driver\n"
813 };
814
815 static const char *decode_row_density_DDR2[] = {
816 "512 MiB", "256 MiB", "128 MiB", "16 GiB",
817 "8 GiB", "4 GiB", "2 GiB", "1 GiB"
818 };
819
820 static const char *decode_row_density_default[] = {
821 "512 MiB", "256 MiB", "128 MiB", "64 MiB",
822 "32 MiB", "16 MiB", "8 MiB", "4 MiB"
823 };
824
47e26b1b 825 if (argc < 2)
4c12eeb8 826 return CMD_RET_USAGE;
47e26b1b 827
81a8824f
WD
828 /*
829 * Chip is always specified.
632de067
LJ
830 */
831 chip = simple_strtoul (argv[1], NULL, 16);
81a8824f 832
632de067 833 if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
4b9206ed 834 puts ("No SDRAM Serial Presence Detect found.\n");
81a8824f
WD
835 return 1;
836 }
837
838 cksum = 0;
839 for (j = 0; j < 63; j++) {
840 cksum += data[j];
841 }
e857a5bd 842 if (cksum != data[63]) {
81a8824f 843 printf ("WARNING: Configuration data checksum failure:\n"
632de067 844 " is 0x%02x, calculated 0x%02x\n", data[63], cksum);
81a8824f 845 }
632de067 846 printf ("SPD data revision %d.%d\n",
81a8824f 847 (data[62] >> 4) & 0x0F, data[62] & 0x0F);
632de067
LJ
848 printf ("Bytes used 0x%02X\n", data[0]);
849 printf ("Serial memory size 0x%02X\n", 1 << data[1]);
850
4b9206ed 851 puts ("Memory type ");
632de067 852 switch (data[2]) {
0df6b844
LJ
853 case 2:
854 type = EDO;
855 puts ("EDO\n");
856 break;
857 case 4:
858 type = SDRAM;
859 puts ("SDRAM\n");
860 break;
861 case 8:
862 type = DDR2;
863 puts ("DDR2\n");
864 break;
865 default:
866 type = unknown;
867 puts ("unknown\n");
868 break;
81a8824f 869 }
632de067 870
4b9206ed 871 puts ("Row address bits ");
e857a5bd 872 if ((data[3] & 0x00F0) == 0)
632de067 873 printf ("%d\n", data[3] & 0x0F);
e857a5bd 874 else
632de067
LJ
875 printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
876
4b9206ed 877 puts ("Column address bits ");
e857a5bd 878 if ((data[4] & 0x00F0) == 0)
632de067 879 printf ("%d\n", data[4] & 0x0F);
e857a5bd 880 else
632de067 881 printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
0df6b844
LJ
882
883 switch (type) {
884 case DDR2:
632de067
LJ
885 printf ("Number of ranks %d\n",
886 (data[5] & 0x07) + 1);
0df6b844
LJ
887 break;
888 default:
632de067 889 printf ("Module rows %d\n", data[5]);
0df6b844
LJ
890 break;
891 }
892
893 switch (type) {
894 case DDR2:
632de067 895 printf ("Module data width %d bits\n", data[6]);
0df6b844
LJ
896 break;
897 default:
632de067
LJ
898 printf ("Module data width %d bits\n",
899 (data[7] << 8) | data[6]);
0df6b844
LJ
900 break;
901 }
902
4b9206ed 903 puts ("Interface signal levels ");
81a8824f 904 switch(data[8]) {
0df6b844 905 case 0: puts ("TTL 5.0 V\n"); break;
4b9206ed 906 case 1: puts ("LVTTL\n"); break;
0df6b844
LJ
907 case 2: puts ("HSTL 1.5 V\n"); break;
908 case 3: puts ("SSTL 3.3 V\n"); break;
909 case 4: puts ("SSTL 2.5 V\n"); break;
910 case 5: puts ("SSTL 1.8 V\n"); break;
4b9206ed 911 default: puts ("unknown\n"); break;
81a8824f 912 }
0df6b844
LJ
913
914 switch (type) {
915 case DDR2:
632de067
LJ
916 printf ("SDRAM cycle time ");
917 print_ddr2_tcyc (data[9]);
0df6b844
LJ
918 break;
919 default:
632de067
LJ
920 printf ("SDRAM cycle time %d.%d ns\n",
921 (data[9] >> 4) & 0x0F, data[9] & 0x0F);
0df6b844
LJ
922 break;
923 }
924
925 switch (type) {
926 case DDR2:
632de067
LJ
927 printf ("SDRAM access time 0.%d%d ns\n",
928 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
0df6b844
LJ
929 break;
930 default:
632de067
LJ
931 printf ("SDRAM access time %d.%d ns\n",
932 (data[10] >> 4) & 0x0F, data[10] & 0x0F);
0df6b844
LJ
933 break;
934 }
935
4b9206ed 936 puts ("EDC configuration ");
632de067 937 switch (data[11]) {
4b9206ed
WD
938 case 0: puts ("None\n"); break;
939 case 1: puts ("Parity\n"); break;
940 case 2: puts ("ECC\n"); break;
941 default: puts ("unknown\n"); break;
81a8824f 942 }
632de067 943
e857a5bd 944 if ((data[12] & 0x80) == 0)
4b9206ed 945 puts ("No self refresh, rate ");
e857a5bd 946 else
4b9206ed 947 puts ("Self refresh, rate ");
632de067 948
81a8824f 949 switch(data[12] & 0x7F) {
632de067
LJ
950 case 0: puts ("15.625 us\n"); break;
951 case 1: puts ("3.9 us\n"); break;
952 case 2: puts ("7.8 us\n"); break;
953 case 3: puts ("31.3 us\n"); break;
954 case 4: puts ("62.5 us\n"); break;
955 case 5: puts ("125 us\n"); break;
4b9206ed 956 default: puts ("unknown\n"); break;
81a8824f 957 }
0df6b844
LJ
958
959 switch (type) {
960 case DDR2:
632de067 961 printf ("SDRAM width (primary) %d\n", data[13]);
0df6b844
LJ
962 break;
963 default:
632de067 964 printf ("SDRAM width (primary) %d\n", data[13] & 0x7F);
0df6b844 965 if ((data[13] & 0x80) != 0) {
632de067
LJ
966 printf (" (second bank) %d\n",
967 2 * (data[13] & 0x7F));
0df6b844
LJ
968 }
969 break;
970 }
971
972 switch (type) {
973 case DDR2:
974 if (data[14] != 0)
632de067 975 printf ("EDC width %d\n", data[14]);
0df6b844
LJ
976 break;
977 default:
978 if (data[14] != 0) {
632de067
LJ
979 printf ("EDC width %d\n",
980 data[14] & 0x7F);
0df6b844
LJ
981
982 if ((data[14] & 0x80) != 0) {
632de067
LJ
983 printf (" (second bank) %d\n",
984 2 * (data[14] & 0x7F));
0df6b844
LJ
985 }
986 }
987 break;
81a8824f 988 }
0df6b844 989
632de067
LJ
990 if (DDR2 != type) {
991 printf ("Min clock delay, back-to-back random column addresses "
992 "%d\n", data[15]);
0df6b844
LJ
993 }
994
4b9206ed
WD
995 puts ("Burst length(s) ");
996 if (data[16] & 0x80) puts (" Page");
997 if (data[16] & 0x08) puts (" 8");
998 if (data[16] & 0x04) puts (" 4");
999 if (data[16] & 0x02) puts (" 2");
1000 if (data[16] & 0x01) puts (" 1");
1001 putc ('\n');
632de067 1002 printf ("Number of banks %d\n", data[17]);
0df6b844
LJ
1003
1004 switch (type) {
1005 case DDR2:
1006 puts ("CAS latency(s) ");
632de067 1007 decode_bits (data[18], decode_CAS_DDR2, 0);
0df6b844
LJ
1008 putc ('\n');
1009 break;
1010 default:
1011 puts ("CAS latency(s) ");
632de067 1012 decode_bits (data[18], decode_CAS_default, 0);
0df6b844
LJ
1013 putc ('\n');
1014 break;
1015 }
1016
1017 if (DDR2 != type) {
1018 puts ("CS latency(s) ");
632de067 1019 decode_bits (data[19], decode_CS_WE_default, 0);
0df6b844
LJ
1020 putc ('\n');
1021 }
1022
1023 if (DDR2 != type) {
1024 puts ("WE latency(s) ");
632de067 1025 decode_bits (data[20], decode_CS_WE_default, 0);
0df6b844
LJ
1026 putc ('\n');
1027 }
1028
1029 switch (type) {
1030 case DDR2:
1031 puts ("Module attributes:\n");
1032 if (data[21] & 0x80)
1033 puts (" TBD (bit 7)\n");
1034 if (data[21] & 0x40)
1035 puts (" Analysis probe installed\n");
1036 if (data[21] & 0x20)
1037 puts (" TBD (bit 5)\n");
1038 if (data[21] & 0x10)
1039 puts (" FET switch external enable\n");
632de067 1040 printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
0df6b844 1041 if (data[20] & 0x11) {
632de067
LJ
1042 printf (" %d active registers on DIMM\n",
1043 (data[21] & 0x03) + 1);
0df6b844
LJ
1044 }
1045 break;
1046 default:
1047 puts ("Module attributes:\n");
1048 if (!data[21])
1049 puts (" (none)\n");
632de067
LJ
1050 else
1051 decode_bits (data[21], decode_byte21_default, 0);
0df6b844
LJ
1052 break;
1053 }
1054
1055 switch (type) {
1056 case DDR2:
632de067 1057 decode_bits (data[22], decode_byte22_DDR2, 0);
0df6b844
LJ
1058 break;
1059 default:
1060 puts ("Device attributes:\n");
1061 if (data[22] & 0x80) puts (" TBD (bit 7)\n");
1062 if (data[22] & 0x40) puts (" TBD (bit 6)\n");
1063 if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
1064 else puts (" Upper Vcc tolerance 10%\n");
1065 if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
1066 else puts (" Lower Vcc tolerance 10%\n");
1067 if (data[22] & 0x08) puts (" Supports write1/read burst\n");
1068 if (data[22] & 0x04) puts (" Supports precharge all\n");
1069 if (data[22] & 0x02) puts (" Supports auto precharge\n");
1070 if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
1071 break;
1072 }
1073
1074 switch (type) {
1075 case DDR2:
632de067
LJ
1076 printf ("SDRAM cycle time (2nd highest CAS latency) ");
1077 print_ddr2_tcyc (data[23]);
0df6b844
LJ
1078 break;
1079 default:
632de067
LJ
1080 printf ("SDRAM cycle time (2nd highest CAS latency) %d."
1081 "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
0df6b844
LJ
1082 break;
1083 }
1084
1085 switch (type) {
1086 case DDR2:
632de067
LJ
1087 printf ("SDRAM access from clock (2nd highest CAS latency) 0."
1088 "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
0df6b844
LJ
1089 break;
1090 default:
632de067
LJ
1091 printf ("SDRAM access from clock (2nd highest CAS latency) %d."
1092 "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
0df6b844
LJ
1093 break;
1094 }
1095
1096 switch (type) {
1097 case DDR2:
632de067
LJ
1098 printf ("SDRAM cycle time (3rd highest CAS latency) ");
1099 print_ddr2_tcyc (data[25]);
0df6b844
LJ
1100 break;
1101 default:
632de067
LJ
1102 printf ("SDRAM cycle time (3rd highest CAS latency) %d."
1103 "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
0df6b844
LJ
1104 break;
1105 }
1106
1107 switch (type) {
1108 case DDR2:
632de067
LJ
1109 printf ("SDRAM access from clock (3rd highest CAS latency) 0."
1110 "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
0df6b844
LJ
1111 break;
1112 default:
632de067
LJ
1113 printf ("SDRAM access from clock (3rd highest CAS latency) %d."
1114 "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
0df6b844
LJ
1115 break;
1116 }
1117
1118 switch (type) {
1119 case DDR2:
632de067
LJ
1120 printf ("Minimum row precharge %d.%02d ns\n",
1121 (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
0df6b844
LJ
1122 break;
1123 default:
632de067 1124 printf ("Minimum row precharge %d ns\n", data[27]);
0df6b844
LJ
1125 break;
1126 }
1127
1128 switch (type) {
1129 case DDR2:
632de067
LJ
1130 printf ("Row active to row active min %d.%02d ns\n",
1131 (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
0df6b844
LJ
1132 break;
1133 default:
632de067 1134 printf ("Row active to row active min %d ns\n", data[28]);
0df6b844
LJ
1135 break;
1136 }
1137
1138 switch (type) {
1139 case DDR2:
632de067
LJ
1140 printf ("RAS to CAS delay min %d.%02d ns\n",
1141 (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
0df6b844
LJ
1142 break;
1143 default:
632de067 1144 printf ("RAS to CAS delay min %d ns\n", data[29]);
0df6b844
LJ
1145 break;
1146 }
1147
632de067 1148 printf ("Minimum RAS pulse width %d ns\n", data[30]);
0df6b844
LJ
1149
1150 switch (type) {
1151 case DDR2:
632de067
LJ
1152 puts ("Density of each row ");
1153 decode_bits (data[31], decode_row_density_DDR2, 1);
1154 putc ('\n');
0df6b844
LJ
1155 break;
1156 default:
632de067
LJ
1157 puts ("Density of each row ");
1158 decode_bits (data[31], decode_row_density_default, 1);
1159 putc ('\n');
0df6b844
LJ
1160 break;
1161 }
1162
1163 switch (type) {
1164 case DDR2:
632de067 1165 puts ("Command and Address setup ");
0df6b844 1166 if (data[32] >= 0xA0) {
632de067
LJ
1167 printf ("1.%d%d ns\n",
1168 ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
0df6b844 1169 } else {
632de067
LJ
1170 printf ("0.%d%d ns\n",
1171 ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
0df6b844
LJ
1172 }
1173 break;
1174 default:
632de067
LJ
1175 printf ("Command and Address setup %c%d.%d ns\n",
1176 (data[32] & 0x80) ? '-' : '+',
1177 (data[32] >> 4) & 0x07, data[32] & 0x0F);
0df6b844
LJ
1178 break;
1179 }
1180
1181 switch (type) {
1182 case DDR2:
632de067 1183 puts ("Command and Address hold ");
0df6b844 1184 if (data[33] >= 0xA0) {
632de067
LJ
1185 printf ("1.%d%d ns\n",
1186 ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
0df6b844 1187 } else {
632de067
LJ
1188 printf ("0.%d%d ns\n",
1189 ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
0df6b844
LJ
1190 }
1191 break;
1192 default:
632de067
LJ
1193 printf ("Command and Address hold %c%d.%d ns\n",
1194 (data[33] & 0x80) ? '-' : '+',
1195 (data[33] >> 4) & 0x07, data[33] & 0x0F);
0df6b844
LJ
1196 break;
1197 }
1198
1199 switch (type) {
1200 case DDR2:
632de067
LJ
1201 printf ("Data signal input setup 0.%d%d ns\n",
1202 (data[34] >> 4) & 0x0F, data[34] & 0x0F);
0df6b844
LJ
1203 break;
1204 default:
632de067
LJ
1205 printf ("Data signal input setup %c%d.%d ns\n",
1206 (data[34] & 0x80) ? '-' : '+',
1207 (data[34] >> 4) & 0x07, data[34] & 0x0F);
0df6b844
LJ
1208 break;
1209 }
1210
1211 switch (type) {
1212 case DDR2:
632de067
LJ
1213 printf ("Data signal input hold 0.%d%d ns\n",
1214 (data[35] >> 4) & 0x0F, data[35] & 0x0F);
0df6b844
LJ
1215 break;
1216 default:
632de067
LJ
1217 printf ("Data signal input hold %c%d.%d ns\n",
1218 (data[35] & 0x80) ? '-' : '+',
1219 (data[35] >> 4) & 0x07, data[35] & 0x0F);
0df6b844
LJ
1220 break;
1221 }
1222
4b9206ed 1223 puts ("Manufacturer's JEDEC ID ");
e857a5bd 1224 for (j = 64; j <= 71; j++)
632de067 1225 printf ("%02X ", data[j]);
4b9206ed 1226 putc ('\n');
632de067 1227 printf ("Manufacturing Location %02X\n", data[72]);
4b9206ed 1228 puts ("Manufacturer's Part Number ");
e857a5bd 1229 for (j = 73; j <= 90; j++)
632de067 1230 printf ("%02X ", data[j]);
4b9206ed 1231 putc ('\n');
632de067
LJ
1232 printf ("Revision Code %02X %02X\n", data[91], data[92]);
1233 printf ("Manufacturing Date %02X %02X\n", data[93], data[94]);
4b9206ed 1234 puts ("Assembly Serial Number ");
e857a5bd 1235 for (j = 95; j <= 98; j++)
632de067 1236 printf ("%02X ", data[j]);
4b9206ed 1237 putc ('\n');
81a8824f 1238
0df6b844 1239 if (DDR2 != type) {
632de067
LJ
1240 printf ("Speed rating PC%d\n",
1241 data[126] == 0x66 ? 66 : data[126]);
0df6b844 1242 }
81a8824f
WD
1243 return 0;
1244}
90253178 1245#endif
81a8824f 1246
67b23a32 1247#if defined(CONFIG_I2C_MUX)
54841ab5 1248static int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
67b23a32
HS
1249{
1250 int ret=0;
1251
1252 if (argc == 1) {
1253 /* show all busses */
1254 I2C_MUX *mux;
1255 I2C_MUX_DEVICE *device = i2c_mux_devices;
1256
1257 printf ("Busses reached over muxes:\n");
1258 while (device != NULL) {
1259 printf ("Bus ID: %x\n", device->busid);
1260 printf (" reached over Mux(es):\n");
1261 mux = device->mux;
1262 while (mux != NULL) {
1263 printf (" %s@%x ch: %x\n", mux->name, mux->chip, mux->channel);
1264 mux = mux->next;
1265 }
1266 device = device->next;
1267 }
1268 } else {
e8260cb2 1269 (void)i2c_mux_ident_muxstring ((uchar *)argv[1]);
67b23a32
HS
1270 ret = 0;
1271 }
1272 return ret;
1273}
1274#endif /* CONFIG_I2C_MUX */
1275
bb99ad6d 1276#if defined(CONFIG_I2C_MULTI_BUS)
54841ab5 1277static int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bb99ad6d
BW
1278{
1279 int bus_idx, ret=0;
1280
e857a5bd
TT
1281 if (argc == 1)
1282 /* querying current setting */
bb99ad6d 1283 printf("Current bus is %d\n", i2c_get_bus_num());
e857a5bd 1284 else {
bb99ad6d
BW
1285 bus_idx = simple_strtoul(argv[1], NULL, 10);
1286 printf("Setting bus to %d\n", bus_idx);
1287 ret = i2c_set_bus_num(bus_idx);
e857a5bd 1288 if (ret)
bb99ad6d 1289 printf("Failure changing bus number (%d)\n", ret);
bb99ad6d
BW
1290 }
1291 return ret;
1292}
1293#endif /* CONFIG_I2C_MULTI_BUS */
1294
54841ab5 1295static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bb99ad6d
BW
1296{
1297 int speed, ret=0;
1298
e857a5bd
TT
1299 if (argc == 1)
1300 /* querying current speed */
bb99ad6d 1301 printf("Current bus speed=%d\n", i2c_get_bus_speed());
e857a5bd 1302 else {
bb99ad6d
BW
1303 speed = simple_strtoul(argv[1], NULL, 10);
1304 printf("Setting bus speed to %d Hz\n", speed);
1305 ret = i2c_set_bus_speed(speed);
e857a5bd 1306 if (ret)
bb99ad6d 1307 printf("Failure changing bus speed (%d)\n", ret);
bb99ad6d
BW
1308 }
1309 return ret;
1310}
1311
54841ab5 1312static int do_i2c_mm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bb99ad6d 1313{
bfc3b77e
FM
1314 return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
1315}
1316
54841ab5 1317static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bfc3b77e
FM
1318{
1319 return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
1320}
e96ad5d3 1321
54841ab5 1322static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bfc3b77e
FM
1323{
1324 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
1325 return 0;
1326}
1327
1328static cmd_tbl_t cmd_i2c_sub[] = {
67b23a32 1329#if defined(CONFIG_I2C_MUX)
bfc3b77e 1330 U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_add_bus, "", ""),
67b23a32 1331#endif /* CONFIG_I2C_MUX */
bfc3b77e 1332 U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
bb99ad6d 1333#if defined(CONFIG_I2C_MULTI_BUS)
bfc3b77e 1334 U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
bb99ad6d 1335#endif /* CONFIG_I2C_MULTI_BUS */
bfc3b77e
FM
1336 U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""),
1337 U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""),
1338 U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""),
1339 U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""),
1340 U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
1341 U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
652e5354 1342 U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
ff5d2dce 1343 U_BOOT_CMD_MKENT(write, 5, 0, do_i2c_write, "", ""),
bfc3b77e 1344 U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
c76fe474 1345#if defined(CONFIG_CMD_SDRAM)
bfc3b77e 1346 U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
90253178 1347#endif
bfc3b77e
FM
1348 U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""),
1349};
1350
2e5167cc 1351#ifdef CONFIG_NEEDS_MANUAL_RELOC
f1d2b313
HS
1352void i2c_reloc(void) {
1353 fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub));
1354}
1355#endif
1356
54841ab5 1357static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
bfc3b77e
FM
1358{
1359 cmd_tbl_t *c;
1360
4444b221 1361 if (argc < 2)
4c12eeb8 1362 return CMD_RET_USAGE;
4444b221 1363
bfc3b77e
FM
1364 /* Strip off leading 'i2c' command argument */
1365 argc--;
1366 argv++;
1367
1368 c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub));
1369
47e26b1b 1370 if (c)
4c12eeb8 1371 return c->cmd(cmdtp, flag, argc, argv);
47e26b1b 1372 else
4c12eeb8 1373 return CMD_RET_USAGE;
bb99ad6d 1374}
8bde7f77
WD
1375
1376/***************************************************/
088f1b19
KP
1377#ifdef CONFIG_SYS_LONGHELP
1378static char i2c_help_text[] =
67b23a32 1379#if defined(CONFIG_I2C_MUX)
fb0070e9 1380 "bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\ni2c "
67b23a32 1381#endif /* CONFIG_I2C_MUX */
fb0070e9 1382 "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
d9fc7032 1383#if defined(CONFIG_I2C_MULTI_BUS)
9bc2e4ee 1384 "i2c dev [dev] - show or set current I2C bus\n"
d9fc7032 1385#endif /* CONFIG_I2C_MULTI_BUS */
fb0070e9 1386 "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
d9fc7032
MF
1387 "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
1388 "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
1389 "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
1390 "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
54b99e51 1391 "i2c probe [address] - test for and show device(s) on the I2C bus\n"
652e5354 1392 "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n"
ff5d2dce 1393 "i2c write memaddress chip address[.0, .1, .2] length - write memory to i2c\n"
e43a27c4 1394 "i2c reset - re-init the I2C Controller\n"
c76fe474 1395#if defined(CONFIG_CMD_SDRAM)
fb0070e9 1396 "i2c sdram chip - print SDRAM configuration information\n"
90253178 1397#endif
088f1b19
KP
1398 "i2c speed [speed] - show or set I2C bus speed";
1399#endif
1400
1401U_BOOT_CMD(
1402 i2c, 6, 1, do_i2c,
1403 "I2C sub-system",
1404 i2c_help_text
d9fc7032 1405);
67b23a32
HS
1406
1407#if defined(CONFIG_I2C_MUX)
fd03ea89 1408static int i2c_mux_add_device(I2C_MUX_DEVICE *dev)
67b23a32
HS
1409{
1410 I2C_MUX_DEVICE *devtmp = i2c_mux_devices;
1411
1412 if (i2c_mux_devices == NULL) {
1413 i2c_mux_devices = dev;
1414 return 0;
1415 }
1416 while (devtmp->next != NULL)
1417 devtmp = devtmp->next;
1418
1419 devtmp->next = dev;
1420 return 0;
1421}
1422
1423I2C_MUX_DEVICE *i2c_mux_search_device(int id)
1424{
1425 I2C_MUX_DEVICE *device = i2c_mux_devices;
1426
1427 while (device != NULL) {
1428 if (device->busid == id)
1429 return device;
1430 device = device->next;
1431 }
1432 return NULL;
1433}
1434
1435/* searches in the buf from *pos the next ':'.
1436 * returns:
1437 * 0 if found (with *pos = where)
1438 * < 0 if an error occured
1439 * > 0 if the end of buf is reached
1440 */
1441static int i2c_mux_search_next (int *pos, uchar *buf, int len)
1442{
1443 while ((buf[*pos] != ':') && (*pos < len)) {
1444 *pos += 1;
1445 }
1446 if (*pos >= len)
1447 return 1;
1448 if (buf[*pos] != ':')
1449 return -1;
1450 return 0;
1451}
1452
1453static int i2c_mux_get_busid (void)
1454{
1455 int tmp = i2c_mux_busid;
1456
1457 i2c_mux_busid ++;
1458 return tmp;
1459}
1460
f9a78b8d
MJ
1461/* Analyses a Muxstring and immediately sends the
1462 commands to the muxes. Runs from flash.
67b23a32
HS
1463 */
1464int i2c_mux_ident_muxstring_f (uchar *buf)
1465{
1466 int pos = 0;
1467 int oldpos;
1468 int ret = 0;
1469 int len = strlen((char *)buf);
1470 int chip;
1471 uchar channel;
1472 int was = 0;
1473
1474 while (ret == 0) {
1475 oldpos = pos;
1476 /* search name */
1477 ret = i2c_mux_search_next(&pos, buf, len);
1478 if (ret != 0)
1479 printf ("ERROR\n");
1480 /* search address */
1481 pos ++;
1482 oldpos = pos;
1483 ret = i2c_mux_search_next(&pos, buf, len);
1484 if (ret != 0)
1485 printf ("ERROR\n");
1486 buf[pos] = 0;
1487 chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1488 buf[pos] = ':';
1489 /* search channel */
1490 pos ++;
1491 oldpos = pos;
1492 ret = i2c_mux_search_next(&pos, buf, len);
1493 if (ret < 0)
1494 printf ("ERROR\n");
1495 was = 0;
1496 if (buf[pos] != 0) {
1497 buf[pos] = 0;
1498 was = 1;
1499 }
1500 channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1501 if (was)
1502 buf[pos] = ':';
1503 if (i2c_write(chip, 0, 0, &channel, 1) != 0) {
1504 printf ("Error setting Mux: chip:%x channel: \
1505 %x\n", chip, channel);
1506 return -1;
1507 }
1508 pos ++;
1509 oldpos = pos;
1510
1511 }
8ec038a6 1512 i2c_init_board();
67b23a32
HS
1513
1514 return 0;
1515}
1516
1517/* Analyses a Muxstring and if this String is correct
1518 * adds a new I2C Bus.
1519 */
1520I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf)
1521{
1522 I2C_MUX_DEVICE *device;
1523 I2C_MUX *mux;
1524 int pos = 0;
1525 int oldpos;
1526 int ret = 0;
1527 int len = strlen((char *)buf);
1528 int was = 0;
1529
1530 device = (I2C_MUX_DEVICE *)malloc (sizeof(I2C_MUX_DEVICE));
1531 device->mux = NULL;
1532 device->busid = i2c_mux_get_busid ();
1533 device->next = NULL;
1534 while (ret == 0) {
1535 mux = (I2C_MUX *)malloc (sizeof(I2C_MUX));
1536 mux->next = NULL;
1537 /* search name of mux */
1538 oldpos = pos;
1539 ret = i2c_mux_search_next(&pos, buf, len);
1540 if (ret != 0)
1541 printf ("%s no name.\n", __FUNCTION__);
1542 mux->name = (char *)malloc (pos - oldpos + 1);
1543 memcpy (mux->name, &buf[oldpos], pos - oldpos);
1544 mux->name[pos - oldpos] = 0;
1545 /* search address */
1546 pos ++;
1547 oldpos = pos;
1548 ret = i2c_mux_search_next(&pos, buf, len);
1549 if (ret != 0)
1550 printf ("%s no mux address.\n", __FUNCTION__);
1551 buf[pos] = 0;
1552 mux->chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1553 buf[pos] = ':';
1554 /* search channel */
1555 pos ++;
1556 oldpos = pos;
1557 ret = i2c_mux_search_next(&pos, buf, len);
1558 if (ret < 0)
1559 printf ("%s no mux channel.\n", __FUNCTION__);
1560 was = 0;
1561 if (buf[pos] != 0) {
1562 buf[pos] = 0;
1563 was = 1;
1564 }
1565 mux->channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
1566 if (was)
1567 buf[pos] = ':';
1568 if (device->mux == NULL)
1569 device->mux = mux;
1570 else {
1571 I2C_MUX *muxtmp = device->mux;
1572 while (muxtmp->next != NULL) {
1573 muxtmp = muxtmp->next;
1574 }
1575 muxtmp->next = mux;
1576 }
1577 pos ++;
1578 oldpos = pos;
1579 }
1580 if (ret > 0) {
1581 /* Add Device */
1582 i2c_mux_add_device (device);
1583 return device;
1584 }
1585
1586 return NULL;
1587}
1588
1589int i2x_mux_select_mux(int bus)
1590{
1591 I2C_MUX_DEVICE *dev;
1592 I2C_MUX *mux;
1593
1594 if ((gd->flags & GD_FLG_RELOC) != GD_FLG_RELOC) {
1595 /* select Default Mux Bus */
6d0f6bcf
JCPV
1596#if defined(CONFIG_SYS_I2C_IVM_BUS)
1597 i2c_mux_ident_muxstring_f ((uchar *)CONFIG_SYS_I2C_IVM_BUS);
67b23a32
HS
1598#else
1599 {
1600 unsigned char *buf;
1601 buf = (unsigned char *) getenv("EEprom_ivm");
1602 if (buf != NULL)
1603 i2c_mux_ident_muxstring_f (buf);
1604 }
1605#endif
1606 return 0;
1607 }
1608 dev = i2c_mux_search_device(bus);
1609 if (dev == NULL)
1610 return -1;
1611
1612 mux = dev->mux;
1613 while (mux != NULL) {
c649dda5
SB
1614 /* do deblocking on each level of mux, before mux config */
1615 i2c_init_board();
67b23a32
HS
1616 if (i2c_write(mux->chip, 0, 0, &mux->channel, 1) != 0) {
1617 printf ("Error setting Mux: chip:%x channel: \
1618 %x\n", mux->chip, mux->channel);
1619 return -1;
1620 }
1621 mux = mux->next;
1622 }
c649dda5
SB
1623 /* do deblocking on each level of mux and after mux config */
1624 i2c_init_board();
67b23a32
HS
1625 return 0;
1626}
1627#endif /* CONFIG_I2C_MUX */