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81a8824f WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * I2C Functions similar to the standard memory functions. | |
26 | * | |
27 | * There are several parameters in many of the commands that bear further | |
28 | * explanations: | |
29 | * | |
30 | * Two of the commands (imm and imw) take a byte/word/long modifier | |
31 | * (e.g. imm.w specifies the word-length modifier). This was done to | |
32 | * allow manipulating word-length registers. It was not done on any other | |
33 | * commands because it was not deemed useful. | |
34 | * | |
35 | * {i2c_chip} is the I2C chip address (the first byte sent on the bus). | |
36 | * Each I2C chip on the bus has a unique address. On the I2C data bus, | |
37 | * the address is the upper seven bits and the LSB is the "read/write" | |
38 | * bit. Note that the {i2c_chip} address specified on the command | |
39 | * line is not shifted up: e.g. a typical EEPROM memory chip may have | |
40 | * an I2C address of 0x50, but the data put on the bus will be 0xA0 | |
41 | * for write and 0xA1 for read. This "non shifted" address notation | |
42 | * matches at least half of the data sheets :-/. | |
43 | * | |
44 | * {addr} is the address (or offset) within the chip. Small memory | |
45 | * chips have 8 bit addresses. Large memory chips have 16 bit | |
46 | * addresses. Other memory chips have 9, 10, or 11 bit addresses. | |
47 | * Many non-memory chips have multiple registers and {addr} is used | |
48 | * as the register index. Some non-memory chips have only one register | |
49 | * and therefore don't need any {addr} parameter. | |
50 | * | |
51 | * The default {addr} parameter is one byte (.1) which works well for | |
52 | * memories and registers with 8 bits of address space. | |
53 | * | |
54 | * You can specify the length of the {addr} field with the optional .0, | |
55 | * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are | |
56 | * manipulating a single register device which doesn't use an address | |
57 | * field, use "0.0" for the address and the ".0" length field will | |
58 | * suppress the address in the I2C data stream. This also works for | |
59 | * successive reads using the I2C auto-incrementing memory pointer. | |
60 | * | |
61 | * If you are manipulating a large memory with 2-byte addresses, use | |
62 | * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal). | |
63 | * | |
64 | * Then there are the unfortunate memory chips that spill the most | |
65 | * significant 1, 2, or 3 bits of address into the chip address byte. | |
66 | * This effectively makes one chip (logically) look like 2, 4, or | |
67 | * 8 chips. This is handled (awkwardly) by #defining | |
68 | * CFG_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the | |
69 | * {addr} field (since .1 is the default, it doesn't actually have to | |
70 | * be specified). Examples: given a memory chip at I2C chip address | |
71 | * 0x50, the following would happen... | |
72 | * imd 50 0 10 display 16 bytes starting at 0x000 | |
73 | * On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd> | |
74 | * imd 50 100 10 display 16 bytes starting at 0x100 | |
75 | * On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd> | |
76 | * imd 50 210 10 display 16 bytes starting at 0x210 | |
77 | * On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd> | |
78 | * This is awfully ugly. It would be nice if someone would think up | |
79 | * a better way of handling this. | |
80 | * | |
81 | * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de). | |
82 | */ | |
83 | ||
84 | #include <common.h> | |
85 | #include <command.h> | |
81a8824f WD |
86 | #include <i2c.h> |
87 | #include <asm/byteorder.h> | |
88 | ||
81a8824f WD |
89 | /* Display values from last command. |
90 | * Memory modify remembered values are different from display memory. | |
91 | */ | |
92 | static uchar i2c_dp_last_chip; | |
93 | static uint i2c_dp_last_addr; | |
94 | static uint i2c_dp_last_alen; | |
95 | static uint i2c_dp_last_length = 0x10; | |
96 | ||
97 | static uchar i2c_mm_last_chip; | |
98 | static uint i2c_mm_last_addr; | |
99 | static uint i2c_mm_last_alen; | |
100 | ||
bb99ad6d BW |
101 | /* If only one I2C bus is present, the list of devices to ignore when |
102 | * the probe command is issued is represented by a 1D array of addresses. | |
103 | * When multiple buses are present, the list is an array of bus-address | |
104 | * pairs. The following macros take care of this */ | |
105 | ||
81a8824f | 106 | #if defined(CFG_I2C_NOPROBES) |
bb99ad6d BW |
107 | #if defined(CONFIG_I2C_MULTI_BUS) |
108 | static struct | |
109 | { | |
110 | uchar bus; | |
111 | uchar addr; | |
112 | } i2c_no_probes[] = CFG_I2C_NOPROBES; | |
113 | #define GET_BUS_NUM i2c_get_bus_num() | |
114 | #define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b)) | |
115 | #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a)) | |
116 | #define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr | |
117 | #else /* single bus */ | |
81a8824f | 118 | static uchar i2c_no_probes[] = CFG_I2C_NOPROBES; |
bb99ad6d BW |
119 | #define GET_BUS_NUM 0 |
120 | #define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */ | |
121 | #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a)) | |
122 | #define NO_PROBE_ADDR(i) i2c_no_probes[(i)] | |
123 | #endif /* CONFIG_MULTI_BUS */ | |
124 | ||
125 | #define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0])) | |
81a8824f WD |
126 | #endif |
127 | ||
128 | static int | |
129 | mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]); | |
81a8824f WD |
130 | |
131 | /* | |
132 | * Syntax: | |
133 | * imd {i2c_chip} {addr}{.0, .1, .2} {len} | |
134 | */ | |
135 | #define DISP_LINE_LEN 16 | |
136 | ||
137 | int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
138 | { | |
139 | u_char chip; | |
140 | uint addr, alen, length; | |
141 | int j, nbytes, linebytes; | |
142 | ||
143 | /* We use the last specified parameters, unless new ones are | |
144 | * entered. | |
145 | */ | |
146 | chip = i2c_dp_last_chip; | |
147 | addr = i2c_dp_last_addr; | |
148 | alen = i2c_dp_last_alen; | |
149 | length = i2c_dp_last_length; | |
150 | ||
151 | if (argc < 3) { | |
152 | printf ("Usage:\n%s\n", cmdtp->usage); | |
153 | return 1; | |
154 | } | |
155 | ||
156 | if ((flag & CMD_FLAG_REPEAT) == 0) { | |
157 | /* | |
158 | * New command specified. | |
159 | */ | |
160 | alen = 1; | |
161 | ||
162 | /* | |
163 | * I2C chip address | |
164 | */ | |
165 | chip = simple_strtoul(argv[1], NULL, 16); | |
166 | ||
167 | /* | |
168 | * I2C data address within the chip. This can be 1 or | |
169 | * 2 bytes long. Some day it might be 3 bytes long :-). | |
170 | */ | |
171 | addr = simple_strtoul(argv[2], NULL, 16); | |
172 | alen = 1; | |
e857a5bd | 173 | for (j = 0; j < 8; j++) { |
81a8824f WD |
174 | if (argv[2][j] == '.') { |
175 | alen = argv[2][j+1] - '0'; | |
176 | if (alen > 4) { | |
177 | printf ("Usage:\n%s\n", cmdtp->usage); | |
178 | return 1; | |
179 | } | |
180 | break; | |
e857a5bd | 181 | } else if (argv[2][j] == '\0') |
81a8824f | 182 | break; |
81a8824f WD |
183 | } |
184 | ||
185 | /* | |
186 | * If another parameter, it is the length to display. | |
187 | * Length is the number of objects, not number of bytes. | |
188 | */ | |
189 | if (argc > 3) | |
190 | length = simple_strtoul(argv[3], NULL, 16); | |
191 | } | |
192 | ||
193 | /* | |
194 | * Print the lines. | |
195 | * | |
196 | * We buffer all read data, so we can make sure data is read only | |
197 | * once. | |
198 | */ | |
199 | nbytes = length; | |
200 | do { | |
201 | unsigned char linebuf[DISP_LINE_LEN]; | |
202 | unsigned char *cp; | |
203 | ||
204 | linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; | |
205 | ||
e857a5bd | 206 | if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0) |
4b9206ed | 207 | puts ("Error reading the chip.\n"); |
e857a5bd | 208 | else { |
81a8824f WD |
209 | printf("%04x:", addr); |
210 | cp = linebuf; | |
211 | for (j=0; j<linebytes; j++) { | |
212 | printf(" %02x", *cp++); | |
213 | addr++; | |
214 | } | |
4b9206ed | 215 | puts (" "); |
81a8824f WD |
216 | cp = linebuf; |
217 | for (j=0; j<linebytes; j++) { | |
218 | if ((*cp < 0x20) || (*cp > 0x7e)) | |
4b9206ed | 219 | puts ("."); |
81a8824f WD |
220 | else |
221 | printf("%c", *cp); | |
222 | cp++; | |
223 | } | |
4b9206ed | 224 | putc ('\n'); |
81a8824f WD |
225 | } |
226 | nbytes -= linebytes; | |
227 | } while (nbytes > 0); | |
228 | ||
229 | i2c_dp_last_chip = chip; | |
230 | i2c_dp_last_addr = addr; | |
231 | i2c_dp_last_alen = alen; | |
232 | i2c_dp_last_length = length; | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
237 | int do_i2c_mm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
238 | { | |
239 | return mod_i2c_mem (cmdtp, 1, flag, argc, argv); | |
240 | } | |
241 | ||
242 | ||
243 | int do_i2c_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
244 | { | |
245 | return mod_i2c_mem (cmdtp, 0, flag, argc, argv); | |
246 | } | |
247 | ||
248 | /* Write (fill) memory | |
249 | * | |
250 | * Syntax: | |
251 | * imw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}] | |
252 | */ | |
253 | int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
254 | { | |
255 | uchar chip; | |
256 | ulong addr; | |
257 | uint alen; | |
258 | uchar byte; | |
259 | int count; | |
260 | int j; | |
261 | ||
262 | if ((argc < 4) || (argc > 5)) { | |
263 | printf ("Usage:\n%s\n", cmdtp->usage); | |
264 | return 1; | |
265 | } | |
266 | ||
267 | /* | |
53677ef1 WD |
268 | * Chip is always specified. |
269 | */ | |
81a8824f WD |
270 | chip = simple_strtoul(argv[1], NULL, 16); |
271 | ||
272 | /* | |
273 | * Address is always specified. | |
274 | */ | |
275 | addr = simple_strtoul(argv[2], NULL, 16); | |
276 | alen = 1; | |
e857a5bd | 277 | for (j = 0; j < 8; j++) { |
81a8824f WD |
278 | if (argv[2][j] == '.') { |
279 | alen = argv[2][j+1] - '0'; | |
e857a5bd | 280 | if (alen > 4) { |
81a8824f WD |
281 | printf ("Usage:\n%s\n", cmdtp->usage); |
282 | return 1; | |
283 | } | |
284 | break; | |
e857a5bd | 285 | } else if (argv[2][j] == '\0') |
81a8824f | 286 | break; |
81a8824f WD |
287 | } |
288 | ||
289 | /* | |
290 | * Value to write is always specified. | |
291 | */ | |
292 | byte = simple_strtoul(argv[3], NULL, 16); | |
293 | ||
294 | /* | |
295 | * Optional count | |
296 | */ | |
e857a5bd | 297 | if (argc == 5) |
81a8824f | 298 | count = simple_strtoul(argv[4], NULL, 16); |
e857a5bd | 299 | else |
81a8824f | 300 | count = 1; |
81a8824f WD |
301 | |
302 | while (count-- > 0) { | |
e857a5bd | 303 | if (i2c_write(chip, addr++, alen, &byte, 1) != 0) |
4b9206ed | 304 | puts ("Error writing the chip.\n"); |
81a8824f WD |
305 | /* |
306 | * Wait for the write to complete. The write can take | |
307 | * up to 10mSec (we allow a little more time). | |
308 | * | |
309 | * On some chips, while the write is in progress, the | |
310 | * chip doesn't respond. This apparently isn't a | |
311 | * universal feature so we don't take advantage of it. | |
312 | */ | |
d4f5c728 | 313 | /* |
314 | * No write delay with FRAM devices. | |
315 | */ | |
316 | #if !defined(CFG_I2C_FRAM) | |
81a8824f | 317 | udelay(11000); |
d4f5c728 | 318 | #endif |
319 | ||
81a8824f | 320 | #if 0 |
e857a5bd | 321 | for (timeout = 0; timeout < 10; timeout++) { |
81a8824f | 322 | udelay(2000); |
e857a5bd | 323 | if (i2c_probe(chip) == 0) |
81a8824f WD |
324 | break; |
325 | } | |
326 | #endif | |
327 | } | |
328 | ||
329 | return (0); | |
330 | } | |
331 | ||
332 | ||
333 | /* Calculate a CRC on memory | |
334 | * | |
335 | * Syntax: | |
336 | * icrc32 {i2c_chip} {addr}{.0, .1, .2} {count} | |
337 | */ | |
338 | int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
339 | { | |
340 | uchar chip; | |
341 | ulong addr; | |
342 | uint alen; | |
343 | int count; | |
344 | uchar byte; | |
345 | ulong crc; | |
346 | ulong err; | |
347 | int j; | |
348 | ||
349 | if (argc < 4) { | |
350 | printf ("Usage:\n%s\n", cmdtp->usage); | |
351 | return 1; | |
352 | } | |
353 | ||
354 | /* | |
53677ef1 WD |
355 | * Chip is always specified. |
356 | */ | |
81a8824f WD |
357 | chip = simple_strtoul(argv[1], NULL, 16); |
358 | ||
359 | /* | |
360 | * Address is always specified. | |
361 | */ | |
362 | addr = simple_strtoul(argv[2], NULL, 16); | |
363 | alen = 1; | |
e857a5bd | 364 | for (j = 0; j < 8; j++) { |
81a8824f WD |
365 | if (argv[2][j] == '.') { |
366 | alen = argv[2][j+1] - '0'; | |
e857a5bd | 367 | if (alen > 4) { |
81a8824f WD |
368 | printf ("Usage:\n%s\n", cmdtp->usage); |
369 | return 1; | |
370 | } | |
371 | break; | |
e857a5bd | 372 | } else if (argv[2][j] == '\0') |
81a8824f | 373 | break; |
81a8824f WD |
374 | } |
375 | ||
376 | /* | |
377 | * Count is always specified | |
378 | */ | |
379 | count = simple_strtoul(argv[3], NULL, 16); | |
380 | ||
381 | printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1); | |
382 | /* | |
383 | * CRC a byte at a time. This is going to be slooow, but hey, the | |
384 | * memories are small and slow too so hopefully nobody notices. | |
385 | */ | |
386 | crc = 0; | |
387 | err = 0; | |
e857a5bd TT |
388 | while (count-- > 0) { |
389 | if (i2c_read(chip, addr, alen, &byte, 1) != 0) | |
81a8824f | 390 | err++; |
81a8824f WD |
391 | crc = crc32 (crc, &byte, 1); |
392 | addr++; | |
393 | } | |
e857a5bd | 394 | if (err > 0) |
4b9206ed | 395 | puts ("Error reading the chip,\n"); |
e857a5bd | 396 | else |
81a8824f | 397 | printf ("%08lx\n", crc); |
81a8824f WD |
398 | |
399 | return 0; | |
400 | } | |
401 | ||
402 | ||
403 | /* Modify memory. | |
404 | * | |
405 | * Syntax: | |
406 | * imm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2} | |
407 | * inm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2} | |
408 | */ | |
409 | ||
410 | static int | |
411 | mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) | |
412 | { | |
413 | uchar chip; | |
414 | ulong addr; | |
415 | uint alen; | |
416 | ulong data; | |
417 | int size = 1; | |
418 | int nbytes; | |
419 | int j; | |
420 | extern char console_buffer[]; | |
421 | ||
422 | if (argc != 3) { | |
423 | printf ("Usage:\n%s\n", cmdtp->usage); | |
424 | return 1; | |
425 | } | |
426 | ||
427 | #ifdef CONFIG_BOOT_RETRY_TIME | |
428 | reset_cmd_timeout(); /* got a good command to get here */ | |
429 | #endif | |
430 | /* | |
431 | * We use the last specified parameters, unless new ones are | |
432 | * entered. | |
433 | */ | |
434 | chip = i2c_mm_last_chip; | |
435 | addr = i2c_mm_last_addr; | |
436 | alen = i2c_mm_last_alen; | |
437 | ||
438 | if ((flag & CMD_FLAG_REPEAT) == 0) { | |
439 | /* | |
440 | * New command specified. Check for a size specification. | |
441 | * Defaults to byte if no or incorrect specification. | |
442 | */ | |
443 | size = cmd_get_data_size(argv[0], 1); | |
444 | ||
445 | /* | |
53677ef1 WD |
446 | * Chip is always specified. |
447 | */ | |
81a8824f WD |
448 | chip = simple_strtoul(argv[1], NULL, 16); |
449 | ||
450 | /* | |
451 | * Address is always specified. | |
452 | */ | |
453 | addr = simple_strtoul(argv[2], NULL, 16); | |
454 | alen = 1; | |
e857a5bd | 455 | for (j = 0; j < 8; j++) { |
81a8824f WD |
456 | if (argv[2][j] == '.') { |
457 | alen = argv[2][j+1] - '0'; | |
e857a5bd | 458 | if (alen > 4) { |
81a8824f WD |
459 | printf ("Usage:\n%s\n", cmdtp->usage); |
460 | return 1; | |
461 | } | |
462 | break; | |
e857a5bd | 463 | } else if (argv[2][j] == '\0') |
81a8824f | 464 | break; |
81a8824f WD |
465 | } |
466 | } | |
467 | ||
468 | /* | |
469 | * Print the address, followed by value. Then accept input for | |
470 | * the next value. A non-converted value exits. | |
471 | */ | |
472 | do { | |
473 | printf("%08lx:", addr); | |
e857a5bd | 474 | if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0) |
4b9206ed | 475 | puts ("\nError reading the chip,\n"); |
e857a5bd | 476 | else { |
81a8824f | 477 | data = cpu_to_be32(data); |
e857a5bd | 478 | if (size == 1) |
81a8824f | 479 | printf(" %02lx", (data >> 24) & 0x000000FF); |
e857a5bd | 480 | else if (size == 2) |
81a8824f | 481 | printf(" %04lx", (data >> 16) & 0x0000FFFF); |
e857a5bd | 482 | else |
81a8824f | 483 | printf(" %08lx", data); |
81a8824f WD |
484 | } |
485 | ||
486 | nbytes = readline (" ? "); | |
487 | if (nbytes == 0) { | |
488 | /* | |
489 | * <CR> pressed as only input, don't modify current | |
490 | * location and move to next. | |
491 | */ | |
492 | if (incrflag) | |
493 | addr += size; | |
494 | nbytes = size; | |
495 | #ifdef CONFIG_BOOT_RETRY_TIME | |
496 | reset_cmd_timeout(); /* good enough to not time out */ | |
497 | #endif | |
498 | } | |
499 | #ifdef CONFIG_BOOT_RETRY_TIME | |
e857a5bd | 500 | else if (nbytes == -2) |
81a8824f | 501 | break; /* timed out, exit the command */ |
81a8824f WD |
502 | #endif |
503 | else { | |
504 | char *endp; | |
505 | ||
506 | data = simple_strtoul(console_buffer, &endp, 16); | |
e857a5bd | 507 | if (size == 1) |
81a8824f | 508 | data = data << 24; |
e857a5bd | 509 | else if (size == 2) |
81a8824f | 510 | data = data << 16; |
81a8824f WD |
511 | data = be32_to_cpu(data); |
512 | nbytes = endp - console_buffer; | |
513 | if (nbytes) { | |
514 | #ifdef CONFIG_BOOT_RETRY_TIME | |
515 | /* | |
516 | * good enough to not time out | |
517 | */ | |
518 | reset_cmd_timeout(); | |
519 | #endif | |
e857a5bd | 520 | if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) |
4b9206ed | 521 | puts ("Error writing the chip.\n"); |
2535d602 WD |
522 | #ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS |
523 | udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); | |
524 | #endif | |
81a8824f WD |
525 | if (incrflag) |
526 | addr += size; | |
527 | } | |
528 | } | |
529 | } while (nbytes); | |
530 | ||
0800707b PT |
531 | i2c_mm_last_chip = chip; |
532 | i2c_mm_last_addr = addr; | |
533 | i2c_mm_last_alen = alen; | |
81a8824f WD |
534 | |
535 | return 0; | |
536 | } | |
537 | ||
538 | /* | |
539 | * Syntax: | |
540 | * iprobe {addr}{.0, .1, .2} | |
541 | */ | |
542 | int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
543 | { | |
544 | int j; | |
545 | #if defined(CFG_I2C_NOPROBES) | |
546 | int k, skip; | |
bb99ad6d BW |
547 | uchar bus = GET_BUS_NUM; |
548 | #endif /* NOPROBES */ | |
81a8824f | 549 | |
4b9206ed | 550 | puts ("Valid chip addresses:"); |
e857a5bd | 551 | for (j = 0; j < 128; j++) { |
81a8824f WD |
552 | #if defined(CFG_I2C_NOPROBES) |
553 | skip = 0; | |
e857a5bd TT |
554 | for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) { |
555 | if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) { | |
81a8824f WD |
556 | skip = 1; |
557 | break; | |
558 | } | |
559 | } | |
560 | if (skip) | |
561 | continue; | |
562 | #endif | |
e857a5bd | 563 | if (i2c_probe(j) == 0) |
81a8824f | 564 | printf(" %02X", j); |
81a8824f | 565 | } |
4b9206ed | 566 | putc ('\n'); |
81a8824f WD |
567 | |
568 | #if defined(CFG_I2C_NOPROBES) | |
569 | puts ("Excluded chip addresses:"); | |
e857a5bd TT |
570 | for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) { |
571 | if (COMPARE_BUS(bus,k)) | |
bb99ad6d BW |
572 | printf(" %02X", NO_PROBE_ADDR(k)); |
573 | } | |
4b9206ed | 574 | putc ('\n'); |
81a8824f WD |
575 | #endif |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
580 | ||
581 | /* | |
582 | * Syntax: | |
583 | * iloop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}] | |
584 | * {length} - Number of bytes to read | |
585 | * {delay} - A DECIMAL number and defaults to 1000 uSec | |
586 | */ | |
587 | int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
588 | { | |
589 | u_char chip; | |
590 | ulong alen; | |
591 | uint addr; | |
592 | uint length; | |
593 | u_char bytes[16]; | |
594 | int delay; | |
595 | int j; | |
596 | ||
597 | if (argc < 3) { | |
598 | printf ("Usage:\n%s\n", cmdtp->usage); | |
599 | return 1; | |
600 | } | |
601 | ||
602 | /* | |
603 | * Chip is always specified. | |
604 | */ | |
605 | chip = simple_strtoul(argv[1], NULL, 16); | |
606 | ||
607 | /* | |
608 | * Address is always specified. | |
609 | */ | |
610 | addr = simple_strtoul(argv[2], NULL, 16); | |
611 | alen = 1; | |
e857a5bd | 612 | for (j = 0; j < 8; j++) { |
81a8824f WD |
613 | if (argv[2][j] == '.') { |
614 | alen = argv[2][j+1] - '0'; | |
615 | if (alen > 4) { | |
616 | printf ("Usage:\n%s\n", cmdtp->usage); | |
617 | return 1; | |
618 | } | |
619 | break; | |
e857a5bd | 620 | } else if (argv[2][j] == '\0') |
81a8824f | 621 | break; |
81a8824f WD |
622 | } |
623 | ||
624 | /* | |
625 | * Length is the number of objects, not number of bytes. | |
626 | */ | |
627 | length = 1; | |
628 | length = simple_strtoul(argv[3], NULL, 16); | |
e857a5bd | 629 | if (length > sizeof(bytes)) |
81a8824f | 630 | length = sizeof(bytes); |
81a8824f WD |
631 | |
632 | /* | |
633 | * The delay time (uSec) is optional. | |
634 | */ | |
635 | delay = 1000; | |
e857a5bd | 636 | if (argc > 3) |
81a8824f | 637 | delay = simple_strtoul(argv[4], NULL, 10); |
81a8824f WD |
638 | /* |
639 | * Run the loop... | |
640 | */ | |
e857a5bd TT |
641 | while (1) { |
642 | if (i2c_read(chip, addr, alen, bytes, length) != 0) | |
4b9206ed | 643 | puts ("Error reading the chip.\n"); |
81a8824f WD |
644 | udelay(delay); |
645 | } | |
646 | ||
647 | /* NOTREACHED */ | |
648 | return 0; | |
649 | } | |
650 | ||
651 | ||
652 | /* | |
653 | * The SDRAM command is separately configured because many | |
654 | * (most?) embedded boards don't use SDRAM DIMMs. | |
655 | */ | |
c76fe474 | 656 | #if defined(CONFIG_CMD_SDRAM) |
632de067 LJ |
657 | static void print_ddr2_tcyc (u_char const b) |
658 | { | |
659 | printf ("%d.", (b >> 4) & 0x0F); | |
660 | switch (b & 0x0F) { | |
661 | case 0x0: | |
662 | case 0x1: | |
663 | case 0x2: | |
664 | case 0x3: | |
665 | case 0x4: | |
666 | case 0x5: | |
667 | case 0x6: | |
668 | case 0x7: | |
669 | case 0x8: | |
670 | case 0x9: | |
671 | printf ("%d ns\n", b & 0x0F); | |
672 | break; | |
673 | case 0xA: | |
674 | puts ("25 ns\n"); | |
675 | break; | |
676 | case 0xB: | |
677 | puts ("33 ns\n"); | |
678 | break; | |
679 | case 0xC: | |
680 | puts ("66 ns\n"); | |
681 | break; | |
682 | case 0xD: | |
683 | puts ("75 ns\n"); | |
684 | break; | |
685 | default: | |
686 | puts ("?? ns\n"); | |
687 | break; | |
688 | } | |
689 | } | |
690 | ||
691 | static void decode_bits (u_char const b, char const *str[], int const do_once) | |
692 | { | |
693 | u_char mask; | |
694 | ||
695 | for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) { | |
696 | if (b & mask) { | |
697 | puts (*str); | |
698 | if (do_once) | |
699 | return; | |
700 | } | |
701 | } | |
702 | } | |
81a8824f WD |
703 | |
704 | /* | |
705 | * Syntax: | |
706 | * sdram {i2c_chip} | |
707 | */ | |
632de067 | 708 | int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
81a8824f | 709 | { |
632de067 LJ |
710 | enum { unknown, EDO, SDRAM, DDR2 } type; |
711 | ||
81a8824f WD |
712 | u_char chip; |
713 | u_char data[128]; | |
714 | u_char cksum; | |
715 | int j; | |
716 | ||
632de067 LJ |
717 | static const char *decode_CAS_DDR2[] = { |
718 | " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD" | |
719 | }; | |
720 | ||
721 | static const char *decode_CAS_default[] = { | |
722 | " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1" | |
723 | }; | |
724 | ||
725 | static const char *decode_CS_WE_default[] = { | |
726 | " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0" | |
727 | }; | |
728 | ||
729 | static const char *decode_byte21_default[] = { | |
730 | " TBD (bit 7)\n", | |
731 | " Redundant row address\n", | |
732 | " Differential clock input\n", | |
733 | " Registerd DQMB inputs\n", | |
734 | " Buffered DQMB inputs\n", | |
735 | " On-card PLL\n", | |
736 | " Registered address/control lines\n", | |
737 | " Buffered address/control lines\n" | |
738 | }; | |
739 | ||
740 | static const char *decode_byte22_DDR2[] = { | |
741 | " TBD (bit 7)\n", | |
742 | " TBD (bit 6)\n", | |
743 | " TBD (bit 5)\n", | |
744 | " TBD (bit 4)\n", | |
745 | " TBD (bit 3)\n", | |
746 | " Supports partial array self refresh\n", | |
747 | " Supports 50 ohm ODT\n", | |
748 | " Supports weak driver\n" | |
749 | }; | |
750 | ||
751 | static const char *decode_row_density_DDR2[] = { | |
752 | "512 MiB", "256 MiB", "128 MiB", "16 GiB", | |
753 | "8 GiB", "4 GiB", "2 GiB", "1 GiB" | |
754 | }; | |
755 | ||
756 | static const char *decode_row_density_default[] = { | |
757 | "512 MiB", "256 MiB", "128 MiB", "64 MiB", | |
758 | "32 MiB", "16 MiB", "8 MiB", "4 MiB" | |
759 | }; | |
760 | ||
81a8824f WD |
761 | if (argc < 2) { |
762 | printf ("Usage:\n%s\n", cmdtp->usage); | |
763 | return 1; | |
764 | } | |
765 | /* | |
766 | * Chip is always specified. | |
632de067 LJ |
767 | */ |
768 | chip = simple_strtoul (argv[1], NULL, 16); | |
81a8824f | 769 | |
632de067 | 770 | if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) { |
4b9206ed | 771 | puts ("No SDRAM Serial Presence Detect found.\n"); |
81a8824f WD |
772 | return 1; |
773 | } | |
774 | ||
775 | cksum = 0; | |
776 | for (j = 0; j < 63; j++) { | |
777 | cksum += data[j]; | |
778 | } | |
e857a5bd | 779 | if (cksum != data[63]) { |
81a8824f | 780 | printf ("WARNING: Configuration data checksum failure:\n" |
632de067 | 781 | " is 0x%02x, calculated 0x%02x\n", data[63], cksum); |
81a8824f | 782 | } |
632de067 | 783 | printf ("SPD data revision %d.%d\n", |
81a8824f | 784 | (data[62] >> 4) & 0x0F, data[62] & 0x0F); |
632de067 LJ |
785 | printf ("Bytes used 0x%02X\n", data[0]); |
786 | printf ("Serial memory size 0x%02X\n", 1 << data[1]); | |
787 | ||
4b9206ed | 788 | puts ("Memory type "); |
632de067 | 789 | switch (data[2]) { |
0df6b844 LJ |
790 | case 2: |
791 | type = EDO; | |
792 | puts ("EDO\n"); | |
793 | break; | |
794 | case 4: | |
795 | type = SDRAM; | |
796 | puts ("SDRAM\n"); | |
797 | break; | |
798 | case 8: | |
799 | type = DDR2; | |
800 | puts ("DDR2\n"); | |
801 | break; | |
802 | default: | |
803 | type = unknown; | |
804 | puts ("unknown\n"); | |
805 | break; | |
81a8824f | 806 | } |
632de067 | 807 | |
4b9206ed | 808 | puts ("Row address bits "); |
e857a5bd | 809 | if ((data[3] & 0x00F0) == 0) |
632de067 | 810 | printf ("%d\n", data[3] & 0x0F); |
e857a5bd | 811 | else |
632de067 LJ |
812 | printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F); |
813 | ||
4b9206ed | 814 | puts ("Column address bits "); |
e857a5bd | 815 | if ((data[4] & 0x00F0) == 0) |
632de067 | 816 | printf ("%d\n", data[4] & 0x0F); |
e857a5bd | 817 | else |
632de067 | 818 | printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F); |
0df6b844 LJ |
819 | |
820 | switch (type) { | |
821 | case DDR2: | |
632de067 LJ |
822 | printf ("Number of ranks %d\n", |
823 | (data[5] & 0x07) + 1); | |
0df6b844 LJ |
824 | break; |
825 | default: | |
632de067 | 826 | printf ("Module rows %d\n", data[5]); |
0df6b844 LJ |
827 | break; |
828 | } | |
829 | ||
830 | switch (type) { | |
831 | case DDR2: | |
632de067 | 832 | printf ("Module data width %d bits\n", data[6]); |
0df6b844 LJ |
833 | break; |
834 | default: | |
632de067 LJ |
835 | printf ("Module data width %d bits\n", |
836 | (data[7] << 8) | data[6]); | |
0df6b844 LJ |
837 | break; |
838 | } | |
839 | ||
4b9206ed | 840 | puts ("Interface signal levels "); |
81a8824f | 841 | switch(data[8]) { |
0df6b844 | 842 | case 0: puts ("TTL 5.0 V\n"); break; |
4b9206ed | 843 | case 1: puts ("LVTTL\n"); break; |
0df6b844 LJ |
844 | case 2: puts ("HSTL 1.5 V\n"); break; |
845 | case 3: puts ("SSTL 3.3 V\n"); break; | |
846 | case 4: puts ("SSTL 2.5 V\n"); break; | |
847 | case 5: puts ("SSTL 1.8 V\n"); break; | |
4b9206ed | 848 | default: puts ("unknown\n"); break; |
81a8824f | 849 | } |
0df6b844 LJ |
850 | |
851 | switch (type) { | |
852 | case DDR2: | |
632de067 LJ |
853 | printf ("SDRAM cycle time "); |
854 | print_ddr2_tcyc (data[9]); | |
0df6b844 LJ |
855 | break; |
856 | default: | |
632de067 LJ |
857 | printf ("SDRAM cycle time %d.%d ns\n", |
858 | (data[9] >> 4) & 0x0F, data[9] & 0x0F); | |
0df6b844 LJ |
859 | break; |
860 | } | |
861 | ||
862 | switch (type) { | |
863 | case DDR2: | |
632de067 LJ |
864 | printf ("SDRAM access time 0.%d%d ns\n", |
865 | (data[10] >> 4) & 0x0F, data[10] & 0x0F); | |
0df6b844 LJ |
866 | break; |
867 | default: | |
632de067 LJ |
868 | printf ("SDRAM access time %d.%d ns\n", |
869 | (data[10] >> 4) & 0x0F, data[10] & 0x0F); | |
0df6b844 LJ |
870 | break; |
871 | } | |
872 | ||
4b9206ed | 873 | puts ("EDC configuration "); |
632de067 | 874 | switch (data[11]) { |
4b9206ed WD |
875 | case 0: puts ("None\n"); break; |
876 | case 1: puts ("Parity\n"); break; | |
877 | case 2: puts ("ECC\n"); break; | |
878 | default: puts ("unknown\n"); break; | |
81a8824f | 879 | } |
632de067 | 880 | |
e857a5bd | 881 | if ((data[12] & 0x80) == 0) |
4b9206ed | 882 | puts ("No self refresh, rate "); |
e857a5bd | 883 | else |
4b9206ed | 884 | puts ("Self refresh, rate "); |
632de067 | 885 | |
81a8824f | 886 | switch(data[12] & 0x7F) { |
632de067 LJ |
887 | case 0: puts ("15.625 us\n"); break; |
888 | case 1: puts ("3.9 us\n"); break; | |
889 | case 2: puts ("7.8 us\n"); break; | |
890 | case 3: puts ("31.3 us\n"); break; | |
891 | case 4: puts ("62.5 us\n"); break; | |
892 | case 5: puts ("125 us\n"); break; | |
4b9206ed | 893 | default: puts ("unknown\n"); break; |
81a8824f | 894 | } |
0df6b844 LJ |
895 | |
896 | switch (type) { | |
897 | case DDR2: | |
632de067 | 898 | printf ("SDRAM width (primary) %d\n", data[13]); |
0df6b844 LJ |
899 | break; |
900 | default: | |
632de067 | 901 | printf ("SDRAM width (primary) %d\n", data[13] & 0x7F); |
0df6b844 | 902 | if ((data[13] & 0x80) != 0) { |
632de067 LJ |
903 | printf (" (second bank) %d\n", |
904 | 2 * (data[13] & 0x7F)); | |
0df6b844 LJ |
905 | } |
906 | break; | |
907 | } | |
908 | ||
909 | switch (type) { | |
910 | case DDR2: | |
911 | if (data[14] != 0) | |
632de067 | 912 | printf ("EDC width %d\n", data[14]); |
0df6b844 LJ |
913 | break; |
914 | default: | |
915 | if (data[14] != 0) { | |
632de067 LJ |
916 | printf ("EDC width %d\n", |
917 | data[14] & 0x7F); | |
0df6b844 LJ |
918 | |
919 | if ((data[14] & 0x80) != 0) { | |
632de067 LJ |
920 | printf (" (second bank) %d\n", |
921 | 2 * (data[14] & 0x7F)); | |
0df6b844 LJ |
922 | } |
923 | } | |
924 | break; | |
81a8824f | 925 | } |
0df6b844 | 926 | |
632de067 LJ |
927 | if (DDR2 != type) { |
928 | printf ("Min clock delay, back-to-back random column addresses " | |
929 | "%d\n", data[15]); | |
0df6b844 LJ |
930 | } |
931 | ||
4b9206ed WD |
932 | puts ("Burst length(s) "); |
933 | if (data[16] & 0x80) puts (" Page"); | |
934 | if (data[16] & 0x08) puts (" 8"); | |
935 | if (data[16] & 0x04) puts (" 4"); | |
936 | if (data[16] & 0x02) puts (" 2"); | |
937 | if (data[16] & 0x01) puts (" 1"); | |
938 | putc ('\n'); | |
632de067 | 939 | printf ("Number of banks %d\n", data[17]); |
0df6b844 LJ |
940 | |
941 | switch (type) { | |
942 | case DDR2: | |
943 | puts ("CAS latency(s) "); | |
632de067 | 944 | decode_bits (data[18], decode_CAS_DDR2, 0); |
0df6b844 LJ |
945 | putc ('\n'); |
946 | break; | |
947 | default: | |
948 | puts ("CAS latency(s) "); | |
632de067 | 949 | decode_bits (data[18], decode_CAS_default, 0); |
0df6b844 LJ |
950 | putc ('\n'); |
951 | break; | |
952 | } | |
953 | ||
954 | if (DDR2 != type) { | |
955 | puts ("CS latency(s) "); | |
632de067 | 956 | decode_bits (data[19], decode_CS_WE_default, 0); |
0df6b844 LJ |
957 | putc ('\n'); |
958 | } | |
959 | ||
960 | if (DDR2 != type) { | |
961 | puts ("WE latency(s) "); | |
632de067 | 962 | decode_bits (data[20], decode_CS_WE_default, 0); |
0df6b844 LJ |
963 | putc ('\n'); |
964 | } | |
965 | ||
966 | switch (type) { | |
967 | case DDR2: | |
968 | puts ("Module attributes:\n"); | |
969 | if (data[21] & 0x80) | |
970 | puts (" TBD (bit 7)\n"); | |
971 | if (data[21] & 0x40) | |
972 | puts (" Analysis probe installed\n"); | |
973 | if (data[21] & 0x20) | |
974 | puts (" TBD (bit 5)\n"); | |
975 | if (data[21] & 0x10) | |
976 | puts (" FET switch external enable\n"); | |
632de067 | 977 | printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03); |
0df6b844 | 978 | if (data[20] & 0x11) { |
632de067 LJ |
979 | printf (" %d active registers on DIMM\n", |
980 | (data[21] & 0x03) + 1); | |
0df6b844 LJ |
981 | } |
982 | break; | |
983 | default: | |
984 | puts ("Module attributes:\n"); | |
985 | if (!data[21]) | |
986 | puts (" (none)\n"); | |
632de067 LJ |
987 | else |
988 | decode_bits (data[21], decode_byte21_default, 0); | |
0df6b844 LJ |
989 | break; |
990 | } | |
991 | ||
992 | switch (type) { | |
993 | case DDR2: | |
632de067 | 994 | decode_bits (data[22], decode_byte22_DDR2, 0); |
0df6b844 LJ |
995 | break; |
996 | default: | |
997 | puts ("Device attributes:\n"); | |
998 | if (data[22] & 0x80) puts (" TBD (bit 7)\n"); | |
999 | if (data[22] & 0x40) puts (" TBD (bit 6)\n"); | |
1000 | if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n"); | |
1001 | else puts (" Upper Vcc tolerance 10%\n"); | |
1002 | if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n"); | |
1003 | else puts (" Lower Vcc tolerance 10%\n"); | |
1004 | if (data[22] & 0x08) puts (" Supports write1/read burst\n"); | |
1005 | if (data[22] & 0x04) puts (" Supports precharge all\n"); | |
1006 | if (data[22] & 0x02) puts (" Supports auto precharge\n"); | |
1007 | if (data[22] & 0x01) puts (" Supports early RAS# precharge\n"); | |
1008 | break; | |
1009 | } | |
1010 | ||
1011 | switch (type) { | |
1012 | case DDR2: | |
632de067 LJ |
1013 | printf ("SDRAM cycle time (2nd highest CAS latency) "); |
1014 | print_ddr2_tcyc (data[23]); | |
0df6b844 LJ |
1015 | break; |
1016 | default: | |
632de067 LJ |
1017 | printf ("SDRAM cycle time (2nd highest CAS latency) %d." |
1018 | "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F); | |
0df6b844 LJ |
1019 | break; |
1020 | } | |
1021 | ||
1022 | switch (type) { | |
1023 | case DDR2: | |
632de067 LJ |
1024 | printf ("SDRAM access from clock (2nd highest CAS latency) 0." |
1025 | "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F); | |
0df6b844 LJ |
1026 | break; |
1027 | default: | |
632de067 LJ |
1028 | printf ("SDRAM access from clock (2nd highest CAS latency) %d." |
1029 | "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F); | |
0df6b844 LJ |
1030 | break; |
1031 | } | |
1032 | ||
1033 | switch (type) { | |
1034 | case DDR2: | |
632de067 LJ |
1035 | printf ("SDRAM cycle time (3rd highest CAS latency) "); |
1036 | print_ddr2_tcyc (data[25]); | |
0df6b844 LJ |
1037 | break; |
1038 | default: | |
632de067 LJ |
1039 | printf ("SDRAM cycle time (3rd highest CAS latency) %d." |
1040 | "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F); | |
0df6b844 LJ |
1041 | break; |
1042 | } | |
1043 | ||
1044 | switch (type) { | |
1045 | case DDR2: | |
632de067 LJ |
1046 | printf ("SDRAM access from clock (3rd highest CAS latency) 0." |
1047 | "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F); | |
0df6b844 LJ |
1048 | break; |
1049 | default: | |
632de067 LJ |
1050 | printf ("SDRAM access from clock (3rd highest CAS latency) %d." |
1051 | "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F); | |
0df6b844 LJ |
1052 | break; |
1053 | } | |
1054 | ||
1055 | switch (type) { | |
1056 | case DDR2: | |
632de067 LJ |
1057 | printf ("Minimum row precharge %d.%02d ns\n", |
1058 | (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03)); | |
0df6b844 LJ |
1059 | break; |
1060 | default: | |
632de067 | 1061 | printf ("Minimum row precharge %d ns\n", data[27]); |
0df6b844 LJ |
1062 | break; |
1063 | } | |
1064 | ||
1065 | switch (type) { | |
1066 | case DDR2: | |
632de067 LJ |
1067 | printf ("Row active to row active min %d.%02d ns\n", |
1068 | (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03)); | |
0df6b844 LJ |
1069 | break; |
1070 | default: | |
632de067 | 1071 | printf ("Row active to row active min %d ns\n", data[28]); |
0df6b844 LJ |
1072 | break; |
1073 | } | |
1074 | ||
1075 | switch (type) { | |
1076 | case DDR2: | |
632de067 LJ |
1077 | printf ("RAS to CAS delay min %d.%02d ns\n", |
1078 | (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03)); | |
0df6b844 LJ |
1079 | break; |
1080 | default: | |
632de067 | 1081 | printf ("RAS to CAS delay min %d ns\n", data[29]); |
0df6b844 LJ |
1082 | break; |
1083 | } | |
1084 | ||
632de067 | 1085 | printf ("Minimum RAS pulse width %d ns\n", data[30]); |
0df6b844 LJ |
1086 | |
1087 | switch (type) { | |
1088 | case DDR2: | |
632de067 LJ |
1089 | puts ("Density of each row "); |
1090 | decode_bits (data[31], decode_row_density_DDR2, 1); | |
1091 | putc ('\n'); | |
0df6b844 LJ |
1092 | break; |
1093 | default: | |
632de067 LJ |
1094 | puts ("Density of each row "); |
1095 | decode_bits (data[31], decode_row_density_default, 1); | |
1096 | putc ('\n'); | |
0df6b844 LJ |
1097 | break; |
1098 | } | |
1099 | ||
1100 | switch (type) { | |
1101 | case DDR2: | |
632de067 | 1102 | puts ("Command and Address setup "); |
0df6b844 | 1103 | if (data[32] >= 0xA0) { |
632de067 LJ |
1104 | printf ("1.%d%d ns\n", |
1105 | ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F); | |
0df6b844 | 1106 | } else { |
632de067 LJ |
1107 | printf ("0.%d%d ns\n", |
1108 | ((data[32] >> 4) & 0x0F), data[32] & 0x0F); | |
0df6b844 LJ |
1109 | } |
1110 | break; | |
1111 | default: | |
632de067 LJ |
1112 | printf ("Command and Address setup %c%d.%d ns\n", |
1113 | (data[32] & 0x80) ? '-' : '+', | |
1114 | (data[32] >> 4) & 0x07, data[32] & 0x0F); | |
0df6b844 LJ |
1115 | break; |
1116 | } | |
1117 | ||
1118 | switch (type) { | |
1119 | case DDR2: | |
632de067 | 1120 | puts ("Command and Address hold "); |
0df6b844 | 1121 | if (data[33] >= 0xA0) { |
632de067 LJ |
1122 | printf ("1.%d%d ns\n", |
1123 | ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F); | |
0df6b844 | 1124 | } else { |
632de067 LJ |
1125 | printf ("0.%d%d ns\n", |
1126 | ((data[33] >> 4) & 0x0F), data[33] & 0x0F); | |
0df6b844 LJ |
1127 | } |
1128 | break; | |
1129 | default: | |
632de067 LJ |
1130 | printf ("Command and Address hold %c%d.%d ns\n", |
1131 | (data[33] & 0x80) ? '-' : '+', | |
1132 | (data[33] >> 4) & 0x07, data[33] & 0x0F); | |
0df6b844 LJ |
1133 | break; |
1134 | } | |
1135 | ||
1136 | switch (type) { | |
1137 | case DDR2: | |
632de067 LJ |
1138 | printf ("Data signal input setup 0.%d%d ns\n", |
1139 | (data[34] >> 4) & 0x0F, data[34] & 0x0F); | |
0df6b844 LJ |
1140 | break; |
1141 | default: | |
632de067 LJ |
1142 | printf ("Data signal input setup %c%d.%d ns\n", |
1143 | (data[34] & 0x80) ? '-' : '+', | |
1144 | (data[34] >> 4) & 0x07, data[34] & 0x0F); | |
0df6b844 LJ |
1145 | break; |
1146 | } | |
1147 | ||
1148 | switch (type) { | |
1149 | case DDR2: | |
632de067 LJ |
1150 | printf ("Data signal input hold 0.%d%d ns\n", |
1151 | (data[35] >> 4) & 0x0F, data[35] & 0x0F); | |
0df6b844 LJ |
1152 | break; |
1153 | default: | |
632de067 LJ |
1154 | printf ("Data signal input hold %c%d.%d ns\n", |
1155 | (data[35] & 0x80) ? '-' : '+', | |
1156 | (data[35] >> 4) & 0x07, data[35] & 0x0F); | |
0df6b844 LJ |
1157 | break; |
1158 | } | |
1159 | ||
4b9206ed | 1160 | puts ("Manufacturer's JEDEC ID "); |
e857a5bd | 1161 | for (j = 64; j <= 71; j++) |
632de067 | 1162 | printf ("%02X ", data[j]); |
4b9206ed | 1163 | putc ('\n'); |
632de067 | 1164 | printf ("Manufacturing Location %02X\n", data[72]); |
4b9206ed | 1165 | puts ("Manufacturer's Part Number "); |
e857a5bd | 1166 | for (j = 73; j <= 90; j++) |
632de067 | 1167 | printf ("%02X ", data[j]); |
4b9206ed | 1168 | putc ('\n'); |
632de067 LJ |
1169 | printf ("Revision Code %02X %02X\n", data[91], data[92]); |
1170 | printf ("Manufacturing Date %02X %02X\n", data[93], data[94]); | |
4b9206ed | 1171 | puts ("Assembly Serial Number "); |
e857a5bd | 1172 | for (j = 95; j <= 98; j++) |
632de067 | 1173 | printf ("%02X ", data[j]); |
4b9206ed | 1174 | putc ('\n'); |
81a8824f | 1175 | |
0df6b844 | 1176 | if (DDR2 != type) { |
632de067 LJ |
1177 | printf ("Speed rating PC%d\n", |
1178 | data[126] == 0x66 ? 66 : data[126]); | |
0df6b844 | 1179 | } |
81a8824f WD |
1180 | return 0; |
1181 | } | |
90253178 | 1182 | #endif |
81a8824f | 1183 | |
bb99ad6d BW |
1184 | #if defined(CONFIG_I2C_CMD_TREE) |
1185 | #if defined(CONFIG_I2C_MULTI_BUS) | |
1186 | int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) | |
1187 | { | |
1188 | int bus_idx, ret=0; | |
1189 | ||
e857a5bd TT |
1190 | if (argc == 1) |
1191 | /* querying current setting */ | |
bb99ad6d | 1192 | printf("Current bus is %d\n", i2c_get_bus_num()); |
e857a5bd | 1193 | else { |
bb99ad6d BW |
1194 | bus_idx = simple_strtoul(argv[1], NULL, 10); |
1195 | printf("Setting bus to %d\n", bus_idx); | |
1196 | ret = i2c_set_bus_num(bus_idx); | |
e857a5bd | 1197 | if (ret) |
bb99ad6d | 1198 | printf("Failure changing bus number (%d)\n", ret); |
bb99ad6d BW |
1199 | } |
1200 | return ret; | |
1201 | } | |
1202 | #endif /* CONFIG_I2C_MULTI_BUS */ | |
1203 | ||
1204 | int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) | |
1205 | { | |
1206 | int speed, ret=0; | |
1207 | ||
e857a5bd TT |
1208 | if (argc == 1) |
1209 | /* querying current speed */ | |
bb99ad6d | 1210 | printf("Current bus speed=%d\n", i2c_get_bus_speed()); |
e857a5bd | 1211 | else { |
bb99ad6d BW |
1212 | speed = simple_strtoul(argv[1], NULL, 10); |
1213 | printf("Setting bus speed to %d Hz\n", speed); | |
1214 | ret = i2c_set_bus_speed(speed); | |
e857a5bd | 1215 | if (ret) |
bb99ad6d | 1216 | printf("Failure changing bus speed (%d)\n", ret); |
bb99ad6d BW |
1217 | } |
1218 | return ret; | |
1219 | } | |
1220 | ||
1221 | int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) | |
1222 | { | |
1223 | #if defined(CONFIG_I2C_MULTI_BUS) | |
e857a5bd | 1224 | if (!strncmp(argv[1], "de", 2)) |
bb99ad6d | 1225 | return do_i2c_bus_num(cmdtp, flag, --argc, ++argv); |
bb99ad6d | 1226 | #endif /* CONFIG_I2C_MULTI_BUS */ |
e857a5bd | 1227 | if (!strncmp(argv[1], "sp", 2)) |
bb99ad6d | 1228 | return do_i2c_bus_speed(cmdtp, flag, --argc, ++argv); |
e857a5bd | 1229 | if (!strncmp(argv[1], "md", 2)) |
bb99ad6d | 1230 | return do_i2c_md(cmdtp, flag, --argc, ++argv); |
e857a5bd | 1231 | if (!strncmp(argv[1], "mm", 2)) |
bb99ad6d | 1232 | return do_i2c_mm(cmdtp, flag, --argc, ++argv); |
e857a5bd | 1233 | if (!strncmp(argv[1], "mw", 2)) |
bb99ad6d | 1234 | return do_i2c_mw(cmdtp, flag, --argc, ++argv); |
e857a5bd | 1235 | if (!strncmp(argv[1], "nm", 2)) |
bb99ad6d | 1236 | return do_i2c_nm(cmdtp, flag, --argc, ++argv); |
e857a5bd | 1237 | if (!strncmp(argv[1], "cr", 2)) |
bb99ad6d | 1238 | return do_i2c_crc(cmdtp, flag, --argc, ++argv); |
e857a5bd | 1239 | if (!strncmp(argv[1], "pr", 2)) |
bb99ad6d | 1240 | return do_i2c_probe(cmdtp, flag, --argc, ++argv); |
e857a5bd | 1241 | if (!strncmp(argv[1], "lo", 2)) |
bb99ad6d | 1242 | return do_i2c_loop(cmdtp, flag, --argc, ++argv); |
c76fe474 | 1243 | #if defined(CONFIG_CMD_SDRAM) |
e857a5bd | 1244 | if (!strncmp(argv[1], "sd", 2)) |
bb99ad6d | 1245 | return do_sdram(cmdtp, flag, --argc, ++argv); |
90253178 | 1246 | #endif |
bb99ad6d | 1247 | else |
bb99ad6d | 1248 | printf ("Usage:\n%s\n", cmdtp->usage); |
bb99ad6d BW |
1249 | return 0; |
1250 | } | |
1251 | #endif /* CONFIG_I2C_CMD_TREE */ | |
8bde7f77 WD |
1252 | |
1253 | /***************************************************/ | |
1254 | ||
d9fc7032 MF |
1255 | #if defined(CONFIG_I2C_CMD_TREE) |
1256 | U_BOOT_CMD( | |
1257 | i2c, 6, 1, do_i2c, | |
53677ef1 | 1258 | "i2c - I2C sub-system\n", |
d9fc7032 MF |
1259 | #if defined(CONFIG_I2C_MULTI_BUS) |
1260 | "dev [dev] - show or set current I2C bus\n" | |
1261 | #endif /* CONFIG_I2C_MULTI_BUS */ | |
1262 | "i2c speed [speed] - show or set I2C bus speed\n" | |
1263 | "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n" | |
1264 | "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n" | |
1265 | "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n" | |
1266 | "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n" | |
1267 | "i2c crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n" | |
1268 | "i2c probe - show devices on the I2C bus\n" | |
1269 | "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n" | |
c76fe474 | 1270 | #if defined(CONFIG_CMD_SDRAM) |
d9fc7032 | 1271 | "i2c sdram chip - print SDRAM configuration information\n" |
90253178 | 1272 | #endif |
d9fc7032 | 1273 | ); |
0c75c9d8 | 1274 | #endif /* CONFIG_I2C_CMD_TREE */ |
0d498393 WD |
1275 | U_BOOT_CMD( |
1276 | imd, 4, 1, do_i2c_md, \ | |
8bde7f77 WD |
1277 | "imd - i2c memory display\n", \ |
1278 | "chip address[.0, .1, .2] [# of objects]\n - i2c memory display\n" \ | |
1279 | ); | |
1280 | ||
0d498393 | 1281 | U_BOOT_CMD( |
53677ef1 | 1282 | imm, 3, 1, do_i2c_mm, |
8bde7f77 WD |
1283 | "imm - i2c memory modify (auto-incrementing)\n", |
1284 | "chip address[.0, .1, .2]\n" | |
1285 | " - memory modify, auto increment address\n" | |
1286 | ); | |
0d498393 WD |
1287 | U_BOOT_CMD( |
1288 | inm, 3, 1, do_i2c_nm, | |
8bde7f77 WD |
1289 | "inm - memory modify (constant address)\n", |
1290 | "chip address[.0, .1, .2]\n - memory modify, read and keep address\n" | |
1291 | ); | |
1292 | ||
0d498393 WD |
1293 | U_BOOT_CMD( |
1294 | imw, 5, 1, do_i2c_mw, | |
8bde7f77 WD |
1295 | "imw - memory write (fill)\n", |
1296 | "chip address[.0, .1, .2] value [count]\n - memory write (fill)\n" | |
1297 | ); | |
1298 | ||
0d498393 WD |
1299 | U_BOOT_CMD( |
1300 | icrc32, 5, 1, do_i2c_crc, | |
8bde7f77 WD |
1301 | "icrc32 - checksum calculation\n", |
1302 | "chip address[.0, .1, .2] count\n - compute CRC32 checksum\n" | |
1303 | ); | |
1304 | ||
0d498393 WD |
1305 | U_BOOT_CMD( |
1306 | iprobe, 1, 1, do_i2c_probe, | |
8bde7f77 WD |
1307 | "iprobe - probe to discover valid I2C chip addresses\n", |
1308 | "\n -discover valid I2C chip addresses\n" | |
1309 | ); | |
1310 | ||
1311 | /* | |
1312 | * Require full name for "iloop" because it is an infinite loop! | |
1313 | */ | |
0d498393 WD |
1314 | U_BOOT_CMD( |
1315 | iloop, 5, 1, do_i2c_loop, | |
8bde7f77 WD |
1316 | "iloop - infinite loop on address range\n", |
1317 | "chip address[.0, .1, .2] [# of objects]\n" | |
1318 | " - loop, reading a set of addresses\n" | |
1319 | ); | |
1320 | ||
c76fe474 | 1321 | #if defined(CONFIG_CMD_SDRAM) |
0d498393 WD |
1322 | U_BOOT_CMD( |
1323 | isdram, 2, 1, do_sdram, | |
8bde7f77 WD |
1324 | "isdram - print SDRAM configuration information\n", |
1325 | "chip\n - print SDRAM configuration information\n" | |
1326 | " (valid chip values 50..57)\n" | |
1327 | ); | |
1328 | #endif |