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81a8824f WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * I2C Functions similar to the standard memory functions. | |
26 | * | |
27 | * There are several parameters in many of the commands that bear further | |
28 | * explanations: | |
29 | * | |
81a8824f WD |
30 | * {i2c_chip} is the I2C chip address (the first byte sent on the bus). |
31 | * Each I2C chip on the bus has a unique address. On the I2C data bus, | |
32 | * the address is the upper seven bits and the LSB is the "read/write" | |
33 | * bit. Note that the {i2c_chip} address specified on the command | |
34 | * line is not shifted up: e.g. a typical EEPROM memory chip may have | |
35 | * an I2C address of 0x50, but the data put on the bus will be 0xA0 | |
36 | * for write and 0xA1 for read. This "non shifted" address notation | |
37 | * matches at least half of the data sheets :-/. | |
38 | * | |
39 | * {addr} is the address (or offset) within the chip. Small memory | |
40 | * chips have 8 bit addresses. Large memory chips have 16 bit | |
41 | * addresses. Other memory chips have 9, 10, or 11 bit addresses. | |
42 | * Many non-memory chips have multiple registers and {addr} is used | |
43 | * as the register index. Some non-memory chips have only one register | |
44 | * and therefore don't need any {addr} parameter. | |
45 | * | |
46 | * The default {addr} parameter is one byte (.1) which works well for | |
47 | * memories and registers with 8 bits of address space. | |
48 | * | |
49 | * You can specify the length of the {addr} field with the optional .0, | |
50 | * .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are | |
51 | * manipulating a single register device which doesn't use an address | |
52 | * field, use "0.0" for the address and the ".0" length field will | |
53 | * suppress the address in the I2C data stream. This also works for | |
54 | * successive reads using the I2C auto-incrementing memory pointer. | |
55 | * | |
56 | * If you are manipulating a large memory with 2-byte addresses, use | |
57 | * the .2 address modifier, e.g. 210.2 addresses location 528 (decimal). | |
58 | * | |
59 | * Then there are the unfortunate memory chips that spill the most | |
60 | * significant 1, 2, or 3 bits of address into the chip address byte. | |
61 | * This effectively makes one chip (logically) look like 2, 4, or | |
62 | * 8 chips. This is handled (awkwardly) by #defining | |
6d0f6bcf | 63 | * CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the |
81a8824f WD |
64 | * {addr} field (since .1 is the default, it doesn't actually have to |
65 | * be specified). Examples: given a memory chip at I2C chip address | |
66 | * 0x50, the following would happen... | |
0f89c54b | 67 | * i2c md 50 0 10 display 16 bytes starting at 0x000 |
81a8824f | 68 | * On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd> |
0f89c54b | 69 | * i2c md 50 100 10 display 16 bytes starting at 0x100 |
81a8824f | 70 | * On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd> |
0f89c54b | 71 | * i2c md 50 210 10 display 16 bytes starting at 0x210 |
81a8824f WD |
72 | * On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd> |
73 | * This is awfully ugly. It would be nice if someone would think up | |
74 | * a better way of handling this. | |
75 | * | |
76 | * Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de). | |
77 | */ | |
78 | ||
79 | #include <common.h> | |
80 | #include <command.h> | |
67b23a32 | 81 | #include <environment.h> |
81a8824f | 82 | #include <i2c.h> |
67b23a32 | 83 | #include <malloc.h> |
81a8824f WD |
84 | #include <asm/byteorder.h> |
85 | ||
81a8824f WD |
86 | /* Display values from last command. |
87 | * Memory modify remembered values are different from display memory. | |
88 | */ | |
89 | static uchar i2c_dp_last_chip; | |
90 | static uint i2c_dp_last_addr; | |
91 | static uint i2c_dp_last_alen; | |
92 | static uint i2c_dp_last_length = 0x10; | |
93 | ||
94 | static uchar i2c_mm_last_chip; | |
95 | static uint i2c_mm_last_addr; | |
96 | static uint i2c_mm_last_alen; | |
97 | ||
bb99ad6d BW |
98 | /* If only one I2C bus is present, the list of devices to ignore when |
99 | * the probe command is issued is represented by a 1D array of addresses. | |
100 | * When multiple buses are present, the list is an array of bus-address | |
101 | * pairs. The following macros take care of this */ | |
102 | ||
6d0f6bcf | 103 | #if defined(CONFIG_SYS_I2C_NOPROBES) |
bb99ad6d BW |
104 | #if defined(CONFIG_I2C_MULTI_BUS) |
105 | static struct | |
106 | { | |
107 | uchar bus; | |
108 | uchar addr; | |
6d0f6bcf | 109 | } i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES; |
bb99ad6d BW |
110 | #define GET_BUS_NUM i2c_get_bus_num() |
111 | #define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b)) | |
112 | #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a)) | |
113 | #define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr | |
114 | #else /* single bus */ | |
6d0f6bcf | 115 | static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES; |
bb99ad6d BW |
116 | #define GET_BUS_NUM 0 |
117 | #define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */ | |
118 | #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a)) | |
119 | #define NO_PROBE_ADDR(i) i2c_no_probes[(i)] | |
120 | #endif /* CONFIG_MULTI_BUS */ | |
121 | ||
122 | #define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0])) | |
81a8824f WD |
123 | #endif |
124 | ||
67b23a32 HS |
125 | #if defined(CONFIG_I2C_MUX) |
126 | static I2C_MUX_DEVICE *i2c_mux_devices = NULL; | |
6d0f6bcf | 127 | static int i2c_mux_busid = CONFIG_SYS_MAX_I2C_BUS; |
67b23a32 HS |
128 | |
129 | DECLARE_GLOBAL_DATA_PTR; | |
130 | ||
131 | #endif | |
132 | ||
a266fe95 FM |
133 | #define DISP_LINE_LEN 16 |
134 | ||
655b34a7 PT |
135 | /* TODO: Implement architecture-specific get/set functions */ |
136 | unsigned int __def_i2c_get_bus_speed(void) | |
137 | { | |
138 | return CONFIG_SYS_I2C_SPEED; | |
139 | } | |
140 | unsigned int i2c_get_bus_speed(void) | |
141 | __attribute__((weak, alias("__def_i2c_get_bus_speed"))); | |
142 | ||
143 | int __def_i2c_set_bus_speed(unsigned int speed) | |
144 | { | |
145 | if (speed != CONFIG_SYS_I2C_SPEED) | |
146 | return -1; | |
147 | ||
148 | return 0; | |
149 | } | |
150 | int i2c_set_bus_speed(unsigned int) | |
151 | __attribute__((weak, alias("__def_i2c_set_bus_speed"))); | |
152 | ||
2c0dc990 FM |
153 | /* |
154 | * get_alen: small parser helper function to get address length | |
155 | * returns the address length,or 0 on error | |
156 | */ | |
157 | static uint get_alen(char *arg) | |
158 | { | |
159 | int j; | |
160 | int alen; | |
161 | ||
162 | alen = 1; | |
163 | for (j = 0; j < 8; j++) { | |
164 | if (arg[j] == '.') { | |
165 | alen = arg[j+1] - '0'; | |
166 | if (alen > 3) { | |
167 | return 0; | |
168 | } | |
169 | break; | |
170 | } else if (arg[j] == '\0') | |
171 | break; | |
172 | } | |
173 | return alen; | |
174 | } | |
175 | ||
652e5354 FM |
176 | /* |
177 | * Syntax: | |
178 | * i2c read {i2c_chip} {devaddr}{.0, .1, .2} {len} {memaddr} | |
179 | */ | |
180 | ||
54841ab5 | 181 | static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
652e5354 FM |
182 | { |
183 | u_char chip; | |
184 | uint devaddr, alen, length; | |
185 | u_char *memaddr; | |
652e5354 | 186 | |
47e26b1b WD |
187 | if (argc != 5) |
188 | return cmd_usage(cmdtp); | |
652e5354 FM |
189 | |
190 | /* | |
191 | * I2C chip address | |
192 | */ | |
193 | chip = simple_strtoul(argv[1], NULL, 16); | |
194 | ||
195 | /* | |
196 | * I2C data address within the chip. This can be 1 or | |
197 | * 2 bytes long. Some day it might be 3 bytes long :-). | |
198 | */ | |
199 | devaddr = simple_strtoul(argv[2], NULL, 16); | |
2c0dc990 | 200 | alen = get_alen(argv[2]); |
47e26b1b WD |
201 | if (alen == 0) |
202 | return cmd_usage(cmdtp); | |
652e5354 FM |
203 | |
204 | /* | |
205 | * Length is the number of objects, not number of bytes. | |
206 | */ | |
207 | length = simple_strtoul(argv[3], NULL, 16); | |
208 | ||
209 | /* | |
210 | * memaddr is the address where to store things in memory | |
211 | */ | |
212 | memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16); | |
213 | ||
214 | if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) { | |
215 | puts ("Error reading the chip.\n"); | |
216 | return 1; | |
217 | } | |
218 | return 0; | |
219 | } | |
220 | ||
4a8cf338 FM |
221 | /* |
222 | * Syntax: | |
223 | * i2c md {i2c_chip} {addr}{.0, .1, .2} {len} | |
224 | */ | |
54841ab5 | 225 | static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
81a8824f WD |
226 | { |
227 | u_char chip; | |
228 | uint addr, alen, length; | |
229 | int j, nbytes, linebytes; | |
230 | ||
231 | /* We use the last specified parameters, unless new ones are | |
232 | * entered. | |
233 | */ | |
234 | chip = i2c_dp_last_chip; | |
235 | addr = i2c_dp_last_addr; | |
236 | alen = i2c_dp_last_alen; | |
237 | length = i2c_dp_last_length; | |
238 | ||
47e26b1b WD |
239 | if (argc < 3) |
240 | return cmd_usage(cmdtp); | |
81a8824f WD |
241 | |
242 | if ((flag & CMD_FLAG_REPEAT) == 0) { | |
243 | /* | |
244 | * New command specified. | |
245 | */ | |
81a8824f WD |
246 | |
247 | /* | |
248 | * I2C chip address | |
249 | */ | |
250 | chip = simple_strtoul(argv[1], NULL, 16); | |
251 | ||
252 | /* | |
253 | * I2C data address within the chip. This can be 1 or | |
254 | * 2 bytes long. Some day it might be 3 bytes long :-). | |
255 | */ | |
256 | addr = simple_strtoul(argv[2], NULL, 16); | |
2c0dc990 | 257 | alen = get_alen(argv[2]); |
47e26b1b WD |
258 | if (alen == 0) |
259 | return cmd_usage(cmdtp); | |
81a8824f WD |
260 | |
261 | /* | |
262 | * If another parameter, it is the length to display. | |
263 | * Length is the number of objects, not number of bytes. | |
264 | */ | |
265 | if (argc > 3) | |
266 | length = simple_strtoul(argv[3], NULL, 16); | |
267 | } | |
268 | ||
269 | /* | |
270 | * Print the lines. | |
271 | * | |
272 | * We buffer all read data, so we can make sure data is read only | |
273 | * once. | |
274 | */ | |
275 | nbytes = length; | |
276 | do { | |
277 | unsigned char linebuf[DISP_LINE_LEN]; | |
278 | unsigned char *cp; | |
279 | ||
280 | linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; | |
281 | ||
e857a5bd | 282 | if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0) |
4b9206ed | 283 | puts ("Error reading the chip.\n"); |
e857a5bd | 284 | else { |
81a8824f WD |
285 | printf("%04x:", addr); |
286 | cp = linebuf; | |
287 | for (j=0; j<linebytes; j++) { | |
288 | printf(" %02x", *cp++); | |
289 | addr++; | |
290 | } | |
4b9206ed | 291 | puts (" "); |
81a8824f WD |
292 | cp = linebuf; |
293 | for (j=0; j<linebytes; j++) { | |
294 | if ((*cp < 0x20) || (*cp > 0x7e)) | |
4b9206ed | 295 | puts ("."); |
81a8824f WD |
296 | else |
297 | printf("%c", *cp); | |
298 | cp++; | |
299 | } | |
4b9206ed | 300 | putc ('\n'); |
81a8824f WD |
301 | } |
302 | nbytes -= linebytes; | |
303 | } while (nbytes > 0); | |
304 | ||
305 | i2c_dp_last_chip = chip; | |
306 | i2c_dp_last_addr = addr; | |
307 | i2c_dp_last_alen = alen; | |
308 | i2c_dp_last_length = length; | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
81a8824f WD |
313 | |
314 | /* Write (fill) memory | |
315 | * | |
316 | * Syntax: | |
0f89c54b | 317 | * i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}] |
81a8824f | 318 | */ |
54841ab5 | 319 | static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
81a8824f WD |
320 | { |
321 | uchar chip; | |
322 | ulong addr; | |
323 | uint alen; | |
324 | uchar byte; | |
325 | int count; | |
81a8824f | 326 | |
47e26b1b WD |
327 | if ((argc < 4) || (argc > 5)) |
328 | return cmd_usage(cmdtp); | |
81a8824f WD |
329 | |
330 | /* | |
53677ef1 WD |
331 | * Chip is always specified. |
332 | */ | |
81a8824f WD |
333 | chip = simple_strtoul(argv[1], NULL, 16); |
334 | ||
335 | /* | |
336 | * Address is always specified. | |
337 | */ | |
338 | addr = simple_strtoul(argv[2], NULL, 16); | |
2c0dc990 | 339 | alen = get_alen(argv[2]); |
47e26b1b WD |
340 | if (alen == 0) |
341 | return cmd_usage(cmdtp); | |
81a8824f WD |
342 | |
343 | /* | |
344 | * Value to write is always specified. | |
345 | */ | |
346 | byte = simple_strtoul(argv[3], NULL, 16); | |
347 | ||
348 | /* | |
349 | * Optional count | |
350 | */ | |
e857a5bd | 351 | if (argc == 5) |
81a8824f | 352 | count = simple_strtoul(argv[4], NULL, 16); |
e857a5bd | 353 | else |
81a8824f | 354 | count = 1; |
81a8824f WD |
355 | |
356 | while (count-- > 0) { | |
e857a5bd | 357 | if (i2c_write(chip, addr++, alen, &byte, 1) != 0) |
4b9206ed | 358 | puts ("Error writing the chip.\n"); |
81a8824f WD |
359 | /* |
360 | * Wait for the write to complete. The write can take | |
361 | * up to 10mSec (we allow a little more time). | |
81a8824f | 362 | */ |
d4f5c728 | 363 | /* |
364 | * No write delay with FRAM devices. | |
365 | */ | |
6d0f6bcf | 366 | #if !defined(CONFIG_SYS_I2C_FRAM) |
81a8824f | 367 | udelay(11000); |
d4f5c728 | 368 | #endif |
81a8824f WD |
369 | } |
370 | ||
371 | return (0); | |
372 | } | |
373 | ||
81a8824f WD |
374 | /* Calculate a CRC on memory |
375 | * | |
376 | * Syntax: | |
0f89c54b | 377 | * i2c crc32 {i2c_chip} {addr}{.0, .1, .2} {count} |
81a8824f | 378 | */ |
54841ab5 | 379 | static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
81a8824f WD |
380 | { |
381 | uchar chip; | |
382 | ulong addr; | |
383 | uint alen; | |
384 | int count; | |
385 | uchar byte; | |
386 | ulong crc; | |
387 | ulong err; | |
81a8824f | 388 | |
47e26b1b WD |
389 | if (argc < 4) |
390 | return cmd_usage(cmdtp); | |
81a8824f WD |
391 | |
392 | /* | |
53677ef1 WD |
393 | * Chip is always specified. |
394 | */ | |
81a8824f WD |
395 | chip = simple_strtoul(argv[1], NULL, 16); |
396 | ||
397 | /* | |
398 | * Address is always specified. | |
399 | */ | |
400 | addr = simple_strtoul(argv[2], NULL, 16); | |
2c0dc990 | 401 | alen = get_alen(argv[2]); |
47e26b1b WD |
402 | if (alen == 0) |
403 | return cmd_usage(cmdtp); | |
81a8824f WD |
404 | |
405 | /* | |
406 | * Count is always specified | |
407 | */ | |
408 | count = simple_strtoul(argv[3], NULL, 16); | |
409 | ||
410 | printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1); | |
411 | /* | |
412 | * CRC a byte at a time. This is going to be slooow, but hey, the | |
413 | * memories are small and slow too so hopefully nobody notices. | |
414 | */ | |
415 | crc = 0; | |
416 | err = 0; | |
e857a5bd TT |
417 | while (count-- > 0) { |
418 | if (i2c_read(chip, addr, alen, &byte, 1) != 0) | |
81a8824f | 419 | err++; |
81a8824f WD |
420 | crc = crc32 (crc, &byte, 1); |
421 | addr++; | |
422 | } | |
e857a5bd | 423 | if (err > 0) |
4b9206ed | 424 | puts ("Error reading the chip,\n"); |
e857a5bd | 425 | else |
81a8824f | 426 | printf ("%08lx\n", crc); |
81a8824f WD |
427 | |
428 | return 0; | |
429 | } | |
430 | ||
81a8824f WD |
431 | /* Modify memory. |
432 | * | |
433 | * Syntax: | |
0f89c54b PT |
434 | * i2c mm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2} |
435 | * i2c nm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2} | |
81a8824f WD |
436 | */ |
437 | ||
438 | static int | |
54841ab5 | 439 | mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[]) |
81a8824f WD |
440 | { |
441 | uchar chip; | |
442 | ulong addr; | |
443 | uint alen; | |
444 | ulong data; | |
445 | int size = 1; | |
446 | int nbytes; | |
81a8824f WD |
447 | extern char console_buffer[]; |
448 | ||
47e26b1b WD |
449 | if (argc != 3) |
450 | return cmd_usage(cmdtp); | |
81a8824f WD |
451 | |
452 | #ifdef CONFIG_BOOT_RETRY_TIME | |
453 | reset_cmd_timeout(); /* got a good command to get here */ | |
454 | #endif | |
455 | /* | |
456 | * We use the last specified parameters, unless new ones are | |
457 | * entered. | |
458 | */ | |
459 | chip = i2c_mm_last_chip; | |
460 | addr = i2c_mm_last_addr; | |
461 | alen = i2c_mm_last_alen; | |
462 | ||
463 | if ((flag & CMD_FLAG_REPEAT) == 0) { | |
464 | /* | |
465 | * New command specified. Check for a size specification. | |
466 | * Defaults to byte if no or incorrect specification. | |
467 | */ | |
468 | size = cmd_get_data_size(argv[0], 1); | |
469 | ||
470 | /* | |
53677ef1 WD |
471 | * Chip is always specified. |
472 | */ | |
81a8824f WD |
473 | chip = simple_strtoul(argv[1], NULL, 16); |
474 | ||
475 | /* | |
476 | * Address is always specified. | |
477 | */ | |
478 | addr = simple_strtoul(argv[2], NULL, 16); | |
2c0dc990 | 479 | alen = get_alen(argv[2]); |
47e26b1b WD |
480 | if (alen == 0) |
481 | return cmd_usage(cmdtp); | |
81a8824f WD |
482 | } |
483 | ||
484 | /* | |
485 | * Print the address, followed by value. Then accept input for | |
486 | * the next value. A non-converted value exits. | |
487 | */ | |
488 | do { | |
489 | printf("%08lx:", addr); | |
e857a5bd | 490 | if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0) |
4b9206ed | 491 | puts ("\nError reading the chip,\n"); |
e857a5bd | 492 | else { |
81a8824f | 493 | data = cpu_to_be32(data); |
e857a5bd | 494 | if (size == 1) |
81a8824f | 495 | printf(" %02lx", (data >> 24) & 0x000000FF); |
e857a5bd | 496 | else if (size == 2) |
81a8824f | 497 | printf(" %04lx", (data >> 16) & 0x0000FFFF); |
e857a5bd | 498 | else |
81a8824f | 499 | printf(" %08lx", data); |
81a8824f WD |
500 | } |
501 | ||
502 | nbytes = readline (" ? "); | |
503 | if (nbytes == 0) { | |
504 | /* | |
505 | * <CR> pressed as only input, don't modify current | |
506 | * location and move to next. | |
507 | */ | |
508 | if (incrflag) | |
509 | addr += size; | |
510 | nbytes = size; | |
511 | #ifdef CONFIG_BOOT_RETRY_TIME | |
512 | reset_cmd_timeout(); /* good enough to not time out */ | |
513 | #endif | |
514 | } | |
515 | #ifdef CONFIG_BOOT_RETRY_TIME | |
e857a5bd | 516 | else if (nbytes == -2) |
81a8824f | 517 | break; /* timed out, exit the command */ |
81a8824f WD |
518 | #endif |
519 | else { | |
520 | char *endp; | |
521 | ||
522 | data = simple_strtoul(console_buffer, &endp, 16); | |
e857a5bd | 523 | if (size == 1) |
81a8824f | 524 | data = data << 24; |
e857a5bd | 525 | else if (size == 2) |
81a8824f | 526 | data = data << 16; |
81a8824f WD |
527 | data = be32_to_cpu(data); |
528 | nbytes = endp - console_buffer; | |
529 | if (nbytes) { | |
530 | #ifdef CONFIG_BOOT_RETRY_TIME | |
531 | /* | |
532 | * good enough to not time out | |
533 | */ | |
534 | reset_cmd_timeout(); | |
535 | #endif | |
e857a5bd | 536 | if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) |
4b9206ed | 537 | puts ("Error writing the chip.\n"); |
6d0f6bcf JCPV |
538 | #ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS |
539 | udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); | |
2535d602 | 540 | #endif |
81a8824f WD |
541 | if (incrflag) |
542 | addr += size; | |
543 | } | |
544 | } | |
545 | } while (nbytes); | |
546 | ||
0800707b PT |
547 | i2c_mm_last_chip = chip; |
548 | i2c_mm_last_addr = addr; | |
549 | i2c_mm_last_alen = alen; | |
81a8824f WD |
550 | |
551 | return 0; | |
552 | } | |
553 | ||
554 | /* | |
555 | * Syntax: | |
0f89c54b | 556 | * i2c probe {addr}{.0, .1, .2} |
81a8824f | 557 | */ |
54841ab5 | 558 | static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
81a8824f WD |
559 | { |
560 | int j; | |
6d0f6bcf | 561 | #if defined(CONFIG_SYS_I2C_NOPROBES) |
81a8824f | 562 | int k, skip; |
bb99ad6d BW |
563 | uchar bus = GET_BUS_NUM; |
564 | #endif /* NOPROBES */ | |
81a8824f | 565 | |
4b9206ed | 566 | puts ("Valid chip addresses:"); |
e857a5bd | 567 | for (j = 0; j < 128; j++) { |
6d0f6bcf | 568 | #if defined(CONFIG_SYS_I2C_NOPROBES) |
81a8824f | 569 | skip = 0; |
e857a5bd TT |
570 | for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) { |
571 | if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) { | |
81a8824f WD |
572 | skip = 1; |
573 | break; | |
574 | } | |
575 | } | |
576 | if (skip) | |
577 | continue; | |
578 | #endif | |
e857a5bd | 579 | if (i2c_probe(j) == 0) |
81a8824f | 580 | printf(" %02X", j); |
81a8824f | 581 | } |
4b9206ed | 582 | putc ('\n'); |
81a8824f | 583 | |
6d0f6bcf | 584 | #if defined(CONFIG_SYS_I2C_NOPROBES) |
81a8824f | 585 | puts ("Excluded chip addresses:"); |
e857a5bd TT |
586 | for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) { |
587 | if (COMPARE_BUS(bus,k)) | |
bb99ad6d BW |
588 | printf(" %02X", NO_PROBE_ADDR(k)); |
589 | } | |
4b9206ed | 590 | putc ('\n'); |
81a8824f WD |
591 | #endif |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
81a8824f WD |
596 | /* |
597 | * Syntax: | |
0f89c54b | 598 | * i2c loop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}] |
81a8824f WD |
599 | * {length} - Number of bytes to read |
600 | * {delay} - A DECIMAL number and defaults to 1000 uSec | |
601 | */ | |
54841ab5 | 602 | static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
81a8824f WD |
603 | { |
604 | u_char chip; | |
605 | ulong alen; | |
606 | uint addr; | |
607 | uint length; | |
608 | u_char bytes[16]; | |
609 | int delay; | |
81a8824f | 610 | |
47e26b1b WD |
611 | if (argc < 3) |
612 | return cmd_usage(cmdtp); | |
81a8824f WD |
613 | |
614 | /* | |
615 | * Chip is always specified. | |
616 | */ | |
617 | chip = simple_strtoul(argv[1], NULL, 16); | |
618 | ||
619 | /* | |
620 | * Address is always specified. | |
621 | */ | |
622 | addr = simple_strtoul(argv[2], NULL, 16); | |
2c0dc990 | 623 | alen = get_alen(argv[2]); |
47e26b1b WD |
624 | if (alen == 0) |
625 | return cmd_usage(cmdtp); | |
81a8824f WD |
626 | |
627 | /* | |
628 | * Length is the number of objects, not number of bytes. | |
629 | */ | |
630 | length = 1; | |
631 | length = simple_strtoul(argv[3], NULL, 16); | |
e857a5bd | 632 | if (length > sizeof(bytes)) |
81a8824f | 633 | length = sizeof(bytes); |
81a8824f WD |
634 | |
635 | /* | |
636 | * The delay time (uSec) is optional. | |
637 | */ | |
638 | delay = 1000; | |
e857a5bd | 639 | if (argc > 3) |
81a8824f | 640 | delay = simple_strtoul(argv[4], NULL, 10); |
81a8824f WD |
641 | /* |
642 | * Run the loop... | |
643 | */ | |
e857a5bd TT |
644 | while (1) { |
645 | if (i2c_read(chip, addr, alen, bytes, length) != 0) | |
4b9206ed | 646 | puts ("Error reading the chip.\n"); |
81a8824f WD |
647 | udelay(delay); |
648 | } | |
649 | ||
650 | /* NOTREACHED */ | |
651 | return 0; | |
652 | } | |
653 | ||
81a8824f WD |
654 | /* |
655 | * The SDRAM command is separately configured because many | |
656 | * (most?) embedded boards don't use SDRAM DIMMs. | |
657 | */ | |
c76fe474 | 658 | #if defined(CONFIG_CMD_SDRAM) |
632de067 LJ |
659 | static void print_ddr2_tcyc (u_char const b) |
660 | { | |
661 | printf ("%d.", (b >> 4) & 0x0F); | |
662 | switch (b & 0x0F) { | |
663 | case 0x0: | |
664 | case 0x1: | |
665 | case 0x2: | |
666 | case 0x3: | |
667 | case 0x4: | |
668 | case 0x5: | |
669 | case 0x6: | |
670 | case 0x7: | |
671 | case 0x8: | |
672 | case 0x9: | |
673 | printf ("%d ns\n", b & 0x0F); | |
674 | break; | |
675 | case 0xA: | |
676 | puts ("25 ns\n"); | |
677 | break; | |
678 | case 0xB: | |
679 | puts ("33 ns\n"); | |
680 | break; | |
681 | case 0xC: | |
682 | puts ("66 ns\n"); | |
683 | break; | |
684 | case 0xD: | |
685 | puts ("75 ns\n"); | |
686 | break; | |
687 | default: | |
688 | puts ("?? ns\n"); | |
689 | break; | |
690 | } | |
691 | } | |
692 | ||
693 | static void decode_bits (u_char const b, char const *str[], int const do_once) | |
694 | { | |
695 | u_char mask; | |
696 | ||
697 | for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) { | |
698 | if (b & mask) { | |
699 | puts (*str); | |
700 | if (do_once) | |
701 | return; | |
702 | } | |
703 | } | |
704 | } | |
81a8824f WD |
705 | |
706 | /* | |
707 | * Syntax: | |
0f89c54b | 708 | * i2c sdram {i2c_chip} |
81a8824f | 709 | */ |
54841ab5 | 710 | static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) |
81a8824f | 711 | { |
632de067 LJ |
712 | enum { unknown, EDO, SDRAM, DDR2 } type; |
713 | ||
81a8824f WD |
714 | u_char chip; |
715 | u_char data[128]; | |
716 | u_char cksum; | |
717 | int j; | |
718 | ||
632de067 LJ |
719 | static const char *decode_CAS_DDR2[] = { |
720 | " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD" | |
721 | }; | |
722 | ||
723 | static const char *decode_CAS_default[] = { | |
724 | " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1" | |
725 | }; | |
726 | ||
727 | static const char *decode_CS_WE_default[] = { | |
728 | " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0" | |
729 | }; | |
730 | ||
731 | static const char *decode_byte21_default[] = { | |
732 | " TBD (bit 7)\n", | |
733 | " Redundant row address\n", | |
734 | " Differential clock input\n", | |
735 | " Registerd DQMB inputs\n", | |
736 | " Buffered DQMB inputs\n", | |
737 | " On-card PLL\n", | |
738 | " Registered address/control lines\n", | |
739 | " Buffered address/control lines\n" | |
740 | }; | |
741 | ||
742 | static const char *decode_byte22_DDR2[] = { | |
743 | " TBD (bit 7)\n", | |
744 | " TBD (bit 6)\n", | |
745 | " TBD (bit 5)\n", | |
746 | " TBD (bit 4)\n", | |
747 | " TBD (bit 3)\n", | |
748 | " Supports partial array self refresh\n", | |
749 | " Supports 50 ohm ODT\n", | |
750 | " Supports weak driver\n" | |
751 | }; | |
752 | ||
753 | static const char *decode_row_density_DDR2[] = { | |
754 | "512 MiB", "256 MiB", "128 MiB", "16 GiB", | |
755 | "8 GiB", "4 GiB", "2 GiB", "1 GiB" | |
756 | }; | |
757 | ||
758 | static const char *decode_row_density_default[] = { | |
759 | "512 MiB", "256 MiB", "128 MiB", "64 MiB", | |
760 | "32 MiB", "16 MiB", "8 MiB", "4 MiB" | |
761 | }; | |
762 | ||
47e26b1b WD |
763 | if (argc < 2) |
764 | return cmd_usage(cmdtp); | |
765 | ||
81a8824f WD |
766 | /* |
767 | * Chip is always specified. | |
632de067 LJ |
768 | */ |
769 | chip = simple_strtoul (argv[1], NULL, 16); | |
81a8824f | 770 | |
632de067 | 771 | if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) { |
4b9206ed | 772 | puts ("No SDRAM Serial Presence Detect found.\n"); |
81a8824f WD |
773 | return 1; |
774 | } | |
775 | ||
776 | cksum = 0; | |
777 | for (j = 0; j < 63; j++) { | |
778 | cksum += data[j]; | |
779 | } | |
e857a5bd | 780 | if (cksum != data[63]) { |
81a8824f | 781 | printf ("WARNING: Configuration data checksum failure:\n" |
632de067 | 782 | " is 0x%02x, calculated 0x%02x\n", data[63], cksum); |
81a8824f | 783 | } |
632de067 | 784 | printf ("SPD data revision %d.%d\n", |
81a8824f | 785 | (data[62] >> 4) & 0x0F, data[62] & 0x0F); |
632de067 LJ |
786 | printf ("Bytes used 0x%02X\n", data[0]); |
787 | printf ("Serial memory size 0x%02X\n", 1 << data[1]); | |
788 | ||
4b9206ed | 789 | puts ("Memory type "); |
632de067 | 790 | switch (data[2]) { |
0df6b844 LJ |
791 | case 2: |
792 | type = EDO; | |
793 | puts ("EDO\n"); | |
794 | break; | |
795 | case 4: | |
796 | type = SDRAM; | |
797 | puts ("SDRAM\n"); | |
798 | break; | |
799 | case 8: | |
800 | type = DDR2; | |
801 | puts ("DDR2\n"); | |
802 | break; | |
803 | default: | |
804 | type = unknown; | |
805 | puts ("unknown\n"); | |
806 | break; | |
81a8824f | 807 | } |
632de067 | 808 | |
4b9206ed | 809 | puts ("Row address bits "); |
e857a5bd | 810 | if ((data[3] & 0x00F0) == 0) |
632de067 | 811 | printf ("%d\n", data[3] & 0x0F); |
e857a5bd | 812 | else |
632de067 LJ |
813 | printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F); |
814 | ||
4b9206ed | 815 | puts ("Column address bits "); |
e857a5bd | 816 | if ((data[4] & 0x00F0) == 0) |
632de067 | 817 | printf ("%d\n", data[4] & 0x0F); |
e857a5bd | 818 | else |
632de067 | 819 | printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F); |
0df6b844 LJ |
820 | |
821 | switch (type) { | |
822 | case DDR2: | |
632de067 LJ |
823 | printf ("Number of ranks %d\n", |
824 | (data[5] & 0x07) + 1); | |
0df6b844 LJ |
825 | break; |
826 | default: | |
632de067 | 827 | printf ("Module rows %d\n", data[5]); |
0df6b844 LJ |
828 | break; |
829 | } | |
830 | ||
831 | switch (type) { | |
832 | case DDR2: | |
632de067 | 833 | printf ("Module data width %d bits\n", data[6]); |
0df6b844 LJ |
834 | break; |
835 | default: | |
632de067 LJ |
836 | printf ("Module data width %d bits\n", |
837 | (data[7] << 8) | data[6]); | |
0df6b844 LJ |
838 | break; |
839 | } | |
840 | ||
4b9206ed | 841 | puts ("Interface signal levels "); |
81a8824f | 842 | switch(data[8]) { |
0df6b844 | 843 | case 0: puts ("TTL 5.0 V\n"); break; |
4b9206ed | 844 | case 1: puts ("LVTTL\n"); break; |
0df6b844 LJ |
845 | case 2: puts ("HSTL 1.5 V\n"); break; |
846 | case 3: puts ("SSTL 3.3 V\n"); break; | |
847 | case 4: puts ("SSTL 2.5 V\n"); break; | |
848 | case 5: puts ("SSTL 1.8 V\n"); break; | |
4b9206ed | 849 | default: puts ("unknown\n"); break; |
81a8824f | 850 | } |
0df6b844 LJ |
851 | |
852 | switch (type) { | |
853 | case DDR2: | |
632de067 LJ |
854 | printf ("SDRAM cycle time "); |
855 | print_ddr2_tcyc (data[9]); | |
0df6b844 LJ |
856 | break; |
857 | default: | |
632de067 LJ |
858 | printf ("SDRAM cycle time %d.%d ns\n", |
859 | (data[9] >> 4) & 0x0F, data[9] & 0x0F); | |
0df6b844 LJ |
860 | break; |
861 | } | |
862 | ||
863 | switch (type) { | |
864 | case DDR2: | |
632de067 LJ |
865 | printf ("SDRAM access time 0.%d%d ns\n", |
866 | (data[10] >> 4) & 0x0F, data[10] & 0x0F); | |
0df6b844 LJ |
867 | break; |
868 | default: | |
632de067 LJ |
869 | printf ("SDRAM access time %d.%d ns\n", |
870 | (data[10] >> 4) & 0x0F, data[10] & 0x0F); | |
0df6b844 LJ |
871 | break; |
872 | } | |
873 | ||
4b9206ed | 874 | puts ("EDC configuration "); |
632de067 | 875 | switch (data[11]) { |
4b9206ed WD |
876 | case 0: puts ("None\n"); break; |
877 | case 1: puts ("Parity\n"); break; | |
878 | case 2: puts ("ECC\n"); break; | |
879 | default: puts ("unknown\n"); break; | |
81a8824f | 880 | } |
632de067 | 881 | |
e857a5bd | 882 | if ((data[12] & 0x80) == 0) |
4b9206ed | 883 | puts ("No self refresh, rate "); |
e857a5bd | 884 | else |
4b9206ed | 885 | puts ("Self refresh, rate "); |
632de067 | 886 | |
81a8824f | 887 | switch(data[12] & 0x7F) { |
632de067 LJ |
888 | case 0: puts ("15.625 us\n"); break; |
889 | case 1: puts ("3.9 us\n"); break; | |
890 | case 2: puts ("7.8 us\n"); break; | |
891 | case 3: puts ("31.3 us\n"); break; | |
892 | case 4: puts ("62.5 us\n"); break; | |
893 | case 5: puts ("125 us\n"); break; | |
4b9206ed | 894 | default: puts ("unknown\n"); break; |
81a8824f | 895 | } |
0df6b844 LJ |
896 | |
897 | switch (type) { | |
898 | case DDR2: | |
632de067 | 899 | printf ("SDRAM width (primary) %d\n", data[13]); |
0df6b844 LJ |
900 | break; |
901 | default: | |
632de067 | 902 | printf ("SDRAM width (primary) %d\n", data[13] & 0x7F); |
0df6b844 | 903 | if ((data[13] & 0x80) != 0) { |
632de067 LJ |
904 | printf (" (second bank) %d\n", |
905 | 2 * (data[13] & 0x7F)); | |
0df6b844 LJ |
906 | } |
907 | break; | |
908 | } | |
909 | ||
910 | switch (type) { | |
911 | case DDR2: | |
912 | if (data[14] != 0) | |
632de067 | 913 | printf ("EDC width %d\n", data[14]); |
0df6b844 LJ |
914 | break; |
915 | default: | |
916 | if (data[14] != 0) { | |
632de067 LJ |
917 | printf ("EDC width %d\n", |
918 | data[14] & 0x7F); | |
0df6b844 LJ |
919 | |
920 | if ((data[14] & 0x80) != 0) { | |
632de067 LJ |
921 | printf (" (second bank) %d\n", |
922 | 2 * (data[14] & 0x7F)); | |
0df6b844 LJ |
923 | } |
924 | } | |
925 | break; | |
81a8824f | 926 | } |
0df6b844 | 927 | |
632de067 LJ |
928 | if (DDR2 != type) { |
929 | printf ("Min clock delay, back-to-back random column addresses " | |
930 | "%d\n", data[15]); | |
0df6b844 LJ |
931 | } |
932 | ||
4b9206ed WD |
933 | puts ("Burst length(s) "); |
934 | if (data[16] & 0x80) puts (" Page"); | |
935 | if (data[16] & 0x08) puts (" 8"); | |
936 | if (data[16] & 0x04) puts (" 4"); | |
937 | if (data[16] & 0x02) puts (" 2"); | |
938 | if (data[16] & 0x01) puts (" 1"); | |
939 | putc ('\n'); | |
632de067 | 940 | printf ("Number of banks %d\n", data[17]); |
0df6b844 LJ |
941 | |
942 | switch (type) { | |
943 | case DDR2: | |
944 | puts ("CAS latency(s) "); | |
632de067 | 945 | decode_bits (data[18], decode_CAS_DDR2, 0); |
0df6b844 LJ |
946 | putc ('\n'); |
947 | break; | |
948 | default: | |
949 | puts ("CAS latency(s) "); | |
632de067 | 950 | decode_bits (data[18], decode_CAS_default, 0); |
0df6b844 LJ |
951 | putc ('\n'); |
952 | break; | |
953 | } | |
954 | ||
955 | if (DDR2 != type) { | |
956 | puts ("CS latency(s) "); | |
632de067 | 957 | decode_bits (data[19], decode_CS_WE_default, 0); |
0df6b844 LJ |
958 | putc ('\n'); |
959 | } | |
960 | ||
961 | if (DDR2 != type) { | |
962 | puts ("WE latency(s) "); | |
632de067 | 963 | decode_bits (data[20], decode_CS_WE_default, 0); |
0df6b844 LJ |
964 | putc ('\n'); |
965 | } | |
966 | ||
967 | switch (type) { | |
968 | case DDR2: | |
969 | puts ("Module attributes:\n"); | |
970 | if (data[21] & 0x80) | |
971 | puts (" TBD (bit 7)\n"); | |
972 | if (data[21] & 0x40) | |
973 | puts (" Analysis probe installed\n"); | |
974 | if (data[21] & 0x20) | |
975 | puts (" TBD (bit 5)\n"); | |
976 | if (data[21] & 0x10) | |
977 | puts (" FET switch external enable\n"); | |
632de067 | 978 | printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03); |
0df6b844 | 979 | if (data[20] & 0x11) { |
632de067 LJ |
980 | printf (" %d active registers on DIMM\n", |
981 | (data[21] & 0x03) + 1); | |
0df6b844 LJ |
982 | } |
983 | break; | |
984 | default: | |
985 | puts ("Module attributes:\n"); | |
986 | if (!data[21]) | |
987 | puts (" (none)\n"); | |
632de067 LJ |
988 | else |
989 | decode_bits (data[21], decode_byte21_default, 0); | |
0df6b844 LJ |
990 | break; |
991 | } | |
992 | ||
993 | switch (type) { | |
994 | case DDR2: | |
632de067 | 995 | decode_bits (data[22], decode_byte22_DDR2, 0); |
0df6b844 LJ |
996 | break; |
997 | default: | |
998 | puts ("Device attributes:\n"); | |
999 | if (data[22] & 0x80) puts (" TBD (bit 7)\n"); | |
1000 | if (data[22] & 0x40) puts (" TBD (bit 6)\n"); | |
1001 | if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n"); | |
1002 | else puts (" Upper Vcc tolerance 10%\n"); | |
1003 | if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n"); | |
1004 | else puts (" Lower Vcc tolerance 10%\n"); | |
1005 | if (data[22] & 0x08) puts (" Supports write1/read burst\n"); | |
1006 | if (data[22] & 0x04) puts (" Supports precharge all\n"); | |
1007 | if (data[22] & 0x02) puts (" Supports auto precharge\n"); | |
1008 | if (data[22] & 0x01) puts (" Supports early RAS# precharge\n"); | |
1009 | break; | |
1010 | } | |
1011 | ||
1012 | switch (type) { | |
1013 | case DDR2: | |
632de067 LJ |
1014 | printf ("SDRAM cycle time (2nd highest CAS latency) "); |
1015 | print_ddr2_tcyc (data[23]); | |
0df6b844 LJ |
1016 | break; |
1017 | default: | |
632de067 LJ |
1018 | printf ("SDRAM cycle time (2nd highest CAS latency) %d." |
1019 | "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F); | |
0df6b844 LJ |
1020 | break; |
1021 | } | |
1022 | ||
1023 | switch (type) { | |
1024 | case DDR2: | |
632de067 LJ |
1025 | printf ("SDRAM access from clock (2nd highest CAS latency) 0." |
1026 | "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F); | |
0df6b844 LJ |
1027 | break; |
1028 | default: | |
632de067 LJ |
1029 | printf ("SDRAM access from clock (2nd highest CAS latency) %d." |
1030 | "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F); | |
0df6b844 LJ |
1031 | break; |
1032 | } | |
1033 | ||
1034 | switch (type) { | |
1035 | case DDR2: | |
632de067 LJ |
1036 | printf ("SDRAM cycle time (3rd highest CAS latency) "); |
1037 | print_ddr2_tcyc (data[25]); | |
0df6b844 LJ |
1038 | break; |
1039 | default: | |
632de067 LJ |
1040 | printf ("SDRAM cycle time (3rd highest CAS latency) %d." |
1041 | "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F); | |
0df6b844 LJ |
1042 | break; |
1043 | } | |
1044 | ||
1045 | switch (type) { | |
1046 | case DDR2: | |
632de067 LJ |
1047 | printf ("SDRAM access from clock (3rd highest CAS latency) 0." |
1048 | "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F); | |
0df6b844 LJ |
1049 | break; |
1050 | default: | |
632de067 LJ |
1051 | printf ("SDRAM access from clock (3rd highest CAS latency) %d." |
1052 | "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F); | |
0df6b844 LJ |
1053 | break; |
1054 | } | |
1055 | ||
1056 | switch (type) { | |
1057 | case DDR2: | |
632de067 LJ |
1058 | printf ("Minimum row precharge %d.%02d ns\n", |
1059 | (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03)); | |
0df6b844 LJ |
1060 | break; |
1061 | default: | |
632de067 | 1062 | printf ("Minimum row precharge %d ns\n", data[27]); |
0df6b844 LJ |
1063 | break; |
1064 | } | |
1065 | ||
1066 | switch (type) { | |
1067 | case DDR2: | |
632de067 LJ |
1068 | printf ("Row active to row active min %d.%02d ns\n", |
1069 | (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03)); | |
0df6b844 LJ |
1070 | break; |
1071 | default: | |
632de067 | 1072 | printf ("Row active to row active min %d ns\n", data[28]); |
0df6b844 LJ |
1073 | break; |
1074 | } | |
1075 | ||
1076 | switch (type) { | |
1077 | case DDR2: | |
632de067 LJ |
1078 | printf ("RAS to CAS delay min %d.%02d ns\n", |
1079 | (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03)); | |
0df6b844 LJ |
1080 | break; |
1081 | default: | |
632de067 | 1082 | printf ("RAS to CAS delay min %d ns\n", data[29]); |
0df6b844 LJ |
1083 | break; |
1084 | } | |
1085 | ||
632de067 | 1086 | printf ("Minimum RAS pulse width %d ns\n", data[30]); |
0df6b844 LJ |
1087 | |
1088 | switch (type) { | |
1089 | case DDR2: | |
632de067 LJ |
1090 | puts ("Density of each row "); |
1091 | decode_bits (data[31], decode_row_density_DDR2, 1); | |
1092 | putc ('\n'); | |
0df6b844 LJ |
1093 | break; |
1094 | default: | |
632de067 LJ |
1095 | puts ("Density of each row "); |
1096 | decode_bits (data[31], decode_row_density_default, 1); | |
1097 | putc ('\n'); | |
0df6b844 LJ |
1098 | break; |
1099 | } | |
1100 | ||
1101 | switch (type) { | |
1102 | case DDR2: | |
632de067 | 1103 | puts ("Command and Address setup "); |
0df6b844 | 1104 | if (data[32] >= 0xA0) { |
632de067 LJ |
1105 | printf ("1.%d%d ns\n", |
1106 | ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F); | |
0df6b844 | 1107 | } else { |
632de067 LJ |
1108 | printf ("0.%d%d ns\n", |
1109 | ((data[32] >> 4) & 0x0F), data[32] & 0x0F); | |
0df6b844 LJ |
1110 | } |
1111 | break; | |
1112 | default: | |
632de067 LJ |
1113 | printf ("Command and Address setup %c%d.%d ns\n", |
1114 | (data[32] & 0x80) ? '-' : '+', | |
1115 | (data[32] >> 4) & 0x07, data[32] & 0x0F); | |
0df6b844 LJ |
1116 | break; |
1117 | } | |
1118 | ||
1119 | switch (type) { | |
1120 | case DDR2: | |
632de067 | 1121 | puts ("Command and Address hold "); |
0df6b844 | 1122 | if (data[33] >= 0xA0) { |
632de067 LJ |
1123 | printf ("1.%d%d ns\n", |
1124 | ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F); | |
0df6b844 | 1125 | } else { |
632de067 LJ |
1126 | printf ("0.%d%d ns\n", |
1127 | ((data[33] >> 4) & 0x0F), data[33] & 0x0F); | |
0df6b844 LJ |
1128 | } |
1129 | break; | |
1130 | default: | |
632de067 LJ |
1131 | printf ("Command and Address hold %c%d.%d ns\n", |
1132 | (data[33] & 0x80) ? '-' : '+', | |
1133 | (data[33] >> 4) & 0x07, data[33] & 0x0F); | |
0df6b844 LJ |
1134 | break; |
1135 | } | |
1136 | ||
1137 | switch (type) { | |
1138 | case DDR2: | |
632de067 LJ |
1139 | printf ("Data signal input setup 0.%d%d ns\n", |
1140 | (data[34] >> 4) & 0x0F, data[34] & 0x0F); | |
0df6b844 LJ |
1141 | break; |
1142 | default: | |
632de067 LJ |
1143 | printf ("Data signal input setup %c%d.%d ns\n", |
1144 | (data[34] & 0x80) ? '-' : '+', | |
1145 | (data[34] >> 4) & 0x07, data[34] & 0x0F); | |
0df6b844 LJ |
1146 | break; |
1147 | } | |
1148 | ||
1149 | switch (type) { | |
1150 | case DDR2: | |
632de067 LJ |
1151 | printf ("Data signal input hold 0.%d%d ns\n", |
1152 | (data[35] >> 4) & 0x0F, data[35] & 0x0F); | |
0df6b844 LJ |
1153 | break; |
1154 | default: | |
632de067 LJ |
1155 | printf ("Data signal input hold %c%d.%d ns\n", |
1156 | (data[35] & 0x80) ? '-' : '+', | |
1157 | (data[35] >> 4) & 0x07, data[35] & 0x0F); | |
0df6b844 LJ |
1158 | break; |
1159 | } | |
1160 | ||
4b9206ed | 1161 | puts ("Manufacturer's JEDEC ID "); |
e857a5bd | 1162 | for (j = 64; j <= 71; j++) |
632de067 | 1163 | printf ("%02X ", data[j]); |
4b9206ed | 1164 | putc ('\n'); |
632de067 | 1165 | printf ("Manufacturing Location %02X\n", data[72]); |
4b9206ed | 1166 | puts ("Manufacturer's Part Number "); |
e857a5bd | 1167 | for (j = 73; j <= 90; j++) |
632de067 | 1168 | printf ("%02X ", data[j]); |
4b9206ed | 1169 | putc ('\n'); |
632de067 LJ |
1170 | printf ("Revision Code %02X %02X\n", data[91], data[92]); |
1171 | printf ("Manufacturing Date %02X %02X\n", data[93], data[94]); | |
4b9206ed | 1172 | puts ("Assembly Serial Number "); |
e857a5bd | 1173 | for (j = 95; j <= 98; j++) |
632de067 | 1174 | printf ("%02X ", data[j]); |
4b9206ed | 1175 | putc ('\n'); |
81a8824f | 1176 | |
0df6b844 | 1177 | if (DDR2 != type) { |
632de067 LJ |
1178 | printf ("Speed rating PC%d\n", |
1179 | data[126] == 0x66 ? 66 : data[126]); | |
0df6b844 | 1180 | } |
81a8824f WD |
1181 | return 0; |
1182 | } | |
90253178 | 1183 | #endif |
81a8824f | 1184 | |
67b23a32 | 1185 | #if defined(CONFIG_I2C_MUX) |
54841ab5 | 1186 | static int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) |
67b23a32 HS |
1187 | { |
1188 | int ret=0; | |
1189 | ||
1190 | if (argc == 1) { | |
1191 | /* show all busses */ | |
1192 | I2C_MUX *mux; | |
1193 | I2C_MUX_DEVICE *device = i2c_mux_devices; | |
1194 | ||
1195 | printf ("Busses reached over muxes:\n"); | |
1196 | while (device != NULL) { | |
1197 | printf ("Bus ID: %x\n", device->busid); | |
1198 | printf (" reached over Mux(es):\n"); | |
1199 | mux = device->mux; | |
1200 | while (mux != NULL) { | |
1201 | printf (" %s@%x ch: %x\n", mux->name, mux->chip, mux->channel); | |
1202 | mux = mux->next; | |
1203 | } | |
1204 | device = device->next; | |
1205 | } | |
1206 | } else { | |
1207 | I2C_MUX_DEVICE *dev; | |
1208 | ||
1209 | dev = i2c_mux_ident_muxstring ((uchar *)argv[1]); | |
1210 | ret = 0; | |
1211 | } | |
1212 | return ret; | |
1213 | } | |
1214 | #endif /* CONFIG_I2C_MUX */ | |
1215 | ||
bb99ad6d | 1216 | #if defined(CONFIG_I2C_MULTI_BUS) |
54841ab5 | 1217 | static int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) |
bb99ad6d BW |
1218 | { |
1219 | int bus_idx, ret=0; | |
1220 | ||
e857a5bd TT |
1221 | if (argc == 1) |
1222 | /* querying current setting */ | |
bb99ad6d | 1223 | printf("Current bus is %d\n", i2c_get_bus_num()); |
e857a5bd | 1224 | else { |
bb99ad6d BW |
1225 | bus_idx = simple_strtoul(argv[1], NULL, 10); |
1226 | printf("Setting bus to %d\n", bus_idx); | |
1227 | ret = i2c_set_bus_num(bus_idx); | |
e857a5bd | 1228 | if (ret) |
bb99ad6d | 1229 | printf("Failure changing bus number (%d)\n", ret); |
bb99ad6d BW |
1230 | } |
1231 | return ret; | |
1232 | } | |
1233 | #endif /* CONFIG_I2C_MULTI_BUS */ | |
1234 | ||
54841ab5 | 1235 | static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) |
bb99ad6d BW |
1236 | { |
1237 | int speed, ret=0; | |
1238 | ||
e857a5bd TT |
1239 | if (argc == 1) |
1240 | /* querying current speed */ | |
bb99ad6d | 1241 | printf("Current bus speed=%d\n", i2c_get_bus_speed()); |
e857a5bd | 1242 | else { |
bb99ad6d BW |
1243 | speed = simple_strtoul(argv[1], NULL, 10); |
1244 | printf("Setting bus speed to %d Hz\n", speed); | |
1245 | ret = i2c_set_bus_speed(speed); | |
e857a5bd | 1246 | if (ret) |
bb99ad6d | 1247 | printf("Failure changing bus speed (%d)\n", ret); |
bb99ad6d BW |
1248 | } |
1249 | return ret; | |
1250 | } | |
1251 | ||
54841ab5 | 1252 | static int do_i2c_mm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) |
bb99ad6d | 1253 | { |
bfc3b77e FM |
1254 | return mod_i2c_mem (cmdtp, 1, flag, argc, argv); |
1255 | } | |
1256 | ||
54841ab5 | 1257 | static int do_i2c_nm(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) |
bfc3b77e FM |
1258 | { |
1259 | return mod_i2c_mem (cmdtp, 0, flag, argc, argv); | |
1260 | } | |
e96ad5d3 | 1261 | |
54841ab5 | 1262 | static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) |
bfc3b77e FM |
1263 | { |
1264 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); | |
1265 | return 0; | |
1266 | } | |
1267 | ||
1268 | static cmd_tbl_t cmd_i2c_sub[] = { | |
67b23a32 | 1269 | #if defined(CONFIG_I2C_MUX) |
bfc3b77e | 1270 | U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_add_bus, "", ""), |
67b23a32 | 1271 | #endif /* CONFIG_I2C_MUX */ |
bfc3b77e | 1272 | U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""), |
bb99ad6d | 1273 | #if defined(CONFIG_I2C_MULTI_BUS) |
bfc3b77e | 1274 | U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""), |
bb99ad6d | 1275 | #endif /* CONFIG_I2C_MULTI_BUS */ |
bfc3b77e FM |
1276 | U_BOOT_CMD_MKENT(loop, 3, 1, do_i2c_loop, "", ""), |
1277 | U_BOOT_CMD_MKENT(md, 3, 1, do_i2c_md, "", ""), | |
1278 | U_BOOT_CMD_MKENT(mm, 2, 1, do_i2c_mm, "", ""), | |
1279 | U_BOOT_CMD_MKENT(mw, 3, 1, do_i2c_mw, "", ""), | |
1280 | U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""), | |
1281 | U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""), | |
652e5354 | 1282 | U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""), |
bfc3b77e | 1283 | U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""), |
c76fe474 | 1284 | #if defined(CONFIG_CMD_SDRAM) |
bfc3b77e | 1285 | U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""), |
90253178 | 1286 | #endif |
bfc3b77e FM |
1287 | U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""), |
1288 | }; | |
1289 | ||
54841ab5 | 1290 | static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) |
bfc3b77e FM |
1291 | { |
1292 | cmd_tbl_t *c; | |
1293 | ||
1294 | /* Strip off leading 'i2c' command argument */ | |
1295 | argc--; | |
1296 | argv++; | |
1297 | ||
1298 | c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub)); | |
1299 | ||
47e26b1b | 1300 | if (c) |
bfc3b77e | 1301 | return c->cmd(cmdtp, flag, argc, argv); |
47e26b1b WD |
1302 | else |
1303 | return cmd_usage(cmdtp); | |
bb99ad6d | 1304 | } |
8bde7f77 WD |
1305 | |
1306 | /***************************************************/ | |
1307 | ||
d9fc7032 MF |
1308 | U_BOOT_CMD( |
1309 | i2c, 6, 1, do_i2c, | |
2fb2604d | 1310 | "I2C sub-system", |
67b23a32 | 1311 | #if defined(CONFIG_I2C_MUX) |
fb0070e9 | 1312 | "bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes\ni2c " |
67b23a32 | 1313 | #endif /* CONFIG_I2C_MUX */ |
fb0070e9 | 1314 | "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n" |
d9fc7032 | 1315 | #if defined(CONFIG_I2C_MULTI_BUS) |
9bc2e4ee | 1316 | "i2c dev [dev] - show or set current I2C bus\n" |
d9fc7032 | 1317 | #endif /* CONFIG_I2C_MULTI_BUS */ |
fb0070e9 | 1318 | "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n" |
d9fc7032 MF |
1319 | "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n" |
1320 | "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n" | |
1321 | "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n" | |
1322 | "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n" | |
d9fc7032 | 1323 | "i2c probe - show devices on the I2C bus\n" |
652e5354 | 1324 | "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n" |
e43a27c4 | 1325 | "i2c reset - re-init the I2C Controller\n" |
c76fe474 | 1326 | #if defined(CONFIG_CMD_SDRAM) |
fb0070e9 | 1327 | "i2c sdram chip - print SDRAM configuration information\n" |
90253178 | 1328 | #endif |
fb0070e9 | 1329 | "i2c speed [speed] - show or set I2C bus speed" |
d9fc7032 | 1330 | ); |
67b23a32 HS |
1331 | |
1332 | #if defined(CONFIG_I2C_MUX) | |
fd03ea89 | 1333 | static int i2c_mux_add_device(I2C_MUX_DEVICE *dev) |
67b23a32 HS |
1334 | { |
1335 | I2C_MUX_DEVICE *devtmp = i2c_mux_devices; | |
1336 | ||
1337 | if (i2c_mux_devices == NULL) { | |
1338 | i2c_mux_devices = dev; | |
1339 | return 0; | |
1340 | } | |
1341 | while (devtmp->next != NULL) | |
1342 | devtmp = devtmp->next; | |
1343 | ||
1344 | devtmp->next = dev; | |
1345 | return 0; | |
1346 | } | |
1347 | ||
1348 | I2C_MUX_DEVICE *i2c_mux_search_device(int id) | |
1349 | { | |
1350 | I2C_MUX_DEVICE *device = i2c_mux_devices; | |
1351 | ||
1352 | while (device != NULL) { | |
1353 | if (device->busid == id) | |
1354 | return device; | |
1355 | device = device->next; | |
1356 | } | |
1357 | return NULL; | |
1358 | } | |
1359 | ||
1360 | /* searches in the buf from *pos the next ':'. | |
1361 | * returns: | |
1362 | * 0 if found (with *pos = where) | |
1363 | * < 0 if an error occured | |
1364 | * > 0 if the end of buf is reached | |
1365 | */ | |
1366 | static int i2c_mux_search_next (int *pos, uchar *buf, int len) | |
1367 | { | |
1368 | while ((buf[*pos] != ':') && (*pos < len)) { | |
1369 | *pos += 1; | |
1370 | } | |
1371 | if (*pos >= len) | |
1372 | return 1; | |
1373 | if (buf[*pos] != ':') | |
1374 | return -1; | |
1375 | return 0; | |
1376 | } | |
1377 | ||
1378 | static int i2c_mux_get_busid (void) | |
1379 | { | |
1380 | int tmp = i2c_mux_busid; | |
1381 | ||
1382 | i2c_mux_busid ++; | |
1383 | return tmp; | |
1384 | } | |
1385 | ||
1386 | /* Analyses a Muxstring and sends immediately the | |
1387 | Commands to the Muxes. Runs from Flash. | |
1388 | */ | |
1389 | int i2c_mux_ident_muxstring_f (uchar *buf) | |
1390 | { | |
1391 | int pos = 0; | |
1392 | int oldpos; | |
1393 | int ret = 0; | |
1394 | int len = strlen((char *)buf); | |
1395 | int chip; | |
1396 | uchar channel; | |
1397 | int was = 0; | |
1398 | ||
1399 | while (ret == 0) { | |
1400 | oldpos = pos; | |
1401 | /* search name */ | |
1402 | ret = i2c_mux_search_next(&pos, buf, len); | |
1403 | if (ret != 0) | |
1404 | printf ("ERROR\n"); | |
1405 | /* search address */ | |
1406 | pos ++; | |
1407 | oldpos = pos; | |
1408 | ret = i2c_mux_search_next(&pos, buf, len); | |
1409 | if (ret != 0) | |
1410 | printf ("ERROR\n"); | |
1411 | buf[pos] = 0; | |
1412 | chip = simple_strtoul((char *)&buf[oldpos], NULL, 16); | |
1413 | buf[pos] = ':'; | |
1414 | /* search channel */ | |
1415 | pos ++; | |
1416 | oldpos = pos; | |
1417 | ret = i2c_mux_search_next(&pos, buf, len); | |
1418 | if (ret < 0) | |
1419 | printf ("ERROR\n"); | |
1420 | was = 0; | |
1421 | if (buf[pos] != 0) { | |
1422 | buf[pos] = 0; | |
1423 | was = 1; | |
1424 | } | |
1425 | channel = simple_strtoul((char *)&buf[oldpos], NULL, 16); | |
1426 | if (was) | |
1427 | buf[pos] = ':'; | |
1428 | if (i2c_write(chip, 0, 0, &channel, 1) != 0) { | |
1429 | printf ("Error setting Mux: chip:%x channel: \ | |
1430 | %x\n", chip, channel); | |
1431 | return -1; | |
1432 | } | |
1433 | pos ++; | |
1434 | oldpos = pos; | |
1435 | ||
1436 | } | |
1437 | ||
1438 | return 0; | |
1439 | } | |
1440 | ||
1441 | /* Analyses a Muxstring and if this String is correct | |
1442 | * adds a new I2C Bus. | |
1443 | */ | |
1444 | I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf) | |
1445 | { | |
1446 | I2C_MUX_DEVICE *device; | |
1447 | I2C_MUX *mux; | |
1448 | int pos = 0; | |
1449 | int oldpos; | |
1450 | int ret = 0; | |
1451 | int len = strlen((char *)buf); | |
1452 | int was = 0; | |
1453 | ||
1454 | device = (I2C_MUX_DEVICE *)malloc (sizeof(I2C_MUX_DEVICE)); | |
1455 | device->mux = NULL; | |
1456 | device->busid = i2c_mux_get_busid (); | |
1457 | device->next = NULL; | |
1458 | while (ret == 0) { | |
1459 | mux = (I2C_MUX *)malloc (sizeof(I2C_MUX)); | |
1460 | mux->next = NULL; | |
1461 | /* search name of mux */ | |
1462 | oldpos = pos; | |
1463 | ret = i2c_mux_search_next(&pos, buf, len); | |
1464 | if (ret != 0) | |
1465 | printf ("%s no name.\n", __FUNCTION__); | |
1466 | mux->name = (char *)malloc (pos - oldpos + 1); | |
1467 | memcpy (mux->name, &buf[oldpos], pos - oldpos); | |
1468 | mux->name[pos - oldpos] = 0; | |
1469 | /* search address */ | |
1470 | pos ++; | |
1471 | oldpos = pos; | |
1472 | ret = i2c_mux_search_next(&pos, buf, len); | |
1473 | if (ret != 0) | |
1474 | printf ("%s no mux address.\n", __FUNCTION__); | |
1475 | buf[pos] = 0; | |
1476 | mux->chip = simple_strtoul((char *)&buf[oldpos], NULL, 16); | |
1477 | buf[pos] = ':'; | |
1478 | /* search channel */ | |
1479 | pos ++; | |
1480 | oldpos = pos; | |
1481 | ret = i2c_mux_search_next(&pos, buf, len); | |
1482 | if (ret < 0) | |
1483 | printf ("%s no mux channel.\n", __FUNCTION__); | |
1484 | was = 0; | |
1485 | if (buf[pos] != 0) { | |
1486 | buf[pos] = 0; | |
1487 | was = 1; | |
1488 | } | |
1489 | mux->channel = simple_strtoul((char *)&buf[oldpos], NULL, 16); | |
1490 | if (was) | |
1491 | buf[pos] = ':'; | |
1492 | if (device->mux == NULL) | |
1493 | device->mux = mux; | |
1494 | else { | |
1495 | I2C_MUX *muxtmp = device->mux; | |
1496 | while (muxtmp->next != NULL) { | |
1497 | muxtmp = muxtmp->next; | |
1498 | } | |
1499 | muxtmp->next = mux; | |
1500 | } | |
1501 | pos ++; | |
1502 | oldpos = pos; | |
1503 | } | |
1504 | if (ret > 0) { | |
1505 | /* Add Device */ | |
1506 | i2c_mux_add_device (device); | |
1507 | return device; | |
1508 | } | |
1509 | ||
1510 | return NULL; | |
1511 | } | |
1512 | ||
1513 | int i2x_mux_select_mux(int bus) | |
1514 | { | |
1515 | I2C_MUX_DEVICE *dev; | |
1516 | I2C_MUX *mux; | |
1517 | ||
1518 | if ((gd->flags & GD_FLG_RELOC) != GD_FLG_RELOC) { | |
1519 | /* select Default Mux Bus */ | |
6d0f6bcf JCPV |
1520 | #if defined(CONFIG_SYS_I2C_IVM_BUS) |
1521 | i2c_mux_ident_muxstring_f ((uchar *)CONFIG_SYS_I2C_IVM_BUS); | |
67b23a32 HS |
1522 | #else |
1523 | { | |
1524 | unsigned char *buf; | |
1525 | buf = (unsigned char *) getenv("EEprom_ivm"); | |
1526 | if (buf != NULL) | |
1527 | i2c_mux_ident_muxstring_f (buf); | |
1528 | } | |
1529 | #endif | |
1530 | return 0; | |
1531 | } | |
1532 | dev = i2c_mux_search_device(bus); | |
1533 | if (dev == NULL) | |
1534 | return -1; | |
1535 | ||
1536 | mux = dev->mux; | |
1537 | while (mux != NULL) { | |
1538 | if (i2c_write(mux->chip, 0, 0, &mux->channel, 1) != 0) { | |
1539 | printf ("Error setting Mux: chip:%x channel: \ | |
1540 | %x\n", mux->chip, mux->channel); | |
1541 | return -1; | |
1542 | } | |
1543 | mux = mux->next; | |
1544 | } | |
1545 | return 0; | |
1546 | } | |
1547 | #endif /* CONFIG_I2C_MUX */ |