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dd7d41f0 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * MII Utilities | |
26 | */ | |
27 | ||
28 | #include <common.h> | |
29 | #include <command.h> | |
dd7d41f0 WD |
30 | |
31 | #if (CONFIG_COMMANDS & CFG_CMD_MII) | |
e35745bb WD |
32 | #include <miiphy.h> |
33 | ||
34 | #define CONFIG_TERSE_MII /* XXX necessary here because "miivals.h" is missing */ | |
dd7d41f0 | 35 | |
2471111d | 36 | #ifdef CONFIG_TERSE_MII |
dd7d41f0 WD |
37 | /* |
38 | * Display values from last command. | |
39 | */ | |
40 | uint last_op; | |
41 | uint last_addr; | |
42 | uint last_data; | |
43 | uint last_reg; | |
44 | ||
45 | /* | |
46 | * MII read/write | |
47 | * | |
48 | * Syntax: | |
49 | * mii read {addr} {reg} | |
50 | * mii write {addr} {reg} {data} | |
51 | */ | |
52 | ||
53 | int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) | |
54 | { | |
55 | char op; | |
56 | unsigned char addr, reg; | |
57 | unsigned short data; | |
58 | int rcode = 0; | |
59 | ||
bf9e3b38 | 60 | #if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2) |
dd7d41f0 WD |
61 | mii_init (); |
62 | #endif | |
63 | ||
64 | /* | |
65 | * We use the last specified parameters, unless new ones are | |
66 | * entered. | |
67 | */ | |
68 | op = last_op; | |
69 | addr = last_addr; | |
70 | data = last_data; | |
71 | reg = last_reg; | |
72 | ||
73 | if ((flag & CMD_FLAG_REPEAT) == 0) { | |
74 | op = argv[1][0]; | |
75 | if (argc >= 3) | |
76 | addr = simple_strtoul (argv[2], NULL, 16); | |
77 | if (argc >= 4) | |
78 | reg = simple_strtoul (argv[3], NULL, 16); | |
79 | if (argc >= 5) | |
80 | data = simple_strtoul (argv[4], NULL, 16); | |
81 | } | |
82 | ||
83 | /* | |
84 | * check info/read/write. | |
85 | */ | |
86 | if (op == 'i') { | |
8bf3b005 | 87 | unsigned char j, start, end; |
dd7d41f0 WD |
88 | unsigned int oui; |
89 | unsigned char model; | |
90 | unsigned char rev; | |
91 | ||
92 | /* | |
93 | * Look for any and all PHYs. Valid addresses are 0..31. | |
94 | */ | |
8bf3b005 WD |
95 | if (argc >= 3) { |
96 | start = addr; end = addr + 1; | |
97 | } else { | |
98 | start = 0; end = 32; | |
99 | } | |
100 | ||
101 | for (j = start; j < end; j++) { | |
dd7d41f0 WD |
102 | if (miiphy_info (j, &oui, &model, &rev) == 0) { |
103 | printf ("PHY 0x%02X: " | |
104 | "OUI = 0x%04X, " | |
105 | "Model = 0x%02X, " | |
106 | "Rev = 0x%02X, " | |
107 | "%3dbaseT, %s\n", | |
108 | j, oui, model, rev, | |
855a496f | 109 | miiphy_speed (j), |
dd7d41f0 WD |
110 | miiphy_duplex (j) == FULL ? "FDX" : "HDX"); |
111 | } | |
112 | } | |
113 | } else if (op == 'r') { | |
114 | if (miiphy_read (addr, reg, &data) != 0) { | |
4b9206ed | 115 | puts ("Error reading from the PHY\n"); |
dd7d41f0 WD |
116 | rcode = 1; |
117 | } | |
118 | printf ("%04X\n", data & 0x0000FFFF); | |
119 | } else if (op == 'w') { | |
120 | if (miiphy_write (addr, reg, data) != 0) { | |
4b9206ed | 121 | puts ("Error writing to the PHY\n"); |
dd7d41f0 WD |
122 | rcode = 1; |
123 | } | |
124 | } else { | |
125 | printf ("Usage:\n%s\n", cmdtp->usage); | |
126 | return 1; | |
127 | } | |
128 | ||
129 | /* | |
130 | * Save the parameters for repeats. | |
131 | */ | |
132 | last_op = op; | |
133 | last_addr = addr; | |
134 | last_data = data; | |
80885a9d | 135 | last_reg = reg; |
dd7d41f0 WD |
136 | |
137 | return rcode; | |
138 | } | |
139 | ||
8bde7f77 WD |
140 | /***************************************************/ |
141 | ||
0d498393 WD |
142 | U_BOOT_CMD( |
143 | mii, 5, 1, do_mii, | |
8bde7f77 WD |
144 | "mii - MII utility commands\n", |
145 | "info <addr> - display MII PHY info\n" | |
146 | "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n" | |
147 | "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n" | |
148 | ); | |
e35745bb WD |
149 | |
150 | #else /* ! CONFIG_TERSE_MII ================================================= */ | |
151 | ||
152 | #include <miivals.h> | |
8bde7f77 | 153 | |
2471111d WD |
154 | typedef struct _MII_reg_desc_t { |
155 | ushort regno; | |
156 | char * name; | |
157 | } MII_reg_desc_t; | |
158 | ||
159 | MII_reg_desc_t reg_0_5_desc_tbl[] = { | |
160 | { 0, "PHY control register" }, | |
161 | { 1, "PHY status register" }, | |
162 | { 2, "PHY ID 1 register" }, | |
163 | { 3, "PHY ID 2 register" }, | |
164 | { 4, "Autonegotiation advertisement register" }, | |
165 | { 5, "Autonegotiation partner abilities register" }, | |
166 | }; | |
167 | ||
168 | typedef struct _MII_field_desc_t { | |
169 | ushort hi; | |
170 | ushort lo; | |
171 | ushort mask; | |
172 | char * name; | |
173 | } MII_field_desc_t; | |
174 | ||
175 | MII_field_desc_t reg_0_desc_tbl[] = { | |
176 | { 15, 15, 0x01, "reset" }, | |
177 | { 14, 14, 0x01, "loopback" }, | |
178 | { 13, 6, 0x81, "speed selection" }, /* special */ | |
179 | { 12, 12, 0x01, "A/N enable" }, | |
180 | { 11, 11, 0x01, "power-down" }, | |
181 | { 10, 10, 0x01, "isolate" }, | |
182 | { 9, 9, 0x01, "restart A/N" }, | |
183 | { 8, 8, 0x01, "duplex" }, /* special */ | |
184 | { 7, 7, 0x01, "collision test enable" }, | |
185 | { 5, 0, 0x3f, "(reserved)" } | |
186 | }; | |
187 | ||
188 | MII_field_desc_t reg_1_desc_tbl[] = { | |
189 | { 15, 15, 0x01, "100BASE-T4 able" }, | |
190 | { 14, 14, 0x01, "100BASE-X full duplex able" }, | |
191 | { 13, 13, 0x01, "100BASE-X half duplex able" }, | |
192 | { 12, 12, 0x01, "10 Mbps full duplex able" }, | |
193 | { 11, 11, 0x01, "10 Mbps half duplex able" }, | |
194 | { 10, 10, 0x01, "100BASE-T2 full duplex able" }, | |
195 | { 9, 9, 0x01, "100BASE-T2 half duplex able" }, | |
196 | { 8, 8, 0x01, "extended status" }, | |
197 | { 7, 7, 0x01, "(reserved)" }, | |
198 | { 6, 6, 0x01, "MF preamble suppression" }, | |
199 | { 5, 5, 0x01, "A/N complete" }, | |
200 | { 4, 4, 0x01, "remote fault" }, | |
201 | { 3, 3, 0x01, "A/N able" }, | |
202 | { 2, 2, 0x01, "link status" }, | |
203 | { 1, 1, 0x01, "jabber detect" }, | |
204 | { 0, 0, 0x01, "extended capabilities" }, | |
205 | }; | |
206 | ||
207 | MII_field_desc_t reg_2_desc_tbl[] = { | |
208 | { 15, 0, 0xffff, "OUI portion" }, | |
209 | }; | |
210 | ||
211 | MII_field_desc_t reg_3_desc_tbl[] = { | |
212 | { 15, 10, 0x3f, "OUI portion" }, | |
213 | { 9, 4, 0x3f, "manufacturer part number" }, | |
214 | { 3, 0, 0x0f, "manufacturer rev. number" }, | |
215 | }; | |
216 | ||
217 | MII_field_desc_t reg_4_desc_tbl[] = { | |
218 | { 15, 15, 0x01, "next page able" }, | |
219 | { 14, 14, 0x01, "reserved" }, | |
220 | { 13, 13, 0x01, "remote fault" }, | |
221 | { 12, 12, 0x01, "reserved" }, | |
222 | { 11, 11, 0x01, "asymmetric pause" }, | |
223 | { 10, 10, 0x01, "pause enable" }, | |
224 | { 9, 9, 0x01, "100BASE-T4 able" }, | |
225 | { 8, 8, 0x01, "100BASE-TX full duplex able" }, | |
226 | { 7, 7, 0x01, "100BASE-TX able" }, | |
227 | { 6, 6, 0x01, "10BASE-T full duplex able" }, | |
228 | { 5, 5, 0x01, "10BASE-T able" }, | |
229 | { 4, 0, 0x1f, "xxx to do" }, | |
230 | }; | |
231 | ||
232 | MII_field_desc_t reg_5_desc_tbl[] = { | |
233 | { 15, 15, 0x01, "next page able" }, | |
234 | { 14, 14, 0x01, "acknowledge" }, | |
235 | { 13, 13, 0x01, "remote fault" }, | |
236 | { 12, 12, 0x01, "(reserved)" }, | |
237 | { 11, 11, 0x01, "asymmetric pause able" }, | |
238 | { 10, 10, 0x01, "pause able" }, | |
239 | { 9, 9, 0x01, "100BASE-T4 able" }, | |
240 | { 8, 8, 0x01, "100BASE-X full duplex able" }, | |
241 | { 7, 7, 0x01, "100BASE-TX able" }, | |
242 | { 6, 6, 0x01, "10BASE-T full duplex able" }, | |
243 | { 5, 5, 0x01, "10BASE-T able" }, | |
244 | { 4, 0, 0x1f, "xxx to do" }, | |
245 | }; | |
246 | ||
247 | #define DESC0LEN (sizeof(reg_0_desc_tbl)/sizeof(reg_0_desc_tbl[0])) | |
248 | #define DESC1LEN (sizeof(reg_1_desc_tbl)/sizeof(reg_1_desc_tbl[0])) | |
249 | #define DESC2LEN (sizeof(reg_2_desc_tbl)/sizeof(reg_2_desc_tbl[0])) | |
250 | #define DESC3LEN (sizeof(reg_3_desc_tbl)/sizeof(reg_3_desc_tbl[0])) | |
251 | #define DESC4LEN (sizeof(reg_4_desc_tbl)/sizeof(reg_4_desc_tbl[0])) | |
252 | #define DESC5LEN (sizeof(reg_5_desc_tbl)/sizeof(reg_5_desc_tbl[0])) | |
253 | ||
254 | typedef struct _MII_field_desc_and_len_t { | |
255 | MII_field_desc_t * pdesc; | |
256 | ushort len; | |
257 | } MII_field_desc_and_len_t; | |
258 | ||
259 | MII_field_desc_and_len_t desc_and_len_tbl[] = { | |
260 | { reg_0_desc_tbl, DESC0LEN }, | |
261 | { reg_1_desc_tbl, DESC1LEN }, | |
262 | { reg_2_desc_tbl, DESC2LEN }, | |
263 | { reg_3_desc_tbl, DESC3LEN }, | |
264 | { reg_4_desc_tbl, DESC4LEN }, | |
265 | { reg_5_desc_tbl, DESC5LEN }, | |
266 | }; | |
267 | ||
268 | static void dump_reg( | |
269 | ushort regval, | |
270 | MII_reg_desc_t * prd, | |
271 | MII_field_desc_and_len_t * pdl); | |
272 | ||
273 | static int special_field( | |
274 | ushort regno, | |
275 | MII_field_desc_t * pdesc, | |
276 | ushort regval); | |
277 | ||
278 | void MII_dump_0_to_5( | |
279 | ushort regvals[6], | |
280 | uchar reglo, | |
281 | uchar reghi) | |
282 | { | |
283 | ulong i; | |
284 | ||
285 | for (i = 0; i < 6; i++) { | |
286 | if ((reglo <= i) && (i <= reghi)) | |
287 | dump_reg(regvals[i], ®_0_5_desc_tbl[i], | |
288 | &desc_and_len_tbl[i]); | |
289 | } | |
290 | } | |
291 | ||
292 | static void dump_reg( | |
293 | ushort regval, | |
294 | MII_reg_desc_t * prd, | |
295 | MII_field_desc_and_len_t * pdl) | |
296 | { | |
297 | ulong i; | |
298 | ushort mask_in_place; | |
299 | MII_field_desc_t * pdesc; | |
300 | ||
301 | printf("%u. (%04hx) -- %s --\n", | |
302 | prd->regno, regval, prd->name); | |
303 | ||
304 | for (i = 0; i < pdl->len; i++) { | |
305 | pdesc = &pdl->pdesc[i]; | |
306 | ||
307 | mask_in_place = pdesc->mask << pdesc->lo; | |
308 | ||
309 | printf(" (%04hx:%04hx) %u.", | |
310 | mask_in_place, | |
311 | regval & mask_in_place, | |
312 | prd->regno); | |
313 | ||
314 | if (special_field(prd->regno, pdesc, regval)) { | |
315 | } | |
316 | else { | |
317 | if (pdesc->hi == pdesc->lo) | |
318 | printf("%2u ", pdesc->lo); | |
319 | else | |
320 | printf("%2u-%2u", pdesc->hi, pdesc->lo); | |
321 | printf(" = %5u %s", | |
322 | (regval & mask_in_place) >> pdesc->lo, | |
323 | pdesc->name); | |
324 | } | |
325 | printf("\n"); | |
326 | ||
327 | } | |
328 | printf("\n"); | |
329 | } | |
330 | ||
331 | /* Special fields: | |
332 | ** 0.6,13 | |
333 | ** 0.8 | |
334 | ** 2.15-0 | |
335 | ** 3.15-0 | |
336 | ** 4.4-0 | |
337 | ** 5.4-0 | |
338 | */ | |
339 | ||
340 | static int special_field( | |
341 | ushort regno, | |
342 | MII_field_desc_t * pdesc, | |
343 | ushort regval) | |
344 | { | |
345 | if ((regno == 0) && (pdesc->lo == 6)) { | |
346 | ushort speed_bits = regval & MII_CTL_SPEED_MASK; | |
347 | printf("%2u,%2u = b%u%u speed selection = %s Mbps", | |
348 | 6, 13, | |
349 | (regval >> 6) & 1, | |
350 | (regval >> 13) & 1, | |
351 | speed_bits == MII_CTL_SPEED_1000_MBPS ? "1000" : | |
352 | speed_bits == MII_CTL_SPEED_100_MBPS ? "100" : | |
353 | speed_bits == MII_CTL_SPEED_10_MBPS ? "10" : | |
354 | "???"); | |
355 | return 1; | |
356 | } | |
357 | ||
358 | else if ((regno == 0) && (pdesc->lo == 8)) { | |
359 | printf("%2u = %5u duplex = %s", | |
360 | pdesc->lo, | |
361 | (regval >> pdesc->lo) & 1, | |
362 | ((regval >> pdesc->lo) & 1) ? "full" : "half"); | |
363 | return 1; | |
364 | } | |
365 | ||
366 | else if ((regno == 4) && (pdesc->lo == 0)) { | |
367 | ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask; | |
368 | printf("%2u-%2u = %5u selector = %s", | |
369 | pdesc->hi, pdesc->lo, sel_bits, | |
370 | sel_bits == MII_AN_ADV_IEEE_802_3 ? | |
371 | "IEEE 802.3" : | |
372 | sel_bits == MII_AN_ADV_IEEE_802_9_ISLAN_16T ? | |
373 | "IEEE 802.9 ISLAN-16T" : | |
374 | "???"); | |
375 | return 1; | |
376 | } | |
377 | ||
378 | else if ((regno == 5) && (pdesc->lo == 0)) { | |
379 | ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask; | |
380 | printf("%2u-%2u = %u selector = %s", | |
381 | pdesc->hi, pdesc->lo, sel_bits, | |
382 | sel_bits == MII_AN_PARTNER_IEEE_802_3 ? | |
383 | "IEEE 802.3" : | |
384 | sel_bits == MII_AN_PARTNER_IEEE_802_9_ISLAN_16T ? | |
385 | "IEEE 802.9 ISLAN-16T" : | |
386 | "???"); | |
387 | return 1; | |
388 | } | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
393 | uint last_op; | |
394 | uint last_data; | |
395 | uint last_addr_lo; | |
396 | uint last_addr_hi; | |
397 | uint last_reg_lo; | |
398 | uint last_reg_hi; | |
399 | ||
400 | static void extract_range( | |
401 | char * input, | |
402 | unsigned char * plo, | |
403 | unsigned char * phi) | |
404 | { | |
405 | char * end; | |
406 | *plo = simple_strtoul(input, &end, 16); | |
407 | if (*end == '-') { | |
408 | end++; | |
409 | *phi = simple_strtoul(end, NULL, 16); | |
410 | } | |
411 | else { | |
412 | *phi = *plo; | |
413 | } | |
414 | } | |
415 | ||
5cf91d6b | 416 | /* ---------------------------------------------------------------- */ |
2471111d WD |
417 | int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
418 | { | |
419 | char op; | |
420 | unsigned char addrlo, addrhi, reglo, reghi; | |
421 | unsigned char addr, reg; | |
422 | unsigned short data; | |
423 | int rcode = 0; | |
424 | ||
425 | #ifdef CONFIG_8xx | |
426 | mii_init (); | |
427 | #endif | |
428 | ||
429 | /* | |
430 | * We use the last specified parameters, unless new ones are | |
431 | * entered. | |
432 | */ | |
433 | op = last_op; | |
434 | addrlo = last_addr_lo; | |
435 | addrhi = last_addr_hi; | |
436 | reglo = last_reg_lo; | |
437 | reghi = last_reg_hi; | |
438 | data = last_data; | |
439 | ||
440 | if ((flag & CMD_FLAG_REPEAT) == 0) { | |
441 | op = argv[1][0]; | |
442 | if (argc >= 3) | |
443 | extract_range(argv[2], &addrlo, &addrhi); | |
444 | if (argc >= 4) | |
445 | extract_range(argv[3], ®lo, ®hi); | |
446 | if (argc >= 5) | |
447 | data = simple_strtoul (argv[4], NULL, 16); | |
448 | } | |
449 | ||
450 | /* | |
451 | * check info/read/write. | |
452 | */ | |
453 | if (op == 'i') { | |
454 | unsigned char j, start, end; | |
455 | unsigned int oui; | |
456 | unsigned char model; | |
457 | unsigned char rev; | |
458 | ||
459 | /* | |
460 | * Look for any and all PHYs. Valid addresses are 0..31. | |
461 | */ | |
462 | if (argc >= 3) { | |
463 | start = addr; end = addr + 1; | |
464 | } else { | |
465 | start = 0; end = 32; | |
466 | } | |
467 | ||
468 | for (j = start; j < end; j++) { | |
469 | if (miiphy_info (j, &oui, &model, &rev) == 0) { | |
470 | printf("PHY 0x%02X: " | |
471 | "OUI = 0x%04X, " | |
472 | "Model = 0x%02X, " | |
473 | "Rev = 0x%02X, " | |
474 | "%3dbaseT, %s\n", | |
475 | j, oui, model, rev, | |
476 | miiphy_speed (j), | |
477 | miiphy_duplex (j) == FULL ? "FDX" : "HDX"); | |
478 | } | |
479 | } | |
480 | } else if (op == 'r') { | |
481 | for (addr = addrlo; addr <= addrhi; addr++) { | |
482 | for (reg = reglo; reg <= reghi; reg++) { | |
483 | data = 0xffff; | |
484 | if (miiphy_read (addr, reg, &data) != 0) { | |
485 | printf( | |
486 | "Error reading from the PHY addr=%02x reg=%02x\n", | |
487 | addr, reg); | |
488 | rcode = 1; | |
489 | } | |
490 | else { | |
491 | if ((addrlo != addrhi) || (reglo != reghi)) | |
492 | printf("addr=%02x reg=%02x data=", | |
493 | (uint)addr, (uint)reg); | |
494 | printf("%04X\n", data & 0x0000FFFF); | |
495 | } | |
496 | } | |
497 | if ((addrlo != addrhi) && (reglo != reghi)) | |
498 | printf("\n"); | |
499 | } | |
500 | } else if (op == 'w') { | |
501 | for (addr = addrlo; addr <= addrhi; addr++) { | |
502 | for (reg = reglo; reg <= reghi; reg++) { | |
503 | if (miiphy_write (addr, reg, data) != 0) { | |
504 | printf("Error writing to the PHY addr=%02x reg=%02x\n", | |
505 | addr, reg); | |
506 | rcode = 1; | |
507 | } | |
508 | } | |
509 | } | |
510 | } else if (op == 'd') { | |
511 | ushort regs[6]; | |
512 | int ok = 1; | |
513 | if ((reglo > 5) || (reghi > 5)) { | |
514 | printf( | |
515 | "The MII dump command only formats the " | |
516 | "standard MII registers, 0-5.\n"); | |
517 | return 1; | |
518 | } | |
519 | for (addr = addrlo; addr <= addrhi; addr++) { | |
520 | for (reg = 0; reg < 6; reg++) { | |
521 | if (miiphy_read(addr, reg, ®s[reg]) != 0) { | |
522 | ok = 0; | |
523 | printf( | |
524 | "Error reading from the PHY addr=%02x reg=%02x\n", | |
525 | addr, reg); | |
526 | rcode = 1; | |
527 | } | |
528 | } | |
529 | if (ok) | |
530 | MII_dump_0_to_5(regs, reglo, reghi); | |
531 | printf("\n"); | |
532 | } | |
533 | } else { | |
534 | printf("Usage:\n%s\n", cmdtp->usage); | |
535 | return 1; | |
536 | } | |
537 | ||
538 | /* | |
539 | * Save the parameters for repeats. | |
540 | */ | |
541 | last_op = op; | |
542 | last_addr_lo = addrlo; | |
543 | last_addr_hi = addrhi; | |
544 | last_reg_lo = reglo; | |
545 | last_reg_hi = reghi; | |
546 | last_data = data; | |
547 | ||
548 | return rcode; | |
549 | } | |
550 | ||
551 | /***************************************************/ | |
552 | ||
553 | U_BOOT_CMD( | |
554 | mii, 5, 1, do_mii, | |
555 | "mii - MII utility commands\n", | |
556 | "info <addr> - display MII PHY info\n" | |
557 | "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n" | |
558 | "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n" | |
559 | "mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n" | |
560 | "Addr and/or reg may be ranges, e.g. 2-7.\n" | |
561 | ); | |
562 | ||
563 | #endif /* CONFIG_TERSE_MII */ | |
8bde7f77 | 564 | |
dd7d41f0 | 565 | #endif /* CFG_CMD_MII */ |