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Commit | Line | Data |
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c609719b WD |
1 | /* |
2 | * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
3 | * Andreas Heppel <aheppel@sysgo.de> | |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
7 | * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
10 | */ |
11 | ||
12 | /* | |
13 | * PCI routines | |
14 | */ | |
15 | ||
16 | #include <common.h> | |
0098e179 | 17 | #include <bootretry.h> |
18d66533 | 18 | #include <cli.h> |
c609719b | 19 | #include <command.h> |
c609719b WD |
20 | #include <asm/processor.h> |
21 | #include <asm/io.h> | |
c609719b WD |
22 | #include <pci.h> |
23 | ||
c609719b WD |
24 | /* |
25 | * Follows routines for the output of infos about devices on PCI bus. | |
26 | */ | |
27 | ||
28 | void pci_header_show(pci_dev_t dev); | |
29 | void pci_header_show_brief(pci_dev_t dev); | |
30 | ||
31 | /* | |
32 | * Subroutine: pciinfo | |
33 | * | |
34 | * Description: Show information about devices on PCI bus. | |
6d0f6bcf | 35 | * Depending on the define CONFIG_SYS_SHORT_PCI_LISTING |
c609719b WD |
36 | * the output will be more or less exhaustive. |
37 | * | |
38 | * Inputs: bus_no the number of the bus to be scanned. | |
39 | * | |
40 | * Return: None | |
41 | * | |
42 | */ | |
43 | void pciinfo(int BusNum, int ShortPCIListing) | |
44 | { | |
042b83d4 | 45 | struct pci_controller *hose = pci_bus_to_hose(BusNum); |
c609719b WD |
46 | int Device; |
47 | int Function; | |
48 | unsigned char HeaderType; | |
49 | unsigned short VendorID; | |
50 | pci_dev_t dev; | |
ff3e077b | 51 | int ret; |
c609719b | 52 | |
042b83d4 TR |
53 | if (!hose) |
54 | return; | |
55 | ||
c609719b WD |
56 | printf("Scanning PCI devices on bus %d\n", BusNum); |
57 | ||
58 | if (ShortPCIListing) { | |
59 | printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n"); | |
60 | printf("_____________________________________________________________\n"); | |
61 | } | |
62 | ||
63 | for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) { | |
64 | HeaderType = 0; | |
65 | VendorID = 0; | |
66 | for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) { | |
67 | /* | |
68 | * If this is not a multi-function device, we skip the rest. | |
69 | */ | |
70 | if (Function && !(HeaderType & 0x80)) | |
71 | break; | |
72 | ||
73 | dev = PCI_BDF(BusNum, Device, Function); | |
74 | ||
4efe52bf TR |
75 | if (pci_skip_dev(hose, dev)) |
76 | continue; | |
77 | ||
ff3e077b SG |
78 | ret = pci_read_config_word(dev, PCI_VENDOR_ID, |
79 | &VendorID); | |
80 | if (ret) | |
81 | goto error; | |
c609719b WD |
82 | if ((VendorID == 0xFFFF) || (VendorID == 0x0000)) |
83 | continue; | |
84 | ||
c7de829c | 85 | if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType); |
c609719b WD |
86 | |
87 | if (ShortPCIListing) | |
88 | { | |
89 | printf("%02x.%02x.%02x ", BusNum, Device, Function); | |
90 | pci_header_show_brief(dev); | |
91 | } | |
92 | else | |
93 | { | |
94 | printf("\nFound PCI device %02x.%02x.%02x:\n", | |
95 | BusNum, Device, Function); | |
96 | pci_header_show(dev); | |
97 | } | |
ff3e077b SG |
98 | } |
99 | } | |
100 | ||
101 | return; | |
102 | error: | |
103 | printf("Cannot read bus configuration: %d\n", ret); | |
c609719b WD |
104 | } |
105 | ||
c609719b WD |
106 | |
107 | /* | |
108 | * Subroutine: pci_header_show_brief | |
109 | * | |
110 | * Description: Reads and prints the header of the | |
53677ef1 | 111 | * specified PCI device in short form. |
c609719b WD |
112 | * |
113 | * Inputs: dev Bus+Device+Function number | |
114 | * | |
115 | * Return: None | |
116 | * | |
117 | */ | |
118 | void pci_header_show_brief(pci_dev_t dev) | |
119 | { | |
120 | u16 vendor, device; | |
121 | u8 class, subclass; | |
122 | ||
123 | pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); | |
124 | pci_read_config_word(dev, PCI_DEVICE_ID, &device); | |
125 | pci_read_config_byte(dev, PCI_CLASS_CODE, &class); | |
126 | pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass); | |
127 | ||
5d232d0e | 128 | printf("0x%.4x 0x%.4x %-23s 0x%.2x\n", |
c609719b | 129 | vendor, device, |
983eb9d1 | 130 | pci_class_str(class), subclass); |
c609719b WD |
131 | } |
132 | ||
133 | /* | |
134 | * Subroutine: PCI_Header_Show | |
135 | * | |
136 | * Description: Reads the header of the specified PCI device. | |
137 | * | |
138 | * Inputs: BusDevFunc Bus+Device+Function number | |
139 | * | |
140 | * Return: None | |
141 | * | |
142 | */ | |
143 | void pci_header_show(pci_dev_t dev) | |
144 | { | |
145 | u8 _byte, header_type; | |
146 | u16 _word; | |
147 | u32 _dword; | |
148 | ||
149 | #define PRINT(msg, type, reg) \ | |
150 | pci_read_config_##type(dev, reg, &_##type); \ | |
151 | printf(msg, _##type) | |
152 | ||
153 | #define PRINT2(msg, type, reg, func) \ | |
154 | pci_read_config_##type(dev, reg, &_##type); \ | |
155 | printf(msg, _##type, func(_##type)) | |
156 | ||
157 | pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type); | |
158 | ||
159 | PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID); | |
160 | PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID); | |
161 | PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND); | |
162 | PRINT (" status register = 0x%.4x\n", word, PCI_STATUS); | |
163 | PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID); | |
164 | PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE, | |
983eb9d1 | 165 | pci_class_str); |
c609719b WD |
166 | PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE); |
167 | PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG); | |
168 | PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE); | |
169 | PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER); | |
170 | PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE); | |
171 | PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST); | |
172 | PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0); | |
c609719b | 173 | |
7c7a23bd WD |
174 | switch (header_type & 0x03) { |
175 | case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */ | |
176 | PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1); | |
177 | PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2); | |
178 | PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3); | |
179 | PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4); | |
180 | PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5); | |
181 | PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS); | |
182 | PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID); | |
183 | PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID); | |
184 | PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS); | |
185 | PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); | |
186 | PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); | |
187 | PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT); | |
188 | PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT); | |
189 | break; | |
8bde7f77 | 190 | |
7c7a23bd WD |
191 | case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */ |
192 | ||
193 | PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1); | |
c609719b WD |
194 | PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS); |
195 | PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS); | |
196 | PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS); | |
197 | PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER); | |
198 | PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE); | |
199 | PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT); | |
200 | PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS); | |
201 | PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE); | |
202 | PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT); | |
203 | PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE); | |
204 | PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT); | |
205 | PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32); | |
206 | PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32); | |
207 | PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16); | |
208 | PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16); | |
209 | PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1); | |
210 | PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); | |
211 | PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); | |
212 | PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL); | |
7c7a23bd WD |
213 | break; |
214 | ||
215 | case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */ | |
216 | ||
217 | PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST); | |
218 | PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS); | |
219 | PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS); | |
220 | PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS); | |
221 | PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS); | |
8bde7f77 | 222 | PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER); |
7c7a23bd WD |
223 | PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0); |
224 | PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0); | |
225 | PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1); | |
226 | PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1); | |
227 | PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0); | |
228 | PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI); | |
229 | PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0); | |
230 | PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI); | |
231 | PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1); | |
232 | PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI); | |
233 | PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1); | |
234 | PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI); | |
235 | PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); | |
236 | PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); | |
237 | PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL); | |
238 | PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID); | |
239 | PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID); | |
240 | PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE); | |
241 | break; | |
8bde7f77 | 242 | |
7c7a23bd WD |
243 | default: |
244 | printf("unknown header\n"); | |
8bde7f77 | 245 | break; |
c609719b WD |
246 | } |
247 | ||
248 | #undef PRINT | |
249 | #undef PRINT2 | |
250 | } | |
251 | ||
252 | /* Convert the "bus.device.function" identifier into a number. | |
253 | */ | |
254 | static pci_dev_t get_pci_dev(char* name) | |
255 | { | |
256 | char cnum[12]; | |
257 | int len, i, iold, n; | |
258 | int bdfs[3] = {0,0,0}; | |
259 | ||
260 | len = strlen(name); | |
261 | if (len > 8) | |
262 | return -1; | |
263 | for (i = 0, iold = 0, n = 0; i < len; i++) { | |
264 | if (name[i] == '.') { | |
265 | memcpy(cnum, &name[iold], i - iold); | |
266 | cnum[i - iold] = '\0'; | |
267 | bdfs[n++] = simple_strtoul(cnum, NULL, 16); | |
268 | iold = i + 1; | |
269 | } | |
270 | } | |
271 | strcpy(cnum, &name[iold]); | |
272 | if (n == 0) | |
273 | n = 1; | |
274 | bdfs[n] = simple_strtoul(cnum, NULL, 16); | |
275 | return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]); | |
276 | } | |
277 | ||
278 | static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length) | |
279 | { | |
280 | #define DISP_LINE_LEN 16 | |
281 | ulong i, nbytes, linebytes; | |
282 | int rc = 0; | |
283 | ||
284 | if (length == 0) | |
285 | length = 0x40 / size; /* Standard PCI configuration space */ | |
286 | ||
287 | /* Print the lines. | |
288 | * once, and all accesses are with the specified bus width. | |
289 | */ | |
290 | nbytes = length * size; | |
291 | do { | |
292 | uint val4; | |
293 | ushort val2; | |
294 | u_char val1; | |
295 | ||
296 | printf("%08lx:", addr); | |
297 | linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes; | |
298 | for (i=0; i<linebytes; i+= size) { | |
299 | if (size == 4) { | |
300 | pci_read_config_dword(bdf, addr, &val4); | |
301 | printf(" %08x", val4); | |
302 | } else if (size == 2) { | |
303 | pci_read_config_word(bdf, addr, &val2); | |
304 | printf(" %04x", val2); | |
305 | } else { | |
306 | pci_read_config_byte(bdf, addr, &val1); | |
307 | printf(" %02x", val1); | |
308 | } | |
309 | addr += size; | |
310 | } | |
311 | printf("\n"); | |
312 | nbytes -= linebytes; | |
313 | if (ctrlc()) { | |
314 | rc = 1; | |
315 | break; | |
316 | } | |
317 | } while (nbytes > 0); | |
318 | ||
319 | return (rc); | |
320 | } | |
321 | ||
322 | static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value) | |
323 | { | |
324 | if (size == 4) { | |
325 | pci_write_config_dword(bdf, addr, value); | |
326 | } | |
327 | else if (size == 2) { | |
328 | ushort val = value & 0xffff; | |
329 | pci_write_config_word(bdf, addr, val); | |
330 | } | |
331 | else { | |
332 | u_char val = value & 0xff; | |
333 | pci_write_config_byte(bdf, addr, val); | |
334 | } | |
335 | return 0; | |
336 | } | |
337 | ||
338 | static int | |
339 | pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag) | |
340 | { | |
341 | ulong i; | |
342 | int nbytes; | |
c609719b WD |
343 | uint val4; |
344 | ushort val2; | |
345 | u_char val1; | |
346 | ||
347 | /* Print the address, followed by value. Then accept input for | |
348 | * the next value. A non-converted value exits. | |
349 | */ | |
350 | do { | |
351 | printf("%08lx:", addr); | |
352 | if (size == 4) { | |
353 | pci_read_config_dword(bdf, addr, &val4); | |
354 | printf(" %08x", val4); | |
355 | } | |
356 | else if (size == 2) { | |
357 | pci_read_config_word(bdf, addr, &val2); | |
358 | printf(" %04x", val2); | |
359 | } | |
360 | else { | |
361 | pci_read_config_byte(bdf, addr, &val1); | |
362 | printf(" %02x", val1); | |
363 | } | |
364 | ||
e1bf824d | 365 | nbytes = cli_readline(" ? "); |
c609719b WD |
366 | if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) { |
367 | /* <CR> pressed as only input, don't modify current | |
368 | * location and move to next. "-" pressed will go back. | |
369 | */ | |
370 | if (incrflag) | |
371 | addr += nbytes ? -size : size; | |
372 | nbytes = 1; | |
b26440f1 SG |
373 | /* good enough to not time out */ |
374 | bootretry_reset_cmd_timeout(); | |
c609719b WD |
375 | } |
376 | #ifdef CONFIG_BOOT_RETRY_TIME | |
377 | else if (nbytes == -2) { | |
378 | break; /* timed out, exit the command */ | |
379 | } | |
380 | #endif | |
381 | else { | |
382 | char *endp; | |
383 | i = simple_strtoul(console_buffer, &endp, 16); | |
384 | nbytes = endp - console_buffer; | |
385 | if (nbytes) { | |
c609719b WD |
386 | /* good enough to not time out |
387 | */ | |
b26440f1 | 388 | bootretry_reset_cmd_timeout(); |
c609719b WD |
389 | pci_cfg_write (bdf, addr, size, i); |
390 | if (incrflag) | |
391 | addr += size; | |
392 | } | |
393 | } | |
394 | } while (nbytes); | |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
399 | /* PCI Configuration Space access commands | |
400 | * | |
401 | * Syntax: | |
402 | * pci display[.b, .w, .l] bus.device.function} [addr] [len] | |
403 | * pci next[.b, .w, .l] bus.device.function [addr] | |
404 | * pci modify[.b, .w, .l] bus.device.function [addr] | |
405 | * pci write[.b, .w, .l] bus.device.function addr value | |
406 | */ | |
088f1b19 | 407 | static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
c609719b WD |
408 | { |
409 | ulong addr = 0, value = 0, size = 0; | |
410 | pci_dev_t bdf = 0; | |
411 | char cmd = 's'; | |
412 | ||
413 | if (argc > 1) | |
414 | cmd = argv[1][0]; | |
415 | ||
416 | switch (cmd) { | |
417 | case 'd': /* display */ | |
418 | case 'n': /* next */ | |
419 | case 'm': /* modify */ | |
420 | case 'w': /* write */ | |
421 | /* Check for a size specification. */ | |
422 | size = cmd_get_data_size(argv[1], 4); | |
423 | if (argc > 3) | |
424 | addr = simple_strtoul(argv[3], NULL, 16); | |
425 | if (argc > 4) | |
426 | value = simple_strtoul(argv[4], NULL, 16); | |
427 | case 'h': /* header */ | |
428 | if (argc < 3) | |
429 | goto usage; | |
430 | if ((bdf = get_pci_dev(argv[2])) == -1) | |
431 | return 1; | |
432 | break; | |
96d61603 JS |
433 | #ifdef CONFIG_CMD_PCI_ENUM |
434 | case 'e': | |
435 | break; | |
436 | #endif | |
c609719b WD |
437 | default: /* scan bus */ |
438 | value = 1; /* short listing */ | |
439 | bdf = 0; /* bus number */ | |
440 | if (argc > 1) { | |
441 | if (argv[argc-1][0] == 'l') { | |
442 | value = 0; | |
443 | argc--; | |
444 | } | |
445 | if (argc > 1) | |
446 | bdf = simple_strtoul(argv[1], NULL, 16); | |
447 | } | |
448 | pciinfo(bdf, value); | |
449 | return 0; | |
450 | } | |
451 | ||
452 | switch (argv[1][0]) { | |
453 | case 'h': /* header */ | |
454 | pci_header_show(bdf); | |
455 | return 0; | |
456 | case 'd': /* display */ | |
457 | return pci_cfg_display(bdf, addr, size, value); | |
96d61603 JS |
458 | #ifdef CONFIG_CMD_PCI_ENUM |
459 | case 'e': | |
460 | pci_init(); | |
461 | return 0; | |
462 | #endif | |
c609719b WD |
463 | case 'n': /* next */ |
464 | if (argc < 4) | |
465 | goto usage; | |
466 | return pci_cfg_modify(bdf, addr, size, value, 0); | |
467 | case 'm': /* modify */ | |
468 | if (argc < 4) | |
469 | goto usage; | |
470 | return pci_cfg_modify(bdf, addr, size, value, 1); | |
471 | case 'w': /* write */ | |
472 | if (argc < 5) | |
473 | goto usage; | |
474 | return pci_cfg_write(bdf, addr, size, value); | |
475 | } | |
476 | ||
477 | return 1; | |
478 | usage: | |
4c12eeb8 | 479 | return CMD_RET_USAGE; |
c609719b WD |
480 | } |
481 | ||
8bde7f77 WD |
482 | /***************************************************/ |
483 | ||
088f1b19 KP |
484 | #ifdef CONFIG_SYS_LONGHELP |
485 | static char pci_help_text[] = | |
8bde7f77 WD |
486 | "[bus] [long]\n" |
487 | " - short or long list of PCI devices on bus 'bus'\n" | |
96d61603 JS |
488 | #ifdef CONFIG_CMD_PCI_ENUM |
489 | "pci enum\n" | |
490 | " - re-enumerate PCI buses\n" | |
491 | #endif | |
8bde7f77 WD |
492 | "pci header b.d.f\n" |
493 | " - show header of PCI device 'bus.device.function'\n" | |
494 | "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n" | |
495 | " - display PCI configuration space (CFG)\n" | |
496 | "pci next[.b, .w, .l] b.d.f address\n" | |
497 | " - modify, read and keep CFG address\n" | |
498 | "pci modify[.b, .w, .l] b.d.f address\n" | |
499 | " - modify, auto increment CFG address\n" | |
500 | "pci write[.b, .w, .l] b.d.f address value\n" | |
088f1b19 KP |
501 | " - write to CFG address"; |
502 | #endif | |
503 | ||
504 | U_BOOT_CMD( | |
505 | pci, 5, 1, do_pci, | |
506 | "list and access PCI Configuration Space", pci_help_text | |
8bde7f77 | 507 | ); |