]>
Commit | Line | Data |
---|---|---|
83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
2 | /* |
3 | * (C) Copyright 2001 | |
4 | * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. | |
c609719b WD |
5 | */ |
6 | ||
7 | /* | |
8 | * This provides a bit-banged interface to the ethernet MII management | |
9 | * channel. | |
10 | */ | |
11 | ||
12 | #include <common.h> | |
c74c8e66 | 13 | #include <dm.h> |
c609719b | 14 | #include <miiphy.h> |
5f184715 | 15 | #include <phy.h> |
c609719b | 16 | |
63ff004c MB |
17 | #include <asm/types.h> |
18 | #include <linux/list.h> | |
19 | #include <malloc.h> | |
20 | #include <net.h> | |
21 | ||
22 | /* local debug macro */ | |
63ff004c MB |
23 | #undef MII_DEBUG |
24 | ||
25 | #undef debug | |
26 | #ifdef MII_DEBUG | |
16a53238 | 27 | #define debug(fmt, args...) printf(fmt, ##args) |
63ff004c | 28 | #else |
16a53238 | 29 | #define debug(fmt, args...) |
63ff004c MB |
30 | #endif /* MII_DEBUG */ |
31 | ||
63ff004c MB |
32 | static struct list_head mii_devs; |
33 | static struct mii_dev *current_mii; | |
34 | ||
0daac978 MF |
35 | /* |
36 | * Lookup the mii_dev struct by the registered device name. | |
37 | */ | |
5f184715 | 38 | struct mii_dev *miiphy_get_dev_by_name(const char *devname) |
0daac978 MF |
39 | { |
40 | struct list_head *entry; | |
41 | struct mii_dev *dev; | |
42 | ||
43 | if (!devname) { | |
44 | printf("NULL device name!\n"); | |
45 | return NULL; | |
46 | } | |
47 | ||
48 | list_for_each(entry, &mii_devs) { | |
49 | dev = list_entry(entry, struct mii_dev, link); | |
50 | if (strcmp(dev->name, devname) == 0) | |
51 | return dev; | |
52 | } | |
53 | ||
0daac978 MF |
54 | return NULL; |
55 | } | |
56 | ||
d9785c14 MB |
57 | /***************************************************************************** |
58 | * | |
59 | * Initialize global data. Need to be called before any other miiphy routine. | |
60 | */ | |
5700bb63 | 61 | void miiphy_init(void) |
d9785c14 | 62 | { |
16a53238 | 63 | INIT_LIST_HEAD(&mii_devs); |
298035df | 64 | current_mii = NULL; |
d9785c14 MB |
65 | } |
66 | ||
5f184715 AF |
67 | struct mii_dev *mdio_alloc(void) |
68 | { | |
69 | struct mii_dev *bus; | |
70 | ||
71 | bus = malloc(sizeof(*bus)); | |
72 | if (!bus) | |
73 | return bus; | |
74 | ||
75 | memset(bus, 0, sizeof(*bus)); | |
76 | ||
77 | /* initalize mii_dev struct fields */ | |
78 | INIT_LIST_HEAD(&bus->link); | |
79 | ||
80 | return bus; | |
81 | } | |
82 | ||
cb6baca7 BM |
83 | void mdio_free(struct mii_dev *bus) |
84 | { | |
85 | free(bus); | |
86 | } | |
87 | ||
5f184715 AF |
88 | int mdio_register(struct mii_dev *bus) |
89 | { | |
d39449b1 | 90 | if (!bus || !bus->read || !bus->write) |
5f184715 AF |
91 | return -1; |
92 | ||
93 | /* check if we have unique name */ | |
94 | if (miiphy_get_dev_by_name(bus->name)) { | |
95 | printf("mdio_register: non unique device name '%s'\n", | |
96 | bus->name); | |
97 | return -1; | |
98 | } | |
99 | ||
100 | /* add it to the list */ | |
101 | list_add_tail(&bus->link, &mii_devs); | |
102 | ||
103 | if (!current_mii) | |
104 | current_mii = bus; | |
105 | ||
106 | return 0; | |
107 | } | |
108 | ||
79e2a6a0 MS |
109 | int mdio_register_seq(struct mii_dev *bus, int seq) |
110 | { | |
111 | int ret; | |
112 | ||
113 | /* Setup a unique name for each mdio bus */ | |
114 | ret = snprintf(bus->name, MDIO_NAME_LEN, "eth%d", seq); | |
115 | if (ret < 0) | |
116 | return ret; | |
117 | ||
118 | return mdio_register(bus); | |
119 | } | |
120 | ||
cb6baca7 BM |
121 | int mdio_unregister(struct mii_dev *bus) |
122 | { | |
123 | if (!bus) | |
124 | return 0; | |
125 | ||
126 | /* delete it from the list */ | |
127 | list_del(&bus->link); | |
128 | ||
129 | if (current_mii == bus) | |
130 | current_mii = NULL; | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
5f184715 AF |
135 | void mdio_list_devices(void) |
136 | { | |
137 | struct list_head *entry; | |
138 | ||
139 | list_for_each(entry, &mii_devs) { | |
140 | int i; | |
141 | struct mii_dev *bus = list_entry(entry, struct mii_dev, link); | |
142 | ||
143 | printf("%s:\n", bus->name); | |
144 | ||
145 | for (i = 0; i < PHY_MAX_ADDR; i++) { | |
146 | struct phy_device *phydev = bus->phymap[i]; | |
147 | ||
148 | if (phydev) { | |
15a2acdf | 149 | printf("%x - %s", i, phydev->drv->name); |
5f184715 AF |
150 | |
151 | if (phydev->dev) | |
152 | printf(" <--> %s\n", phydev->dev->name); | |
153 | else | |
154 | printf("\n"); | |
155 | } | |
156 | } | |
157 | } | |
158 | } | |
159 | ||
5700bb63 | 160 | int miiphy_set_current_dev(const char *devname) |
63ff004c | 161 | { |
63ff004c MB |
162 | struct mii_dev *dev; |
163 | ||
5f184715 | 164 | dev = miiphy_get_dev_by_name(devname); |
0daac978 MF |
165 | if (dev) { |
166 | current_mii = dev; | |
167 | return 0; | |
63ff004c MB |
168 | } |
169 | ||
5f184715 AF |
170 | printf("No such device: %s\n", devname); |
171 | ||
63ff004c MB |
172 | return 1; |
173 | } | |
174 | ||
5f184715 AF |
175 | struct mii_dev *mdio_get_current_dev(void) |
176 | { | |
177 | return current_mii; | |
178 | } | |
179 | ||
9215bb1f PB |
180 | struct list_head *mdio_get_list_head(void) |
181 | { | |
182 | return &mii_devs; | |
183 | } | |
184 | ||
5f184715 AF |
185 | struct phy_device *mdio_phydev_for_ethname(const char *ethname) |
186 | { | |
187 | struct list_head *entry; | |
188 | struct mii_dev *bus; | |
189 | ||
190 | list_for_each(entry, &mii_devs) { | |
191 | int i; | |
192 | bus = list_entry(entry, struct mii_dev, link); | |
193 | ||
194 | for (i = 0; i < PHY_MAX_ADDR; i++) { | |
195 | if (!bus->phymap[i] || !bus->phymap[i]->dev) | |
196 | continue; | |
197 | ||
198 | if (strcmp(bus->phymap[i]->dev->name, ethname) == 0) | |
199 | return bus->phymap[i]; | |
200 | } | |
201 | } | |
202 | ||
203 | printf("%s is not a known ethernet\n", ethname); | |
204 | return NULL; | |
205 | } | |
206 | ||
5700bb63 | 207 | const char *miiphy_get_current_dev(void) |
63ff004c MB |
208 | { |
209 | if (current_mii) | |
210 | return current_mii->name; | |
211 | ||
212 | return NULL; | |
213 | } | |
214 | ||
ede16ea3 MF |
215 | static struct mii_dev *miiphy_get_active_dev(const char *devname) |
216 | { | |
217 | /* If the current mii is the one we want, return it */ | |
218 | if (current_mii) | |
219 | if (strcmp(current_mii->name, devname) == 0) | |
220 | return current_mii; | |
221 | ||
222 | /* Otherwise, set the active one to the one we want */ | |
223 | if (miiphy_set_current_dev(devname)) | |
224 | return NULL; | |
225 | else | |
226 | return current_mii; | |
227 | } | |
228 | ||
63ff004c MB |
229 | /***************************************************************************** |
230 | * | |
231 | * Read to variable <value> from the PHY attached to device <devname>, | |
232 | * use PHY address <addr> and register <reg>. | |
233 | * | |
1cdabc4b AF |
234 | * This API is deprecated. Use phy_read on a phy_device found via phy_connect |
235 | * | |
63ff004c MB |
236 | * Returns: |
237 | * 0 on success | |
238 | */ | |
f915c931 | 239 | int miiphy_read(const char *devname, unsigned char addr, unsigned char reg, |
298035df | 240 | unsigned short *value) |
63ff004c | 241 | { |
5f184715 | 242 | struct mii_dev *bus; |
d67d5d52 | 243 | int ret; |
63ff004c | 244 | |
5f184715 | 245 | bus = miiphy_get_active_dev(devname); |
d67d5d52 | 246 | if (!bus) |
5f184715 | 247 | return 1; |
63ff004c | 248 | |
d67d5d52 AG |
249 | ret = bus->read(bus, addr, MDIO_DEVAD_NONE, reg); |
250 | if (ret < 0) | |
251 | return 1; | |
252 | ||
253 | *value = (unsigned short)ret; | |
254 | return 0; | |
63ff004c MB |
255 | } |
256 | ||
257 | /***************************************************************************** | |
258 | * | |
259 | * Write <value> to the PHY attached to device <devname>, | |
260 | * use PHY address <addr> and register <reg>. | |
261 | * | |
1cdabc4b AF |
262 | * This API is deprecated. Use phy_write on a phy_device found by phy_connect |
263 | * | |
63ff004c MB |
264 | * Returns: |
265 | * 0 on success | |
266 | */ | |
f915c931 | 267 | int miiphy_write(const char *devname, unsigned char addr, unsigned char reg, |
298035df | 268 | unsigned short value) |
63ff004c | 269 | { |
5f184715 | 270 | struct mii_dev *bus; |
63ff004c | 271 | |
5f184715 AF |
272 | bus = miiphy_get_active_dev(devname); |
273 | if (bus) | |
274 | return bus->write(bus, addr, MDIO_DEVAD_NONE, reg, value); | |
63ff004c | 275 | |
0daac978 | 276 | return 1; |
63ff004c MB |
277 | } |
278 | ||
279 | /***************************************************************************** | |
280 | * | |
281 | * Print out list of registered MII capable devices. | |
282 | */ | |
16a53238 | 283 | void miiphy_listdev(void) |
63ff004c MB |
284 | { |
285 | struct list_head *entry; | |
286 | struct mii_dev *dev; | |
287 | ||
16a53238 AF |
288 | puts("MII devices: "); |
289 | list_for_each(entry, &mii_devs) { | |
290 | dev = list_entry(entry, struct mii_dev, link); | |
291 | printf("'%s' ", dev->name); | |
63ff004c | 292 | } |
16a53238 | 293 | puts("\n"); |
63ff004c MB |
294 | |
295 | if (current_mii) | |
16a53238 | 296 | printf("Current device: '%s'\n", current_mii->name); |
63ff004c MB |
297 | } |
298 | ||
c609719b WD |
299 | /***************************************************************************** |
300 | * | |
301 | * Read the OUI, manufacture's model number, and revision number. | |
302 | * | |
303 | * OUI: 22 bits (unsigned int) | |
304 | * Model: 6 bits (unsigned char) | |
305 | * Revision: 4 bits (unsigned char) | |
306 | * | |
1cdabc4b AF |
307 | * This API is deprecated. |
308 | * | |
c609719b WD |
309 | * Returns: |
310 | * 0 on success | |
311 | */ | |
5700bb63 | 312 | int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui, |
c609719b WD |
313 | unsigned char *model, unsigned char *rev) |
314 | { | |
315 | unsigned int reg = 0; | |
8bf3b005 | 316 | unsigned short tmp; |
c609719b | 317 | |
16a53238 AF |
318 | if (miiphy_read(devname, addr, MII_PHYSID2, &tmp) != 0) { |
319 | debug("PHY ID register 2 read failed\n"); | |
320 | return -1; | |
c609719b | 321 | } |
8bf3b005 | 322 | reg = tmp; |
c609719b | 323 | |
16a53238 | 324 | debug("MII_PHYSID2 @ 0x%x = 0x%04x\n", addr, reg); |
26c7bab8 | 325 | |
c609719b WD |
326 | if (reg == 0xFFFF) { |
327 | /* No physical device present at this address */ | |
16a53238 | 328 | return -1; |
c609719b WD |
329 | } |
330 | ||
16a53238 AF |
331 | if (miiphy_read(devname, addr, MII_PHYSID1, &tmp) != 0) { |
332 | debug("PHY ID register 1 read failed\n"); | |
333 | return -1; | |
c609719b | 334 | } |
8bf3b005 | 335 | reg |= tmp << 16; |
16a53238 | 336 | debug("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg); |
26c7bab8 | 337 | |
298035df LJ |
338 | *oui = (reg >> 10); |
339 | *model = (unsigned char)((reg >> 4) & 0x0000003F); | |
340 | *rev = (unsigned char)(reg & 0x0000000F); | |
16a53238 | 341 | return 0; |
c609719b WD |
342 | } |
343 | ||
5f184715 | 344 | #ifndef CONFIG_PHYLIB |
c609719b WD |
345 | /***************************************************************************** |
346 | * | |
347 | * Reset the PHY. | |
1cdabc4b AF |
348 | * |
349 | * This API is deprecated. Use PHYLIB. | |
350 | * | |
c609719b WD |
351 | * Returns: |
352 | * 0 on success | |
353 | */ | |
5700bb63 | 354 | int miiphy_reset(const char *devname, unsigned char addr) |
c609719b WD |
355 | { |
356 | unsigned short reg; | |
ab5a0dcb | 357 | int timeout = 500; |
c609719b | 358 | |
16a53238 AF |
359 | if (miiphy_read(devname, addr, MII_BMCR, ®) != 0) { |
360 | debug("PHY status read failed\n"); | |
361 | return -1; | |
f89920c3 | 362 | } |
16a53238 AF |
363 | if (miiphy_write(devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) { |
364 | debug("PHY reset failed\n"); | |
365 | return -1; | |
c609719b | 366 | } |
5653fc33 | 367 | #ifdef CONFIG_PHY_RESET_DELAY |
16a53238 | 368 | udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */ |
5653fc33 | 369 | #endif |
c609719b WD |
370 | /* |
371 | * Poll the control register for the reset bit to go to 0 (it is | |
372 | * auto-clearing). This should happen within 0.5 seconds per the | |
373 | * IEEE spec. | |
374 | */ | |
c609719b | 375 | reg = 0x8000; |
ab5a0dcb | 376 | while (((reg & 0x8000) != 0) && timeout--) { |
8ef583a0 | 377 | if (miiphy_read(devname, addr, MII_BMCR, ®) != 0) { |
ab5a0dcb SR |
378 | debug("PHY status read failed\n"); |
379 | return -1; | |
c609719b | 380 | } |
ab5a0dcb | 381 | udelay(1000); |
c609719b WD |
382 | } |
383 | if ((reg & 0x8000) == 0) { | |
16a53238 | 384 | return 0; |
c609719b | 385 | } else { |
16a53238 AF |
386 | puts("PHY reset timed out\n"); |
387 | return -1; | |
c609719b | 388 | } |
16a53238 | 389 | return 0; |
c609719b | 390 | } |
5f184715 | 391 | #endif /* !PHYLIB */ |
c609719b | 392 | |
c609719b WD |
393 | /***************************************************************************** |
394 | * | |
71bc6e64 | 395 | * Determine the ethernet speed (10/100/1000). Return 10 on error. |
c609719b | 396 | */ |
5700bb63 | 397 | int miiphy_speed(const char *devname, unsigned char addr) |
c609719b | 398 | { |
8c83c030 | 399 | u16 bmcr, anlpar, adv; |
c609719b | 400 | |
6fb6af6d | 401 | #if defined(CONFIG_PHY_GIGE) |
71bc6e64 LJ |
402 | u16 btsr; |
403 | ||
404 | /* | |
405 | * Check for 1000BASE-X. If it is supported, then assume that the speed | |
406 | * is 1000. | |
407 | */ | |
16a53238 | 408 | if (miiphy_is_1000base_x(devname, addr)) |
71bc6e64 | 409 | return _1000BASET; |
16a53238 | 410 | |
71bc6e64 LJ |
411 | /* |
412 | * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set. | |
413 | */ | |
414 | /* Check for 1000BASE-T. */ | |
16a53238 AF |
415 | if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) { |
416 | printf("PHY 1000BT status"); | |
71bc6e64 LJ |
417 | goto miiphy_read_failed; |
418 | } | |
419 | if (btsr != 0xFFFF && | |
16a53238 | 420 | (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))) |
71bc6e64 | 421 | return _1000BASET; |
6fb6af6d | 422 | #endif /* CONFIG_PHY_GIGE */ |
855a496f | 423 | |
a56bd922 | 424 | /* Check Basic Management Control Register first. */ |
16a53238 AF |
425 | if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { |
426 | printf("PHY speed"); | |
71bc6e64 | 427 | goto miiphy_read_failed; |
c609719b | 428 | } |
a56bd922 | 429 | /* Check if auto-negotiation is on. */ |
8ef583a0 | 430 | if (bmcr & BMCR_ANENABLE) { |
a56bd922 | 431 | /* Get auto-negotiation results. */ |
16a53238 AF |
432 | if (miiphy_read(devname, addr, MII_LPA, &anlpar)) { |
433 | printf("PHY AN speed"); | |
71bc6e64 | 434 | goto miiphy_read_failed; |
a56bd922 | 435 | } |
8c83c030 DL |
436 | |
437 | if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) { | |
438 | puts("PHY AN adv speed"); | |
439 | goto miiphy_read_failed; | |
440 | } | |
441 | return ((anlpar & adv) & LPA_100) ? _100BASET : _10BASET; | |
a56bd922 WD |
442 | } |
443 | /* Get speed from basic control settings. */ | |
8ef583a0 | 444 | return (bmcr & BMCR_SPEED100) ? _100BASET : _10BASET; |
a56bd922 | 445 | |
5f841959 | 446 | miiphy_read_failed: |
16a53238 | 447 | printf(" read failed, assuming 10BASE-T\n"); |
71bc6e64 | 448 | return _10BASET; |
c609719b WD |
449 | } |
450 | ||
c609719b WD |
451 | /***************************************************************************** |
452 | * | |
71bc6e64 | 453 | * Determine full/half duplex. Return half on error. |
c609719b | 454 | */ |
5700bb63 | 455 | int miiphy_duplex(const char *devname, unsigned char addr) |
c609719b | 456 | { |
8c83c030 | 457 | u16 bmcr, anlpar, adv; |
c609719b | 458 | |
6fb6af6d | 459 | #if defined(CONFIG_PHY_GIGE) |
71bc6e64 LJ |
460 | u16 btsr; |
461 | ||
462 | /* Check for 1000BASE-X. */ | |
16a53238 | 463 | if (miiphy_is_1000base_x(devname, addr)) { |
71bc6e64 | 464 | /* 1000BASE-X */ |
16a53238 AF |
465 | if (miiphy_read(devname, addr, MII_LPA, &anlpar)) { |
466 | printf("1000BASE-X PHY AN duplex"); | |
71bc6e64 LJ |
467 | goto miiphy_read_failed; |
468 | } | |
469 | } | |
470 | /* | |
471 | * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set. | |
472 | */ | |
473 | /* Check for 1000BASE-T. */ | |
16a53238 AF |
474 | if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) { |
475 | printf("PHY 1000BT status"); | |
71bc6e64 LJ |
476 | goto miiphy_read_failed; |
477 | } | |
478 | if (btsr != 0xFFFF) { | |
479 | if (btsr & PHY_1000BTSR_1000FD) { | |
480 | return FULL; | |
481 | } else if (btsr & PHY_1000BTSR_1000HD) { | |
482 | return HALF; | |
855a496f WD |
483 | } |
484 | } | |
6fb6af6d | 485 | #endif /* CONFIG_PHY_GIGE */ |
855a496f | 486 | |
a56bd922 | 487 | /* Check Basic Management Control Register first. */ |
16a53238 AF |
488 | if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { |
489 | puts("PHY duplex"); | |
71bc6e64 | 490 | goto miiphy_read_failed; |
c609719b | 491 | } |
a56bd922 | 492 | /* Check if auto-negotiation is on. */ |
8ef583a0 | 493 | if (bmcr & BMCR_ANENABLE) { |
a56bd922 | 494 | /* Get auto-negotiation results. */ |
16a53238 AF |
495 | if (miiphy_read(devname, addr, MII_LPA, &anlpar)) { |
496 | puts("PHY AN duplex"); | |
71bc6e64 | 497 | goto miiphy_read_failed; |
a56bd922 | 498 | } |
8c83c030 DL |
499 | |
500 | if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) { | |
501 | puts("PHY AN adv duplex"); | |
502 | goto miiphy_read_failed; | |
503 | } | |
504 | return ((anlpar & adv) & (LPA_10FULL | LPA_100FULL)) ? | |
71bc6e64 | 505 | FULL : HALF; |
a56bd922 WD |
506 | } |
507 | /* Get speed from basic control settings. */ | |
8ef583a0 | 508 | return (bmcr & BMCR_FULLDPLX) ? FULL : HALF; |
71bc6e64 | 509 | |
5f841959 | 510 | miiphy_read_failed: |
16a53238 | 511 | printf(" read failed, assuming half duplex\n"); |
71bc6e64 LJ |
512 | return HALF; |
513 | } | |
a56bd922 | 514 | |
71bc6e64 LJ |
515 | /***************************************************************************** |
516 | * | |
517 | * Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/ | |
518 | * 1000BASE-T, or on error. | |
519 | */ | |
5700bb63 | 520 | int miiphy_is_1000base_x(const char *devname, unsigned char addr) |
71bc6e64 LJ |
521 | { |
522 | #if defined(CONFIG_PHY_GIGE) | |
523 | u16 exsr; | |
524 | ||
16a53238 AF |
525 | if (miiphy_read(devname, addr, MII_ESTATUS, &exsr)) { |
526 | printf("PHY extended status read failed, assuming no " | |
71bc6e64 LJ |
527 | "1000BASE-X\n"); |
528 | return 0; | |
529 | } | |
8ef583a0 | 530 | return 0 != (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)); |
71bc6e64 LJ |
531 | #else |
532 | return 0; | |
533 | #endif | |
c609719b WD |
534 | } |
535 | ||
6d0f6bcf | 536 | #ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
fc3e2165 WD |
537 | /***************************************************************************** |
538 | * | |
539 | * Determine link status | |
540 | */ | |
5700bb63 | 541 | int miiphy_link(const char *devname, unsigned char addr) |
fc3e2165 WD |
542 | { |
543 | unsigned short reg; | |
544 | ||
a3d991bd | 545 | /* dummy read; needed to latch some phys */ |
16a53238 AF |
546 | (void)miiphy_read(devname, addr, MII_BMSR, ®); |
547 | if (miiphy_read(devname, addr, MII_BMSR, ®)) { | |
548 | puts("MII_BMSR read failed, assuming no link\n"); | |
549 | return 0; | |
fc3e2165 WD |
550 | } |
551 | ||
552 | /* Determine if a link is active */ | |
8ef583a0 | 553 | if ((reg & BMSR_LSTATUS) != 0) { |
16a53238 | 554 | return 1; |
fc3e2165 | 555 | } else { |
16a53238 | 556 | return 0; |
fc3e2165 WD |
557 | } |
558 | } | |
559 | #endif |