[thirdparty/u-boot.git] / common / miiphyutil.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2001
 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
 */

/*
 * This provides a bit-banged interface to the ethernet MII management
 * channel.
 */

#include <common.h>
#include <dm.h>
#include <miiphy.h>
#include <phy.h>

#include <asm/types.h>
#include <linux/list.h>
#include <malloc.h>
#include <net.h>

/* local debug macro */
#undef MII_DEBUG

#undef debug
#ifdef MII_DEBUG
#define debug(fmt, args...)	printf(fmt, ##args)
#else
#define debug(fmt, args...)
#endif /* MII_DEBUG */

static struct list_head mii_devs;
static struct mii_dev *current_mii;

/*
 * Lookup the mii_dev struct by the registered device name.
 */
struct mii_dev *miiphy_get_dev_by_name(const char *devname)
{
	struct list_head *entry;
	struct mii_dev *dev;

	if (!devname) {
		printf("NULL device name!\n");
		return NULL;
	}

	list_for_each(entry, &mii_devs) {
		dev = list_entry(entry, struct mii_dev, link);
		if (strcmp(dev->name, devname) == 0)
			return dev;
	}

	return NULL;
}

/*****************************************************************************
 *
 * Initialize global data. Need to be called before any other miiphy routine.
 */
void miiphy_init(void)
{
	INIT_LIST_HEAD(&mii_devs);
	current_mii = NULL;
}

struct mii_dev *mdio_alloc(void)
{
	struct mii_dev *bus;

	bus = malloc(sizeof(*bus));
	if (!bus)
		return bus;

	memset(bus, 0, sizeof(*bus));

	/* initalize mii_dev struct fields */
	INIT_LIST_HEAD(&bus->link);

	return bus;
}

void mdio_free(struct mii_dev *bus)
{
	free(bus);
}

int mdio_register(struct mii_dev *bus)
{
	if (!bus || !bus->read || !bus->write)
		return -1;

	/* check if we have unique name */
	if (miiphy_get_dev_by_name(bus->name)) {
		printf("mdio_register: non unique device name '%s'\n",
			bus->name);
		return -1;
	}

	/* add it to the list */
	list_add_tail(&bus->link, &mii_devs);

	if (!current_mii)
		current_mii = bus;

	return 0;
}

int mdio_register_seq(struct mii_dev *bus, int seq)
{
	int ret;

	/* Setup a unique name for each mdio bus */
	ret = snprintf(bus->name, MDIO_NAME_LEN, "eth%d", seq);
	if (ret < 0)
		return ret;

	return mdio_register(bus);
}

int mdio_unregister(struct mii_dev *bus)
{
	if (!bus)
		return 0;

	/* delete it from the list */
	list_del(&bus->link);

	if (current_mii == bus)
		current_mii = NULL;

	return 0;
}

void mdio_list_devices(void)
{
	struct list_head *entry;

	list_for_each(entry, &mii_devs) {
		int i;
		struct mii_dev *bus = list_entry(entry, struct mii_dev, link);

		printf("%s:\n", bus->name);

		for (i = 0; i < PHY_MAX_ADDR; i++) {
			struct phy_device *phydev = bus->phymap[i];

			if (phydev) {
				printf("%x - %s", i, phydev->drv->name);

				if (phydev->dev)
					printf(" <--> %s\n", phydev->dev->name);
				else
					printf("\n");
			}
		}
	}
}

int miiphy_set_current_dev(const char *devname)
{
	struct mii_dev *dev;

	dev = miiphy_get_dev_by_name(devname);
	if (dev) {
		current_mii = dev;
		return 0;
	}

	printf("No such device: %s\n", devname);

	return 1;
}

struct mii_dev *mdio_get_current_dev(void)
{
	return current_mii;
}

struct phy_device *mdio_phydev_for_ethname(const char *ethname)
{
	struct list_head *entry;
	struct mii_dev *bus;

	list_for_each(entry, &mii_devs) {
		int i;
		bus = list_entry(entry, struct mii_dev, link);

		for (i = 0; i < PHY_MAX_ADDR; i++) {
			if (!bus->phymap[i] || !bus->phymap[i]->dev)
				continue;

			if (strcmp(bus->phymap[i]->dev->name, ethname) == 0)
				return bus->phymap[i];
		}
	}

	printf("%s is not a known ethernet\n", ethname);
	return NULL;
}

const char *miiphy_get_current_dev(void)
{
	if (current_mii)
		return current_mii->name;

	return NULL;
}

static struct mii_dev *miiphy_get_active_dev(const char *devname)
{
	/* If the current mii is the one we want, return it */
	if (current_mii)
		if (strcmp(current_mii->name, devname) == 0)
			return current_mii;

	/* Otherwise, set the active one to the one we want */
	if (miiphy_set_current_dev(devname))
		return NULL;
	else
		return current_mii;
}

/*****************************************************************************
 *
 * Read to variable <value> from the PHY attached to device <devname>,
 * use PHY address <addr> and register <reg>.
 *
 * This API is deprecated. Use phy_read on a phy_device found via phy_connect
 *
 * Returns:
 *   0 on success
 */
int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
		 unsigned short *value)
{
	struct mii_dev *bus;
	int ret;

	bus = miiphy_get_active_dev(devname);
	if (!bus)
		return 1;

	ret = bus->read(bus, addr, MDIO_DEVAD_NONE, reg);
	if (ret < 0)
		return 1;

	*value = (unsigned short)ret;
	return 0;
}

/*****************************************************************************
 *
 * Write <value> to the PHY attached to device <devname>,
 * use PHY address <addr> and register <reg>.
 *
 * This API is deprecated. Use phy_write on a phy_device found by phy_connect
 *
 * Returns:
 *   0 on success
 */
int miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
		  unsigned short value)
{
	struct mii_dev *bus;

	bus = miiphy_get_active_dev(devname);
	if (bus)
		return bus->write(bus, addr, MDIO_DEVAD_NONE, reg, value);

	return 1;
}

/*****************************************************************************
 *
 * Print out list of registered MII capable devices.
 */
void miiphy_listdev(void)
{
	struct list_head *entry;
	struct mii_dev *dev;

	puts("MII devices: ");
	list_for_each(entry, &mii_devs) {
		dev = list_entry(entry, struct mii_dev, link);
		printf("'%s' ", dev->name);
	}
	puts("\n");

	if (current_mii)
		printf("Current device: '%s'\n", current_mii->name);
}

/*****************************************************************************
 *
 * Read the OUI, manufacture's model number, and revision number.
 *
 * OUI:     22 bits (unsigned int)
 * Model:    6 bits (unsigned char)
 * Revision: 4 bits (unsigned char)
 *
 * This API is deprecated.
 *
 * Returns:
 *   0 on success
 */
int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui,
		 unsigned char *model, unsigned char *rev)
{
	unsigned int reg = 0;
	unsigned short tmp;

	if (miiphy_read(devname, addr, MII_PHYSID2, &tmp) != 0) {
		debug("PHY ID register 2 read failed\n");
		return -1;
	}
	reg = tmp;

	debug("MII_PHYSID2 @ 0x%x = 0x%04x\n", addr, reg);

	if (reg == 0xFFFF) {
		/* No physical device present at this address */
		return -1;
	}

	if (miiphy_read(devname, addr, MII_PHYSID1, &tmp) != 0) {
		debug("PHY ID register 1 read failed\n");
		return -1;
	}
	reg |= tmp << 16;
	debug("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);

	*oui = (reg >> 10);
	*model = (unsigned char)((reg >> 4) & 0x0000003F);
	*rev = (unsigned char)(reg & 0x0000000F);
	return 0;
}

#ifndef CONFIG_PHYLIB
/*****************************************************************************
 *
 * Reset the PHY.
 *
 * This API is deprecated. Use PHYLIB.
 *
 * Returns:
 *   0 on success
 */
int miiphy_reset(const char *devname, unsigned char addr)
{
	unsigned short reg;
	int timeout = 500;

	if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
		debug("PHY status read failed\n");
		return -1;
	}
	if (miiphy_write(devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) {
		debug("PHY reset failed\n");
		return -1;
	}
#ifdef CONFIG_PHY_RESET_DELAY
	udelay(CONFIG_PHY_RESET_DELAY);	/* Intel LXT971A needs this */
#endif
	/*
	 * Poll the control register for the reset bit to go to 0 (it is
	 * auto-clearing).  This should happen within 0.5 seconds per the
	 * IEEE spec.
	 */
	reg = 0x8000;
	while (((reg & 0x8000) != 0) && timeout--) {
		if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
			debug("PHY status read failed\n");
			return -1;
		}
		udelay(1000);
	}
	if ((reg & 0x8000) == 0) {
		return 0;
	} else {
		puts("PHY reset timed out\n");
		return -1;
	}
	return 0;
}
#endif /* !PHYLIB */

/*****************************************************************************
 *
 * Determine the ethernet speed (10/100/1000).  Return 10 on error.
 */
int miiphy_speed(const char *devname, unsigned char addr)
{
	u16 bmcr, anlpar, adv;

#if defined(CONFIG_PHY_GIGE)
	u16 btsr;

	/*
	 * Check for 1000BASE-X.  If it is supported, then assume that the speed
	 * is 1000.
	 */
	if (miiphy_is_1000base_x(devname, addr))
		return _1000BASET;

	/*
	 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
	 */
	/* Check for 1000BASE-T. */
	if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) {
		printf("PHY 1000BT status");
		goto miiphy_read_failed;
	}
	if (btsr != 0xFFFF &&
			(btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)))
		return _1000BASET;
#endif /* CONFIG_PHY_GIGE */

	/* Check Basic Management Control Register first. */
	if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
		printf("PHY speed");
		goto miiphy_read_failed;
	}
	/* Check if auto-negotiation is on. */
	if (bmcr & BMCR_ANENABLE) {
		/* Get auto-negotiation results. */
		if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
			printf("PHY AN speed");
			goto miiphy_read_failed;
		}

		if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) {
			puts("PHY AN adv speed");
			goto miiphy_read_failed;
		}
		return ((anlpar & adv) & LPA_100) ? _100BASET : _10BASET;
	}
	/* Get speed from basic control settings. */
	return (bmcr & BMCR_SPEED100) ? _100BASET : _10BASET;

miiphy_read_failed:
	printf(" read failed, assuming 10BASE-T\n");
	return _10BASET;
}

/*****************************************************************************
 *
 * Determine full/half duplex.  Return half on error.
 */
int miiphy_duplex(const char *devname, unsigned char addr)
{
	u16 bmcr, anlpar, adv;

#if defined(CONFIG_PHY_GIGE)
	u16 btsr;

	/* Check for 1000BASE-X. */
	if (miiphy_is_1000base_x(devname, addr)) {
		/* 1000BASE-X */
		if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
			printf("1000BASE-X PHY AN duplex");
			goto miiphy_read_failed;
		}
	}
	/*
	 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
	 */
	/* Check for 1000BASE-T. */
	if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) {
		printf("PHY 1000BT status");
		goto miiphy_read_failed;
	}
	if (btsr != 0xFFFF) {
		if (btsr & PHY_1000BTSR_1000FD) {
			return FULL;
		} else if (btsr & PHY_1000BTSR_1000HD) {
			return HALF;
		}
	}
#endif /* CONFIG_PHY_GIGE */

	/* Check Basic Management Control Register first. */
	if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
		puts("PHY duplex");
		goto miiphy_read_failed;
	}
	/* Check if auto-negotiation is on. */
	if (bmcr & BMCR_ANENABLE) {
		/* Get auto-negotiation results. */
		if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
			puts("PHY AN duplex");
			goto miiphy_read_failed;
		}

		if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) {
			puts("PHY AN adv duplex");
			goto miiphy_read_failed;
		}
		return ((anlpar & adv) & (LPA_10FULL | LPA_100FULL)) ?
		    FULL : HALF;
	}
	/* Get speed from basic control settings. */
	return (bmcr & BMCR_FULLDPLX) ? FULL : HALF;

miiphy_read_failed:
	printf(" read failed, assuming half duplex\n");
	return HALF;
}

/*****************************************************************************
 *
 * Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/
 * 1000BASE-T, or on error.
 */
int miiphy_is_1000base_x(const char *devname, unsigned char addr)
{
#if defined(CONFIG_PHY_GIGE)
	u16 exsr;

	if (miiphy_read(devname, addr, MII_ESTATUS, &exsr)) {
		printf("PHY extended status read failed, assuming no "
			"1000BASE-X\n");
		return 0;
	}
	return 0 != (exsr & (ESTATUS_1000XF | ESTATUS_1000XH));
#else
	return 0;
#endif
}

#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/*****************************************************************************
 *
 * Determine link status
 */
int miiphy_link(const char *devname, unsigned char addr)
{
	unsigned short reg;

	/* dummy read; needed to latch some phys */
	(void)miiphy_read(devname, addr, MII_BMSR, &reg);
	if (miiphy_read(devname, addr, MII_BMSR, &reg)) {
		puts("MII_BMSR read failed, assuming no link\n");
		return 0;
	}

	/* Determine if a link is active */
	if ((reg & BMSR_LSTATUS) != 0) {
		return 1;
	} else {
		return 0;
	}
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
c609719b WD	2	/*
	3	* (C) Copyright 2001
	4	* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
c609719b WD	5	*/
	6
	7	/*
	8	* This provides a bit-banged interface to the ethernet MII management
	9	* channel.
	10	*/
	11
	12	#include <common.h>
c74c8e66	13	#include <dm.h>
c609719b	14	#include <miiphy.h>
5f184715	15	#include <phy.h>
c609719b	16
63ff004c MB	17	#include <asm/types.h>
	18	#include <linux/list.h>
	19	#include <malloc.h>
	20	#include <net.h>
	21
	22	/* local debug macro */
63ff004c MB	23	#undef MII_DEBUG
	24
	25	#undef debug
	26	#ifdef MII_DEBUG
16a53238	27	#define debug(fmt, args...) printf(fmt, ##args)
63ff004c	28	#else
16a53238	29	#define debug(fmt, args...)
63ff004c MB	30	#endif /* MII_DEBUG */
63ff004c MB	31
63ff004c MB	32	static struct list_head mii_devs;
	33	static struct mii_dev *current_mii;
	34
0daac978 MF	35	/*
	36	* Lookup the mii_dev struct by the registered device name.
	37	*/
5f184715	38	struct mii_dev miiphy_get_dev_by_name(const char devname)
0daac978 MF	39	{
	40	struct list_head *entry;
	41	struct mii_dev *dev;
	42
	43	if (!devname) {
	44	printf("NULL device name!\n");
	45	return NULL;
	46	}
	47
	48	list_for_each(entry, &mii_devs) {
	49	dev = list_entry(entry, struct mii_dev, link);
	50	if (strcmp(dev->name, devname) == 0)
	51	return dev;
	52	}
	53
0daac978 MF	54	return NULL;
	55	}
	56
d9785c14 MB	57	/*****************************************************************************
	58	*
	59	* Initialize global data. Need to be called before any other miiphy routine.
	60	*/
5700bb63	61	void miiphy_init(void)
d9785c14	62	{
16a53238	63	INIT_LIST_HEAD(&mii_devs);
298035df	64	current_mii = NULL;
d9785c14 MB	65	}
d9785c14 MB	66
5f184715 AF	67	struct mii_dev *mdio_alloc(void)
	68	{
	69	struct mii_dev *bus;
	70
	71	bus = malloc(sizeof(*bus));
	72	if (!bus)
	73	return bus;
	74
	75	memset(bus, 0, sizeof(*bus));
	76
	77	/* initalize mii_dev struct fields */
	78	INIT_LIST_HEAD(&bus->link);
	79
	80	return bus;
	81	}
	82
cb6baca7 BM	83	void mdio_free(struct mii_dev *bus)
	84	{
	85	free(bus);
	86	}
	87
5f184715 AF	88	int mdio_register(struct mii_dev *bus)
5f184715 AF	89	{
d39449b1	90	if (!bus \|\| !bus->read \|\| !bus->write)
5f184715 AF	91	return -1;
	92
	93	/* check if we have unique name */
	94	if (miiphy_get_dev_by_name(bus->name)) {
	95	printf("mdio_register: non unique device name '%s'\n",
	96	bus->name);
	97	return -1;
	98	}
	99
	100	/* add it to the list */
	101	list_add_tail(&bus->link, &mii_devs);
	102
	103	if (!current_mii)
	104	current_mii = bus;
	105
	106	return 0;
	107	}
	108
79e2a6a0 MS	109	int mdio_register_seq(struct mii_dev *bus, int seq)
	110	{
	111	int ret;
	112
	113	/* Setup a unique name for each mdio bus */
	114	ret = snprintf(bus->name, MDIO_NAME_LEN, "eth%d", seq);
	115	if (ret < 0)
	116	return ret;
	117
	118	return mdio_register(bus);
	119	}
	120
cb6baca7 BM	121	int mdio_unregister(struct mii_dev *bus)
	122	{
	123	if (!bus)
	124	return 0;
	125
	126	/* delete it from the list */
	127	list_del(&bus->link);
	128
	129	if (current_mii == bus)
	130	current_mii = NULL;
	131
	132	return 0;
	133	}
	134
5f184715 AF	135	void mdio_list_devices(void)
	136	{
	137	struct list_head *entry;
	138
	139	list_for_each(entry, &mii_devs) {
	140	int i;
	141	struct mii_dev *bus = list_entry(entry, struct mii_dev, link);
	142
	143	printf("%s:\n", bus->name);
	144
	145	for (i = 0; i < PHY_MAX_ADDR; i++) {
	146	struct phy_device *phydev = bus->phymap[i];
	147
	148	if (phydev) {
15a2acdf	149	printf("%x - %s", i, phydev->drv->name);
5f184715 AF	150
	151	if (phydev->dev)
	152	printf(" <--> %s\n", phydev->dev->name);
	153	else
	154	printf("\n");
	155	}
	156	}
	157	}
	158	}
	159
5700bb63	160	int miiphy_set_current_dev(const char *devname)
63ff004c	161	{
63ff004c MB	162	struct mii_dev *dev;
63ff004c MB	163
5f184715	164	dev = miiphy_get_dev_by_name(devname);
0daac978 MF	165	if (dev) {
	166	current_mii = dev;
	167	return 0;
63ff004c MB	168	}
63ff004c MB	169
5f184715 AF	170	printf("No such device: %s\n", devname);
5f184715 AF	171
63ff004c MB	172	return 1;
	173	}
	174
5f184715 AF	175	struct mii_dev *mdio_get_current_dev(void)
	176	{
	177	return current_mii;
	178	}
	179
	180	struct phy_device mdio_phydev_for_ethname(const char ethname)
	181	{
	182	struct list_head *entry;
	183	struct mii_dev *bus;
	184
	185	list_for_each(entry, &mii_devs) {
	186	int i;
	187	bus = list_entry(entry, struct mii_dev, link);
	188
	189	for (i = 0; i < PHY_MAX_ADDR; i++) {
	190	if (!bus->phymap[i] \|\| !bus->phymap[i]->dev)
	191	continue;
	192
	193	if (strcmp(bus->phymap[i]->dev->name, ethname) == 0)
	194	return bus->phymap[i];
	195	}
	196	}
	197
	198	printf("%s is not a known ethernet\n", ethname);
	199	return NULL;
	200	}
	201
5700bb63	202	const char *miiphy_get_current_dev(void)
63ff004c MB	203	{
	204	if (current_mii)
	205	return current_mii->name;
	206
	207	return NULL;
	208	}
	209
ede16ea3 MF	210	static struct mii_dev miiphy_get_active_dev(const char devname)
	211	{
	212	/* If the current mii is the one we want, return it */
	213	if (current_mii)
	214	if (strcmp(current_mii->name, devname) == 0)
	215	return current_mii;
	216
	217	/* Otherwise, set the active one to the one we want */
	218	if (miiphy_set_current_dev(devname))
	219	return NULL;
	220	else
	221	return current_mii;
	222	}
	223
63ff004c MB	224	/*****************************************************************************
	225	*
	226	* Read to variable <value> from the PHY attached to device <devname>,
	227	* use PHY address <addr> and register <reg>.
	228	*
1cdabc4b AF	229	* This API is deprecated. Use phy_read on a phy_device found via phy_connect
1cdabc4b AF	230	*
63ff004c MB	231	* Returns:
	232	* 0 on success
	233	*/
f915c931	234	int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
298035df	235	unsigned short *value)
63ff004c	236	{
5f184715	237	struct mii_dev *bus;
d67d5d52	238	int ret;
63ff004c	239
5f184715	240	bus = miiphy_get_active_dev(devname);
d67d5d52	241	if (!bus)
5f184715	242	return 1;
63ff004c	243
d67d5d52 AG	244	ret = bus->read(bus, addr, MDIO_DEVAD_NONE, reg);
	245	if (ret < 0)
	246	return 1;
	247
	248	*value = (unsigned short)ret;
	249	return 0;
63ff004c MB	250	}
	251
	252	/*****************************************************************************
	253	*
	254	* Write <value> to the PHY attached to device <devname>,
	255	* use PHY address <addr> and register <reg>.
	256	*
1cdabc4b AF	257	* This API is deprecated. Use phy_write on a phy_device found by phy_connect
1cdabc4b AF	258	*
63ff004c MB	259	* Returns:
	260	* 0 on success
	261	*/
f915c931	262	int miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
298035df	263	unsigned short value)
63ff004c	264	{
5f184715	265	struct mii_dev *bus;
63ff004c	266
5f184715 AF	267	bus = miiphy_get_active_dev(devname);
	268	if (bus)
	269	return bus->write(bus, addr, MDIO_DEVAD_NONE, reg, value);
63ff004c	270
0daac978	271	return 1;
63ff004c MB	272	}
	273
	274	/*****************************************************************************
	275	*
	276	* Print out list of registered MII capable devices.
	277	*/
16a53238	278	void miiphy_listdev(void)
63ff004c MB	279	{
	280	struct list_head *entry;
	281	struct mii_dev *dev;
	282
16a53238 AF	283	puts("MII devices: ");
	284	list_for_each(entry, &mii_devs) {
	285	dev = list_entry(entry, struct mii_dev, link);
	286	printf("'%s' ", dev->name);
63ff004c	287	}
16a53238	288	puts("\n");
63ff004c MB	289
63ff004c MB	290	if (current_mii)
16a53238	291	printf("Current device: '%s'\n", current_mii->name);
63ff004c MB	292	}
63ff004c MB	293
c609719b WD	294	/*****************************************************************************
	295	*
	296	* Read the OUI, manufacture's model number, and revision number.
	297	*
	298	* OUI: 22 bits (unsigned int)
	299	* Model: 6 bits (unsigned char)
	300	* Revision: 4 bits (unsigned char)
	301	*
1cdabc4b AF	302	* This API is deprecated.
1cdabc4b AF	303	*
c609719b WD	304	* Returns:
	305	* 0 on success
	306	*/
5700bb63	307	int miiphy_info(const char devname, unsigned char addr, unsigned int oui,
c609719b WD	308	unsigned char model, unsigned char rev)
	309	{
	310	unsigned int reg = 0;
8bf3b005	311	unsigned short tmp;
c609719b	312
16a53238 AF	313	if (miiphy_read(devname, addr, MII_PHYSID2, &tmp) != 0) {
	314	debug("PHY ID register 2 read failed\n");
	315	return -1;
c609719b	316	}
8bf3b005	317	reg = tmp;
c609719b	318
16a53238	319	debug("MII_PHYSID2 @ 0x%x = 0x%04x\n", addr, reg);
26c7bab8	320
c609719b WD	321	if (reg == 0xFFFF) {
c609719b WD	322	/* No physical device present at this address */
16a53238	323	return -1;
c609719b WD	324	}
c609719b WD	325
16a53238 AF	326	if (miiphy_read(devname, addr, MII_PHYSID1, &tmp) != 0) {
	327	debug("PHY ID register 1 read failed\n");
	328	return -1;
c609719b	329	}
8bf3b005	330	reg \|= tmp << 16;
16a53238	331	debug("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
26c7bab8	332
298035df LJ	333	*oui = (reg >> 10);
	334	*model = (unsigned char)((reg >> 4) & 0x0000003F);
	335	*rev = (unsigned char)(reg & 0x0000000F);
16a53238	336	return 0;
c609719b WD	337	}
c609719b WD	338
5f184715	339	#ifndef CONFIG_PHYLIB
c609719b WD	340	/*****************************************************************************
	341	*
	342	* Reset the PHY.
1cdabc4b AF	343	*
	344	* This API is deprecated. Use PHYLIB.
	345	*
c609719b WD	346	* Returns:
	347	* 0 on success
	348	*/
5700bb63	349	int miiphy_reset(const char *devname, unsigned char addr)
c609719b WD	350	{
c609719b WD	351	unsigned short reg;
ab5a0dcb	352	int timeout = 500;
c609719b	353
16a53238 AF	354	if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
	355	debug("PHY status read failed\n");
	356	return -1;
f89920c3	357	}
16a53238 AF	358	if (miiphy_write(devname, addr, MII_BMCR, reg \| BMCR_RESET) != 0) {
	359	debug("PHY reset failed\n");
	360	return -1;
c609719b	361	}
5653fc33	362	#ifdef CONFIG_PHY_RESET_DELAY
16a53238	363	udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
5653fc33	364	#endif
c609719b WD	365	/*
	366	* Poll the control register for the reset bit to go to 0 (it is
	367	* auto-clearing). This should happen within 0.5 seconds per the
	368	* IEEE spec.
	369	*/
c609719b	370	reg = 0x8000;
ab5a0dcb	371	while (((reg & 0x8000) != 0) && timeout--) {
8ef583a0	372	if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
ab5a0dcb SR	373	debug("PHY status read failed\n");
ab5a0dcb SR	374	return -1;
c609719b	375	}
ab5a0dcb	376	udelay(1000);
c609719b WD	377	}
c609719b WD	378	if ((reg & 0x8000) == 0) {
16a53238	379	return 0;
c609719b	380	} else {
16a53238 AF	381	puts("PHY reset timed out\n");
16a53238 AF	382	return -1;
c609719b	383	}
16a53238	384	return 0;
c609719b	385	}
5f184715	386	#endif /* !PHYLIB */
c609719b	387
c609719b WD	388	/*****************************************************************************
c609719b WD	389	*
71bc6e64	390	* Determine the ethernet speed (10/100/1000). Return 10 on error.
c609719b	391	*/
5700bb63	392	int miiphy_speed(const char *devname, unsigned char addr)
c609719b	393	{
8c83c030	394	u16 bmcr, anlpar, adv;
c609719b	395
6fb6af6d	396	#if defined(CONFIG_PHY_GIGE)
71bc6e64 LJ	397	u16 btsr;
	398
	399	/*
	400	* Check for 1000BASE-X. If it is supported, then assume that the speed
	401	* is 1000.
	402	*/
16a53238	403	if (miiphy_is_1000base_x(devname, addr))
71bc6e64	404	return _1000BASET;
16a53238	405
71bc6e64 LJ	406	/*
	407	* No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
	408	*/
	409	/* Check for 1000BASE-T. */
16a53238 AF	410	if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) {
16a53238 AF	411	printf("PHY 1000BT status");
71bc6e64 LJ	412	goto miiphy_read_failed;
	413	}
	414	if (btsr != 0xFFFF &&
16a53238	415	(btsr & (PHY_1000BTSR_1000FD \| PHY_1000BTSR_1000HD)))
71bc6e64	416	return _1000BASET;
6fb6af6d	417	#endif /* CONFIG_PHY_GIGE */
855a496f	418
a56bd922	419	/* Check Basic Management Control Register first. */
16a53238 AF	420	if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
16a53238 AF	421	printf("PHY speed");
71bc6e64	422	goto miiphy_read_failed;
c609719b	423	}
a56bd922	424	/* Check if auto-negotiation is on. */
8ef583a0	425	if (bmcr & BMCR_ANENABLE) {
a56bd922	426	/* Get auto-negotiation results. */
16a53238 AF	427	if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
16a53238 AF	428	printf("PHY AN speed");
71bc6e64	429	goto miiphy_read_failed;
a56bd922	430	}
8c83c030 DL	431
	432	if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) {
	433	puts("PHY AN adv speed");
	434	goto miiphy_read_failed;
	435	}
	436	return ((anlpar & adv) & LPA_100) ? _100BASET : _10BASET;
a56bd922 WD	437	}
a56bd922 WD	438	/* Get speed from basic control settings. */
8ef583a0	439	return (bmcr & BMCR_SPEED100) ? _100BASET : _10BASET;
a56bd922	440
5f841959	441	miiphy_read_failed:
16a53238	442	printf(" read failed, assuming 10BASE-T\n");
71bc6e64	443	return _10BASET;
c609719b WD	444	}
c609719b WD	445
c609719b WD	446	/*****************************************************************************
c609719b WD	447	*
71bc6e64	448	* Determine full/half duplex. Return half on error.
c609719b	449	*/
5700bb63	450	int miiphy_duplex(const char *devname, unsigned char addr)
c609719b	451	{
8c83c030	452	u16 bmcr, anlpar, adv;
c609719b	453
6fb6af6d	454	#if defined(CONFIG_PHY_GIGE)
71bc6e64 LJ	455	u16 btsr;
	456
	457	/* Check for 1000BASE-X. */
16a53238	458	if (miiphy_is_1000base_x(devname, addr)) {
71bc6e64	459	/* 1000BASE-X */
16a53238 AF	460	if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
16a53238 AF	461	printf("1000BASE-X PHY AN duplex");
71bc6e64 LJ	462	goto miiphy_read_failed;
	463	}
	464	}
	465	/*
	466	* No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
	467	*/
	468	/* Check for 1000BASE-T. */
16a53238 AF	469	if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) {
16a53238 AF	470	printf("PHY 1000BT status");
71bc6e64 LJ	471	goto miiphy_read_failed;
	472	}
	473	if (btsr != 0xFFFF) {
	474	if (btsr & PHY_1000BTSR_1000FD) {
	475	return FULL;
	476	} else if (btsr & PHY_1000BTSR_1000HD) {
	477	return HALF;
855a496f WD	478	}
855a496f WD	479	}
6fb6af6d	480	#endif /* CONFIG_PHY_GIGE */
855a496f	481
a56bd922	482	/* Check Basic Management Control Register first. */
16a53238 AF	483	if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
16a53238 AF	484	puts("PHY duplex");
71bc6e64	485	goto miiphy_read_failed;
c609719b	486	}
a56bd922	487	/* Check if auto-negotiation is on. */
8ef583a0	488	if (bmcr & BMCR_ANENABLE) {
a56bd922	489	/* Get auto-negotiation results. */
16a53238 AF	490	if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
16a53238 AF	491	puts("PHY AN duplex");
71bc6e64	492	goto miiphy_read_failed;
a56bd922	493	}
8c83c030 DL	494
	495	if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) {
	496	puts("PHY AN adv duplex");
	497	goto miiphy_read_failed;
	498	}
	499	return ((anlpar & adv) & (LPA_10FULL \| LPA_100FULL)) ?
71bc6e64	500	FULL : HALF;
a56bd922 WD	501	}
a56bd922 WD	502	/* Get speed from basic control settings. */
8ef583a0	503	return (bmcr & BMCR_FULLDPLX) ? FULL : HALF;
71bc6e64	504
5f841959	505	miiphy_read_failed:
16a53238	506	printf(" read failed, assuming half duplex\n");
71bc6e64 LJ	507	return HALF;
71bc6e64 LJ	508	}
a56bd922	509
71bc6e64 LJ	510	/*****************************************************************************
	511	*
	512	* Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/
	513	* 1000BASE-T, or on error.
	514	*/
5700bb63	515	int miiphy_is_1000base_x(const char *devname, unsigned char addr)
71bc6e64 LJ	516	{
	517	#if defined(CONFIG_PHY_GIGE)
	518	u16 exsr;
	519
16a53238 AF	520	if (miiphy_read(devname, addr, MII_ESTATUS, &exsr)) {
16a53238 AF	521	printf("PHY extended status read failed, assuming no "
71bc6e64 LJ	522	"1000BASE-X\n");
	523	return 0;
	524	}
8ef583a0	525	return 0 != (exsr & (ESTATUS_1000XF \| ESTATUS_1000XH));
71bc6e64 LJ	526	#else
	527	return 0;
	528	#endif
c609719b WD	529	}
c609719b WD	530
6d0f6bcf	531	#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
fc3e2165 WD	532	/*****************************************************************************
	533	*
	534	* Determine link status
	535	*/
5700bb63	536	int miiphy_link(const char *devname, unsigned char addr)
fc3e2165 WD	537	{
	538	unsigned short reg;
	539
a3d991bd	540	/* dummy read; needed to latch some phys */
16a53238 AF	541	(void)miiphy_read(devname, addr, MII_BMSR, &reg);
	542	if (miiphy_read(devname, addr, MII_BMSR, &reg)) {
	543	puts("MII_BMSR read failed, assuming no link\n");
	544	return 0;
fc3e2165 WD	545	}
	546
	547	/* Determine if a link is active */
8ef583a0	548	if ((reg & BMSR_LSTATUS) != 0) {
16a53238	549	return 1;
fc3e2165	550	} else {
16a53238	551	return 0;
fc3e2165 WD	552	}
	553	}
	554	#endif