[thirdparty/u-boot.git] / common / miiphyutil.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2001
 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
 */

/*
 * This provides a bit-banged interface to the ethernet MII management
 * channel.
 */

#include <dm.h>
#include <log.h>
#include <miiphy.h>
#include <phy.h>
#include <linux/delay.h>

#include <asm/types.h>
#include <linux/list.h>
#include <malloc.h>
#include <net.h>

/* local debug macro */
#undef MII_DEBUG

#undef debug
#ifdef MII_DEBUG
#define debug(fmt, args...)	printf(fmt, ##args)
#else
#define debug(fmt, args...)
#endif /* MII_DEBUG */

static LIST_HEAD(mii_devs);
static struct mii_dev *current_mii;

/*
 * Lookup the mii_dev struct by the registered device name.
 */
struct mii_dev *miiphy_get_dev_by_name(const char *devname)
{
	struct list_head *entry;
	struct mii_dev *dev;

	if (!devname) {
		printf("NULL device name!\n");
		return NULL;
	}

	list_for_each(entry, &mii_devs) {
		dev = list_entry(entry, struct mii_dev, link);
		if (strcmp(dev->name, devname) == 0)
			return dev;
	}

	return NULL;
}

struct mii_dev *mdio_alloc(void)
{
	struct mii_dev *bus;

	bus = malloc(sizeof(*bus));
	if (!bus)
		return bus;

	memset(bus, 0, sizeof(*bus));

	/* initialize mii_dev struct fields */
	INIT_LIST_HEAD(&bus->link);

	return bus;
}

void mdio_free(struct mii_dev *bus)
{
	free(bus);
}

int mdio_register(struct mii_dev *bus)
{
	if (!bus || !bus->read || !bus->write)
		return -1;

	/* check if we have unique name */
	if (miiphy_get_dev_by_name(bus->name)) {
		printf("mdio_register: non unique device name '%s'\n",
			bus->name);
		return -1;
	}

	/* add it to the list */
	list_add_tail(&bus->link, &mii_devs);

	if (!current_mii)
		current_mii = bus;

	return 0;
}

int mdio_register_seq(struct mii_dev *bus, int seq)
{
	int ret;

	/* Setup a unique name for each mdio bus */
	ret = snprintf(bus->name, MDIO_NAME_LEN, "eth%d", seq);
	if (ret < 0)
		return ret;

	return mdio_register(bus);
}

int mdio_unregister(struct mii_dev *bus)
{
	if (!bus)
		return 0;

	/* delete it from the list */
	list_del(&bus->link);

	if (current_mii == bus)
		current_mii = NULL;

	return 0;
}

void mdio_list_devices(void)
{
	struct list_head *entry;

	list_for_each(entry, &mii_devs) {
		int i;
		struct mii_dev *bus = list_entry(entry, struct mii_dev, link);

		printf("%s:\n", bus->name);

		for (i = 0; i < PHY_MAX_ADDR; i++) {
			struct phy_device *phydev = bus->phymap[i];

			if (phydev) {
				printf("%x - %s", i, phydev->drv->name);

				if (phydev->dev)
					printf(" <--> %s\n", phydev->dev->name);
				else
					printf("\n");
			}
		}
	}
}

int miiphy_set_current_dev(const char *devname)
{
	struct mii_dev *dev;

	dev = miiphy_get_dev_by_name(devname);
	if (dev) {
		current_mii = dev;
		return 0;
	}

	printf("No such device: %s\n", devname);

	return 1;
}

struct mii_dev *mdio_get_current_dev(void)
{
	return current_mii;
}

struct list_head *mdio_get_list_head(void)
{
	return &mii_devs;
}

struct phy_device *mdio_phydev_for_ethname(const char *ethname)
{
	struct list_head *entry;
	struct mii_dev *bus;

	list_for_each(entry, &mii_devs) {
		int i;
		bus = list_entry(entry, struct mii_dev, link);

		for (i = 0; i < PHY_MAX_ADDR; i++) {
			if (!bus->phymap[i] || !bus->phymap[i]->dev)
				continue;

			if (strcmp(bus->phymap[i]->dev->name, ethname) == 0)
				return bus->phymap[i];
		}
	}

	printf("%s is not a known ethernet\n", ethname);
	return NULL;
}

const char *miiphy_get_current_dev(void)
{
	if (current_mii)
		return current_mii->name;

	return NULL;
}

static struct mii_dev *miiphy_get_active_dev(const char *devname)
{
	/* If the current mii is the one we want, return it */
	if (current_mii)
		if (strcmp(current_mii->name, devname) == 0)
			return current_mii;

	/* Otherwise, set the active one to the one we want */
	if (miiphy_set_current_dev(devname))
		return NULL;
	else
		return current_mii;
}

/*****************************************************************************
 *
 * Read to variable <value> from the PHY attached to device <devname>,
 * use PHY address <addr> and register <reg>.
 *
 * This API is deprecated. Use phy_read on a phy_device found via phy_connect
 *
 * Returns:
 *   0 on success
 */
int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
		 unsigned short *value)
{
	struct mii_dev *bus;
	int ret;

	bus = miiphy_get_active_dev(devname);
	if (!bus)
		return 1;

	ret = bus->read(bus, addr, MDIO_DEVAD_NONE, reg);
	if (ret < 0)
		return 1;

	*value = (unsigned short)ret;
	return 0;
}

/*****************************************************************************
 *
 * Write <value> to the PHY attached to device <devname>,
 * use PHY address <addr> and register <reg>.
 *
 * This API is deprecated. Use phy_write on a phy_device found by phy_connect
 *
 * Returns:
 *   0 on success
 */
int miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
		  unsigned short value)
{
	struct mii_dev *bus;

	bus = miiphy_get_active_dev(devname);
	if (bus)
		return bus->write(bus, addr, MDIO_DEVAD_NONE, reg, value);

	return 1;
}

/*****************************************************************************
 *
 * Print out list of registered MII capable devices.
 */
void miiphy_listdev(void)
{
	struct list_head *entry;
	struct mii_dev *dev;

	puts("MII devices: ");
	list_for_each(entry, &mii_devs) {
		dev = list_entry(entry, struct mii_dev, link);
		printf("'%s' ", dev->name);
	}
	puts("\n");

	if (current_mii)
		printf("Current device: '%s'\n", current_mii->name);
}

/*****************************************************************************
 *
 * Read the OUI, manufacture's model number, and revision number.
 *
 * OUI:     22 bits (unsigned int)
 * Model:    6 bits (unsigned char)
 * Revision: 4 bits (unsigned char)
 *
 * This API is deprecated.
 *
 * Returns:
 *   0 on success
 */
int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui,
		 unsigned char *model, unsigned char *rev)
{
	unsigned int reg = 0;
	unsigned short tmp;

	if (miiphy_read(devname, addr, MII_PHYSID2, &tmp) != 0) {
		debug("PHY ID register 2 read failed\n");
		return -1;
	}
	reg = tmp;

	debug("MII_PHYSID2 @ 0x%x = 0x%04x\n", addr, reg);

	if (reg == 0xFFFF) {
		/* No physical device present at this address */
		return -1;
	}

	if (miiphy_read(devname, addr, MII_PHYSID1, &tmp) != 0) {
		debug("PHY ID register 1 read failed\n");
		return -1;
	}
	reg |= tmp << 16;
	debug("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);

	*oui = (reg >> 10);
	*model = (unsigned char)((reg >> 4) & 0x0000003F);
	*rev = (unsigned char)(reg & 0x0000000F);
	return 0;
}

#ifndef CONFIG_PHYLIB
/*****************************************************************************
 *
 * Reset the PHY.
 *
 * This API is deprecated. Use PHYLIB.
 *
 * Returns:
 *   0 on success
 */
int miiphy_reset(const char *devname, unsigned char addr)
{
	unsigned short reg;
	int timeout = 500;

	if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
		debug("PHY status read failed\n");
		return -1;
	}
	if (miiphy_write(devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) {
		debug("PHY reset failed\n");
		return -1;
	}
#if CONFIG_PHY_RESET_DELAY > 0
	udelay(CONFIG_PHY_RESET_DELAY);	/* Intel LXT971A needs this */
#endif
	/*
	 * Poll the control register for the reset bit to go to 0 (it is
	 * auto-clearing).  This should happen within 0.5 seconds per the
	 * IEEE spec.
	 */
	reg = 0x8000;
	while (((reg & 0x8000) != 0) && timeout--) {
		if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
			debug("PHY status read failed\n");
			return -1;
		}
		udelay(1000);
	}
	if ((reg & 0x8000) == 0) {
		return 0;
	} else {
		puts("PHY reset timed out\n");
		return -1;
	}
	return 0;
}
#endif /* !PHYLIB */

/*****************************************************************************
 *
 * Determine the ethernet speed (10/100/1000).  Return 10 on error.
 */
int miiphy_speed(const char *devname, unsigned char addr)
{
	u16 bmcr, anlpar, adv;

#if defined(CONFIG_PHY_GIGE)
	u16 btsr;

	/*
	 * Check for 1000BASE-X.  If it is supported, then assume that the speed
	 * is 1000.
	 */
	if (miiphy_is_1000base_x(devname, addr))
		return _1000BASET;

	/*
	 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
	 */
	/* Check for 1000BASE-T. */
	if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) {
		printf("PHY 1000BT status");
		goto miiphy_read_failed;
	}
	if (btsr != 0xFFFF &&
			(btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)))
		return _1000BASET;
#endif /* CONFIG_PHY_GIGE */

	/* Check Basic Management Control Register first. */
	if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
		printf("PHY speed");
		goto miiphy_read_failed;
	}
	/* Check if auto-negotiation is on. */
	if (bmcr & BMCR_ANENABLE) {
		/* Get auto-negotiation results. */
		if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
			printf("PHY AN speed");
			goto miiphy_read_failed;
		}

		if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) {
			puts("PHY AN adv speed");
			goto miiphy_read_failed;
		}
		return ((anlpar & adv) & LPA_100) ? _100BASET : _10BASET;
	}
	/* Get speed from basic control settings. */
	return (bmcr & BMCR_SPEED100) ? _100BASET : _10BASET;

miiphy_read_failed:
	printf(" read failed, assuming 10BASE-T\n");
	return _10BASET;
}

/*****************************************************************************
 *
 * Determine full/half duplex.  Return half on error.
 */
int miiphy_duplex(const char *devname, unsigned char addr)
{
	u16 bmcr, anlpar, adv;

#if defined(CONFIG_PHY_GIGE)
	u16 btsr;

	/* Check for 1000BASE-X. */
	if (miiphy_is_1000base_x(devname, addr)) {
		/* 1000BASE-X */
		if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
			printf("1000BASE-X PHY AN duplex");
			goto miiphy_read_failed;
		}
	}
	/*
	 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
	 */
	/* Check for 1000BASE-T. */
	if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) {
		printf("PHY 1000BT status");
		goto miiphy_read_failed;
	}
	if (btsr != 0xFFFF) {
		if (btsr & PHY_1000BTSR_1000FD) {
			return FULL;
		} else if (btsr & PHY_1000BTSR_1000HD) {
			return HALF;
		}
	}
#endif /* CONFIG_PHY_GIGE */

	/* Check Basic Management Control Register first. */
	if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
		puts("PHY duplex");
		goto miiphy_read_failed;
	}
	/* Check if auto-negotiation is on. */
	if (bmcr & BMCR_ANENABLE) {
		/* Get auto-negotiation results. */
		if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
			puts("PHY AN duplex");
			goto miiphy_read_failed;
		}

		if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) {
			puts("PHY AN adv duplex");
			goto miiphy_read_failed;
		}
		return ((anlpar & adv) & (LPA_10FULL | LPA_100FULL)) ?
		    FULL : HALF;
	}
	/* Get speed from basic control settings. */
	return (bmcr & BMCR_FULLDPLX) ? FULL : HALF;

miiphy_read_failed:
	printf(" read failed, assuming half duplex\n");
	return HALF;
}

/*****************************************************************************
 *
 * Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/
 * 1000BASE-T, or on error.
 */
int miiphy_is_1000base_x(const char *devname, unsigned char addr)
{
#if defined(CONFIG_PHY_GIGE)
	u16 exsr;

	if (miiphy_read(devname, addr, MII_ESTATUS, &exsr)) {
		printf("PHY extended status read failed, assuming no "
			"1000BASE-X\n");
		return 0;
	}
	return 0 != (exsr & (ESTATUS_1000XF | ESTATUS_1000XH));
#else
	return 0;
#endif
}

#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/*****************************************************************************
 *
 * Determine link status
 */
int miiphy_link(const char *devname, unsigned char addr)
{
	unsigned short reg;

	/* dummy read; needed to latch some phys */
	(void)miiphy_read(devname, addr, MII_BMSR, &reg);
	if (miiphy_read(devname, addr, MII_BMSR, &reg)) {
		puts("MII_BMSR read failed, assuming no link\n");
		return 0;
	}

	/* Determine if a link is active */
	if ((reg & BMSR_LSTATUS) != 0) {
		return 1;
	} else {
		return 0;
	}
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
c609719b WD	2	/*
	3	* (C) Copyright 2001
	4	* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
c609719b WD	5	*/
	6
	7	/*
	8	* This provides a bit-banged interface to the ethernet MII management
	9	* channel.
	10	*/
	11
c74c8e66	12	#include <dm.h>
f7ae49fc	13	#include <log.h>
c609719b	14	#include <miiphy.h>
5f184715	15	#include <phy.h>
c05ed00a	16	#include <linux/delay.h>
c609719b	17
63ff004c MB	18	#include <asm/types.h>
	19	#include <linux/list.h>
	20	#include <malloc.h>
	21	#include <net.h>
	22
	23	/* local debug macro */
63ff004c MB	24	#undef MII_DEBUG
	25
	26	#undef debug
	27	#ifdef MII_DEBUG
16a53238	28	#define debug(fmt, args...) printf(fmt, ##args)
63ff004c	29	#else
16a53238	30	#define debug(fmt, args...)
63ff004c MB	31	#endif /* MII_DEBUG */
63ff004c MB	32
7e0370f3	33	static LIST_HEAD(mii_devs);
63ff004c MB	34	static struct mii_dev *current_mii;
63ff004c MB	35
0daac978 MF	36	/*
	37	* Lookup the mii_dev struct by the registered device name.
	38	*/
5f184715	39	struct mii_dev miiphy_get_dev_by_name(const char devname)
0daac978 MF	40	{
	41	struct list_head *entry;
	42	struct mii_dev *dev;
	43
	44	if (!devname) {
	45	printf("NULL device name!\n");
	46	return NULL;
	47	}
	48
	49	list_for_each(entry, &mii_devs) {
	50	dev = list_entry(entry, struct mii_dev, link);
	51	if (strcmp(dev->name, devname) == 0)
	52	return dev;
	53	}
	54
0daac978 MF	55	return NULL;
	56	}
	57
5f184715 AF	58	struct mii_dev *mdio_alloc(void)
	59	{
	60	struct mii_dev *bus;
	61
	62	bus = malloc(sizeof(*bus));
	63	if (!bus)
	64	return bus;
	65
33ccfae8 MV	66	memset(bus, 0, sizeof(*bus));
	67
	68	/* initialize mii_dev struct fields */
	69	INIT_LIST_HEAD(&bus->link);
5f184715 AF	70
	71	return bus;
	72	}
	73
cb6baca7 BM	74	void mdio_free(struct mii_dev *bus)
	75	{
	76	free(bus);
	77	}
	78
5f184715 AF	79	int mdio_register(struct mii_dev *bus)
5f184715 AF	80	{
d39449b1	81	if (!bus \|\| !bus->read \|\| !bus->write)
5f184715 AF	82	return -1;
	83
	84	/* check if we have unique name */
	85	if (miiphy_get_dev_by_name(bus->name)) {
	86	printf("mdio_register: non unique device name '%s'\n",
	87	bus->name);
	88	return -1;
	89	}
	90
	91	/* add it to the list */
	92	list_add_tail(&bus->link, &mii_devs);
	93
	94	if (!current_mii)
	95	current_mii = bus;
	96
	97	return 0;
	98	}
	99
79e2a6a0 MS	100	int mdio_register_seq(struct mii_dev *bus, int seq)
	101	{
	102	int ret;
	103
	104	/* Setup a unique name for each mdio bus */
	105	ret = snprintf(bus->name, MDIO_NAME_LEN, "eth%d", seq);
	106	if (ret < 0)
	107	return ret;
	108
	109	return mdio_register(bus);
	110	}
	111
cb6baca7 BM	112	int mdio_unregister(struct mii_dev *bus)
	113	{
	114	if (!bus)
	115	return 0;
	116
	117	/* delete it from the list */
	118	list_del(&bus->link);
	119
	120	if (current_mii == bus)
	121	current_mii = NULL;
	122
	123	return 0;
	124	}
	125
5f184715 AF	126	void mdio_list_devices(void)
	127	{
	128	struct list_head *entry;
	129
	130	list_for_each(entry, &mii_devs) {
	131	int i;
	132	struct mii_dev *bus = list_entry(entry, struct mii_dev, link);
	133
	134	printf("%s:\n", bus->name);
	135
	136	for (i = 0; i < PHY_MAX_ADDR; i++) {
	137	struct phy_device *phydev = bus->phymap[i];
	138
	139	if (phydev) {
15a2acdf	140	printf("%x - %s", i, phydev->drv->name);
5f184715 AF	141
	142	if (phydev->dev)
	143	printf(" <--> %s\n", phydev->dev->name);
	144	else
	145	printf("\n");
	146	}
	147	}
	148	}
	149	}
	150
5700bb63	151	int miiphy_set_current_dev(const char *devname)
63ff004c	152	{
63ff004c MB	153	struct mii_dev *dev;
63ff004c MB	154
5f184715	155	dev = miiphy_get_dev_by_name(devname);
0daac978 MF	156	if (dev) {
	157	current_mii = dev;
	158	return 0;
63ff004c MB	159	}
63ff004c MB	160
5f184715 AF	161	printf("No such device: %s\n", devname);
5f184715 AF	162
63ff004c MB	163	return 1;
	164	}
	165
5f184715 AF	166	struct mii_dev *mdio_get_current_dev(void)
	167	{
	168	return current_mii;
	169	}
	170
9215bb1f PB	171	struct list_head *mdio_get_list_head(void)
	172	{
	173	return &mii_devs;
	174	}
	175
5f184715 AF	176	struct phy_device mdio_phydev_for_ethname(const char ethname)
	177	{
	178	struct list_head *entry;
	179	struct mii_dev *bus;
	180
	181	list_for_each(entry, &mii_devs) {
	182	int i;
	183	bus = list_entry(entry, struct mii_dev, link);
	184
	185	for (i = 0; i < PHY_MAX_ADDR; i++) {
	186	if (!bus->phymap[i] \|\| !bus->phymap[i]->dev)
	187	continue;
	188
	189	if (strcmp(bus->phymap[i]->dev->name, ethname) == 0)
	190	return bus->phymap[i];
	191	}
	192	}
	193
	194	printf("%s is not a known ethernet\n", ethname);
	195	return NULL;
	196	}
	197
5700bb63	198	const char *miiphy_get_current_dev(void)
63ff004c MB	199	{
	200	if (current_mii)
	201	return current_mii->name;
	202
	203	return NULL;
	204	}
	205
ede16ea3 MF	206	static struct mii_dev miiphy_get_active_dev(const char devname)
	207	{
	208	/* If the current mii is the one we want, return it */
	209	if (current_mii)
	210	if (strcmp(current_mii->name, devname) == 0)
	211	return current_mii;
	212
	213	/* Otherwise, set the active one to the one we want */
	214	if (miiphy_set_current_dev(devname))
	215	return NULL;
	216	else
	217	return current_mii;
	218	}
	219
63ff004c MB	220	/*****************************************************************************
	221	*
	222	* Read to variable <value> from the PHY attached to device <devname>,
	223	* use PHY address <addr> and register <reg>.
	224	*
1cdabc4b AF	225	* This API is deprecated. Use phy_read on a phy_device found via phy_connect
1cdabc4b AF	226	*
63ff004c MB	227	* Returns:
	228	* 0 on success
	229	*/
f915c931	230	int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
298035df	231	unsigned short *value)
63ff004c	232	{
5f184715	233	struct mii_dev *bus;
d67d5d52	234	int ret;
63ff004c	235
5f184715	236	bus = miiphy_get_active_dev(devname);
d67d5d52	237	if (!bus)
5f184715	238	return 1;
63ff004c	239
d67d5d52 AG	240	ret = bus->read(bus, addr, MDIO_DEVAD_NONE, reg);
	241	if (ret < 0)
	242	return 1;
	243
	244	*value = (unsigned short)ret;
	245	return 0;
63ff004c MB	246	}
	247
	248	/*****************************************************************************
	249	*
	250	* Write <value> to the PHY attached to device <devname>,
	251	* use PHY address <addr> and register <reg>.
	252	*
1cdabc4b AF	253	* This API is deprecated. Use phy_write on a phy_device found by phy_connect
1cdabc4b AF	254	*
63ff004c MB	255	* Returns:
	256	* 0 on success
	257	*/
f915c931	258	int miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
298035df	259	unsigned short value)
63ff004c	260	{
5f184715	261	struct mii_dev *bus;
63ff004c	262
5f184715 AF	263	bus = miiphy_get_active_dev(devname);
	264	if (bus)
	265	return bus->write(bus, addr, MDIO_DEVAD_NONE, reg, value);
63ff004c	266
0daac978	267	return 1;
63ff004c MB	268	}
	269
	270	/*****************************************************************************
	271	*
	272	* Print out list of registered MII capable devices.
	273	*/
16a53238	274	void miiphy_listdev(void)
63ff004c MB	275	{
	276	struct list_head *entry;
	277	struct mii_dev *dev;
	278
16a53238 AF	279	puts("MII devices: ");
	280	list_for_each(entry, &mii_devs) {
	281	dev = list_entry(entry, struct mii_dev, link);
	282	printf("'%s' ", dev->name);
63ff004c	283	}
16a53238	284	puts("\n");
63ff004c MB	285
63ff004c MB	286	if (current_mii)
16a53238	287	printf("Current device: '%s'\n", current_mii->name);
63ff004c MB	288	}
63ff004c MB	289
c609719b WD	290	/*****************************************************************************
	291	*
	292	* Read the OUI, manufacture's model number, and revision number.
	293	*
	294	* OUI: 22 bits (unsigned int)
	295	* Model: 6 bits (unsigned char)
	296	* Revision: 4 bits (unsigned char)
	297	*
1cdabc4b AF	298	* This API is deprecated.
1cdabc4b AF	299	*
c609719b WD	300	* Returns:
	301	* 0 on success
	302	*/
5700bb63	303	int miiphy_info(const char devname, unsigned char addr, unsigned int oui,
c609719b WD	304	unsigned char model, unsigned char rev)
	305	{
	306	unsigned int reg = 0;
8bf3b005	307	unsigned short tmp;
c609719b	308
16a53238 AF	309	if (miiphy_read(devname, addr, MII_PHYSID2, &tmp) != 0) {
	310	debug("PHY ID register 2 read failed\n");
	311	return -1;
c609719b	312	}
8bf3b005	313	reg = tmp;
c609719b	314
16a53238	315	debug("MII_PHYSID2 @ 0x%x = 0x%04x\n", addr, reg);
26c7bab8	316
c609719b WD	317	if (reg == 0xFFFF) {
c609719b WD	318	/* No physical device present at this address */
16a53238	319	return -1;
c609719b WD	320	}
c609719b WD	321
16a53238 AF	322	if (miiphy_read(devname, addr, MII_PHYSID1, &tmp) != 0) {
	323	debug("PHY ID register 1 read failed\n");
	324	return -1;
c609719b	325	}
8bf3b005	326	reg \|= tmp << 16;
16a53238	327	debug("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
26c7bab8	328
298035df LJ	329	*oui = (reg >> 10);
	330	*model = (unsigned char)((reg >> 4) & 0x0000003F);
	331	*rev = (unsigned char)(reg & 0x0000000F);
16a53238	332	return 0;
c609719b WD	333	}
c609719b WD	334
5f184715	335	#ifndef CONFIG_PHYLIB
c609719b WD	336	/*****************************************************************************
	337	*
	338	* Reset the PHY.
1cdabc4b AF	339	*
	340	* This API is deprecated. Use PHYLIB.
	341	*
c609719b WD	342	* Returns:
	343	* 0 on success
	344	*/
5700bb63	345	int miiphy_reset(const char *devname, unsigned char addr)
c609719b WD	346	{
c609719b WD	347	unsigned short reg;
ab5a0dcb	348	int timeout = 500;
c609719b	349
16a53238 AF	350	if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
	351	debug("PHY status read failed\n");
	352	return -1;
f89920c3	353	}
16a53238 AF	354	if (miiphy_write(devname, addr, MII_BMCR, reg \| BMCR_RESET) != 0) {
	355	debug("PHY reset failed\n");
	356	return -1;
c609719b	357	}
16199a8b	358	#if CONFIG_PHY_RESET_DELAY > 0
16a53238	359	udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
5653fc33	360	#endif
c609719b WD	361	/*
	362	* Poll the control register for the reset bit to go to 0 (it is
	363	* auto-clearing). This should happen within 0.5 seconds per the
	364	* IEEE spec.
	365	*/
c609719b	366	reg = 0x8000;
ab5a0dcb	367	while (((reg & 0x8000) != 0) && timeout--) {
8ef583a0	368	if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
ab5a0dcb SR	369	debug("PHY status read failed\n");
ab5a0dcb SR	370	return -1;
c609719b	371	}
ab5a0dcb	372	udelay(1000);
c609719b WD	373	}
c609719b WD	374	if ((reg & 0x8000) == 0) {
16a53238	375	return 0;
c609719b	376	} else {
16a53238 AF	377	puts("PHY reset timed out\n");
16a53238 AF	378	return -1;
c609719b	379	}
16a53238	380	return 0;
c609719b	381	}
5f184715	382	#endif /* !PHYLIB */
c609719b	383
c609719b WD	384	/*****************************************************************************
c609719b WD	385	*
71bc6e64	386	* Determine the ethernet speed (10/100/1000). Return 10 on error.
c609719b	387	*/
5700bb63	388	int miiphy_speed(const char *devname, unsigned char addr)
c609719b	389	{
8c83c030	390	u16 bmcr, anlpar, adv;
c609719b	391
6fb6af6d	392	#if defined(CONFIG_PHY_GIGE)
71bc6e64 LJ	393	u16 btsr;
	394
	395	/*
	396	* Check for 1000BASE-X. If it is supported, then assume that the speed
	397	* is 1000.
	398	*/
16a53238	399	if (miiphy_is_1000base_x(devname, addr))
71bc6e64	400	return _1000BASET;
16a53238	401
71bc6e64 LJ	402	/*
	403	* No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
	404	*/
	405	/* Check for 1000BASE-T. */
16a53238 AF	406	if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) {
16a53238 AF	407	printf("PHY 1000BT status");
71bc6e64 LJ	408	goto miiphy_read_failed;
	409	}
	410	if (btsr != 0xFFFF &&
16a53238	411	(btsr & (PHY_1000BTSR_1000FD \| PHY_1000BTSR_1000HD)))
71bc6e64	412	return _1000BASET;
6fb6af6d	413	#endif /* CONFIG_PHY_GIGE */
855a496f	414
a56bd922	415	/* Check Basic Management Control Register first. */
16a53238 AF	416	if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
16a53238 AF	417	printf("PHY speed");
71bc6e64	418	goto miiphy_read_failed;
c609719b	419	}
a56bd922	420	/* Check if auto-negotiation is on. */
8ef583a0	421	if (bmcr & BMCR_ANENABLE) {
a56bd922	422	/* Get auto-negotiation results. */
16a53238 AF	423	if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
16a53238 AF	424	printf("PHY AN speed");
71bc6e64	425	goto miiphy_read_failed;
a56bd922	426	}
8c83c030 DL	427
	428	if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) {
	429	puts("PHY AN adv speed");
	430	goto miiphy_read_failed;
	431	}
	432	return ((anlpar & adv) & LPA_100) ? _100BASET : _10BASET;
a56bd922 WD	433	}
a56bd922 WD	434	/* Get speed from basic control settings. */
8ef583a0	435	return (bmcr & BMCR_SPEED100) ? _100BASET : _10BASET;
a56bd922	436
5f841959	437	miiphy_read_failed:
16a53238	438	printf(" read failed, assuming 10BASE-T\n");
71bc6e64	439	return _10BASET;
c609719b WD	440	}
c609719b WD	441
c609719b WD	442	/*****************************************************************************
c609719b WD	443	*
71bc6e64	444	* Determine full/half duplex. Return half on error.
c609719b	445	*/
5700bb63	446	int miiphy_duplex(const char *devname, unsigned char addr)
c609719b	447	{
8c83c030	448	u16 bmcr, anlpar, adv;
c609719b	449
6fb6af6d	450	#if defined(CONFIG_PHY_GIGE)
71bc6e64 LJ	451	u16 btsr;
	452
	453	/* Check for 1000BASE-X. */
16a53238	454	if (miiphy_is_1000base_x(devname, addr)) {
71bc6e64	455	/* 1000BASE-X */
16a53238 AF	456	if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
16a53238 AF	457	printf("1000BASE-X PHY AN duplex");
71bc6e64 LJ	458	goto miiphy_read_failed;
	459	}
	460	}
	461	/*
	462	* No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
	463	*/
	464	/* Check for 1000BASE-T. */
16a53238 AF	465	if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) {
16a53238 AF	466	printf("PHY 1000BT status");
71bc6e64 LJ	467	goto miiphy_read_failed;
	468	}
	469	if (btsr != 0xFFFF) {
	470	if (btsr & PHY_1000BTSR_1000FD) {
	471	return FULL;
	472	} else if (btsr & PHY_1000BTSR_1000HD) {
	473	return HALF;
855a496f WD	474	}
855a496f WD	475	}
6fb6af6d	476	#endif /* CONFIG_PHY_GIGE */
855a496f	477
a56bd922	478	/* Check Basic Management Control Register first. */
16a53238 AF	479	if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
16a53238 AF	480	puts("PHY duplex");
71bc6e64	481	goto miiphy_read_failed;
c609719b	482	}
a56bd922	483	/* Check if auto-negotiation is on. */
8ef583a0	484	if (bmcr & BMCR_ANENABLE) {
a56bd922	485	/* Get auto-negotiation results. */
16a53238 AF	486	if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
16a53238 AF	487	puts("PHY AN duplex");
71bc6e64	488	goto miiphy_read_failed;
a56bd922	489	}
8c83c030 DL	490
	491	if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) {
	492	puts("PHY AN adv duplex");
	493	goto miiphy_read_failed;
	494	}
	495	return ((anlpar & adv) & (LPA_10FULL \| LPA_100FULL)) ?
71bc6e64	496	FULL : HALF;
a56bd922 WD	497	}
a56bd922 WD	498	/* Get speed from basic control settings. */
8ef583a0	499	return (bmcr & BMCR_FULLDPLX) ? FULL : HALF;
71bc6e64	500
5f841959	501	miiphy_read_failed:
16a53238	502	printf(" read failed, assuming half duplex\n");
71bc6e64 LJ	503	return HALF;
71bc6e64 LJ	504	}
a56bd922	505
71bc6e64 LJ	506	/*****************************************************************************
	507	*
	508	* Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/
	509	* 1000BASE-T, or on error.
	510	*/
5700bb63	511	int miiphy_is_1000base_x(const char *devname, unsigned char addr)
71bc6e64 LJ	512	{
	513	#if defined(CONFIG_PHY_GIGE)
	514	u16 exsr;
	515
16a53238 AF	516	if (miiphy_read(devname, addr, MII_ESTATUS, &exsr)) {
16a53238 AF	517	printf("PHY extended status read failed, assuming no "
71bc6e64 LJ	518	"1000BASE-X\n");
	519	return 0;
	520	}
8ef583a0	521	return 0 != (exsr & (ESTATUS_1000XF \| ESTATUS_1000XH));
71bc6e64 LJ	522	#else
	523	return 0;
	524	#endif
c609719b WD	525	}
c609719b WD	526
6d0f6bcf	527	#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
fc3e2165 WD	528	/*****************************************************************************
	529	*
	530	* Determine link status
	531	*/
5700bb63	532	int miiphy_link(const char *devname, unsigned char addr)
fc3e2165 WD	533	{
	534	unsigned short reg;
	535
a3d991bd	536	/* dummy read; needed to latch some phys */
16a53238 AF	537	(void)miiphy_read(devname, addr, MII_BMSR, &reg);
	538	if (miiphy_read(devname, addr, MII_BMSR, &reg)) {
	539	puts("MII_BMSR read failed, assuming no link\n");
	540	return 0;
fc3e2165 WD	541	}
	542
	543	/* Determine if a link is active */
8ef583a0	544	if ((reg & BMSR_LSTATUS) != 0) {
16a53238	545	return 1;
fc3e2165	546	} else {
16a53238	547	return 0;
fc3e2165 WD	548	}
	549	}
	550	#endif