[people/ms/u-boot.git] / common / spartan3.c

/*
 * (C) Copyright 2002
 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

/*
 * Configuration support for Xilinx Spartan3 devices.  Based
 * on spartan2.c (Rich Ireland, rireland@enterasys.com).
 */

#include <common.h>		/* core U-Boot definitions */
#include <spartan3.h>		/* Spartan-II device family */

#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN3)

/* Define FPGA_DEBUG to get debug printf's */
#ifdef	FPGA_DEBUG
#define PRINTF(fmt,args...)	printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif

#undef CFG_FPGA_CHECK_BUSY
#undef CFG_FPGA_PROG_FEEDBACK

/* Note: The assumption is that we cannot possibly run fast enough to
 * overrun the device (the Slave Parallel mode can free run at 50MHz).
 * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
 * the board config file to slow things down.
 */
#ifndef CONFIG_FPGA_DELAY
#define CONFIG_FPGA_DELAY()
#endif

#ifndef CFG_FPGA_WAIT
#define CFG_FPGA_WAIT CFG_HZ/100	/* 10 ms */
#endif

static int Spartan3_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
static int Spartan3_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize );
/* static int Spartan3_sp_info( Xilinx_desc *desc ); */
static int Spartan3_sp_reloc( Xilinx_desc *desc, ulong reloc_offset );

static int Spartan3_ss_load( Xilinx_desc *desc, void *buf, size_t bsize );
static int Spartan3_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize );
/* static int Spartan3_ss_info( Xilinx_desc *desc ); */
static int Spartan3_ss_reloc( Xilinx_desc *desc, ulong reloc_offset );

/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize)
{
	int ret_val = FPGA_FAIL;

	switch (desc->iface) {
	case slave_serial:
		PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
		ret_val = Spartan3_ss_load (desc, buf, bsize);
		break;

	case slave_parallel:
		PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
		ret_val = Spartan3_sp_load (desc, buf, bsize);
		break;

	default:
		printf ("%s: Unsupported interface type, %d\n",
				__FUNCTION__, desc->iface);
	}

	return ret_val;
}

int Spartan3_dump (Xilinx_desc * desc, void *buf, size_t bsize)
{
	int ret_val = FPGA_FAIL;

	switch (desc->iface) {
	case slave_serial:
		PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
		ret_val = Spartan3_ss_dump (desc, buf, bsize);
		break;

	case slave_parallel:
		PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
		ret_val = Spartan3_sp_dump (desc, buf, bsize);
		break;

	default:
		printf ("%s: Unsupported interface type, %d\n",
				__FUNCTION__, desc->iface);
	}

	return ret_val;
}

int Spartan3_info( Xilinx_desc *desc )
{
	return FPGA_SUCCESS;
}


int Spartan3_reloc (Xilinx_desc * desc, ulong reloc_offset)
{
	int ret_val = FPGA_FAIL;	/* assume a failure */

	if (desc->family != Xilinx_Spartan3) {
		printf ("%s: Unsupported family type, %d\n",
				__FUNCTION__, desc->family);
		return FPGA_FAIL;
	} else
		switch (desc->iface) {
		case slave_serial:
			ret_val = Spartan3_ss_reloc (desc, reloc_offset);
			break;

		case slave_parallel:
			ret_val = Spartan3_sp_reloc (desc, reloc_offset);
			break;

		default:
			printf ("%s: Unsupported interface type, %d\n",
					__FUNCTION__, desc->iface);
		}

	return ret_val;
}


/* ------------------------------------------------------------------------- */
/* Spartan-II Slave Parallel Generic Implementation */

static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
{
	int ret_val = FPGA_FAIL;	/* assume the worst */
	Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;

	PRINTF ("%s: start with interface functions @ 0x%p\n",
			__FUNCTION__, fn);

	if (fn) {
		size_t bytecount = 0;
		unsigned char *data = (unsigned char *) buf;
		int cookie = desc->cookie;	/* make a local copy */
		unsigned long ts;		/* timestamp */

		PRINTF ("%s: Function Table:\n"
				"ptr:\t0x%p\n"
				"struct: 0x%p\n"
				"pre: 0x%p\n"
				"pgm:\t0x%p\n"
				"init:\t0x%p\n"
				"err:\t0x%p\n"
				"clk:\t0x%p\n"
				"cs:\t0x%p\n"
				"wr:\t0x%p\n"
				"read data:\t0x%p\n"
				"write data:\t0x%p\n"
				"busy:\t0x%p\n"
				"abort:\t0x%p\n",
				"post:\t0x%p\n\n",
				__FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
				fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
				fn->abort, fn->post);

		/*
		 * This code is designed to emulate the "Express Style"
		 * Continuous Data Loading in Slave Parallel Mode for
		 * the Spartan-II Family.
		 */
#ifdef CFG_FPGA_PROG_FEEDBACK
		printf ("Loading FPGA Device %d...\n", cookie);
#endif
		/*
		 * Run the pre configuration function if there is one.
		 */
		if (*fn->pre) {
			(*fn->pre) (cookie);
		}

		/* Establish the initial state */
		(*fn->pgm) (TRUE, TRUE, cookie);	/* Assert the program, commit */

		/* Get ready for the burn */
		CONFIG_FPGA_DELAY ();
		(*fn->pgm) (FALSE, TRUE, cookie);	/* Deassert the program, commit */

		ts = get_timer (0);		/* get current time */
		/* Now wait for INIT and BUSY to go high */
		do {
			CONFIG_FPGA_DELAY ();
			if (get_timer (ts) > CFG_FPGA_WAIT) {	/* check the time */
				puts ("** Timeout waiting for INIT to clear.\n");
				(*fn->abort) (cookie);	/* abort the burn */
				return FPGA_FAIL;
			}
		} while ((*fn->init) (cookie) && (*fn->busy) (cookie));

		(*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */
		(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
		(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */

		/* Load the data */
		while (bytecount < bsize) {
			/* XXX - do we check for an Ctrl-C press in here ??? */
			/* XXX - Check the error bit? */

			(*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */
			CONFIG_FPGA_DELAY ();
			(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
			CONFIG_FPGA_DELAY ();
			(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */

#ifdef CFG_FPGA_CHECK_BUSY
			ts = get_timer (0);	/* get current time */
			while ((*fn->busy) (cookie)) {
				/* XXX - we should have a check in here somewhere to
				 * make sure we aren't busy forever... */

				CONFIG_FPGA_DELAY ();
				(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
				CONFIG_FPGA_DELAY ();
				(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */

				if (get_timer (ts) > CFG_FPGA_WAIT) {	/* check the time */
					puts ("** Timeout waiting for BUSY to clear.\n");
					(*fn->abort) (cookie);	/* abort the burn */
					return FPGA_FAIL;
				}
			}
#endif

#ifdef CFG_FPGA_PROG_FEEDBACK
			if (bytecount % (bsize / 40) == 0)
				putc ('.');		/* let them know we are alive */
#endif
		}

		CONFIG_FPGA_DELAY ();
		(*fn->cs) (FALSE, TRUE, cookie);	/* Deassert the chip select */
		(*fn->wr) (FALSE, TRUE, cookie);	/* Deassert the write pin */

#ifdef CFG_FPGA_PROG_FEEDBACK
		putc ('\n');			/* terminate the dotted line */
#endif

		/* now check for done signal */
		ts = get_timer (0);		/* get current time */
		ret_val = FPGA_SUCCESS;
		while ((*fn->done) (cookie) == FPGA_FAIL) {
			/* XXX - we should have a check in here somewhere to
			 * make sure we aren't busy forever... */

			CONFIG_FPGA_DELAY ();
			(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
			CONFIG_FPGA_DELAY ();
			(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */

			if (get_timer (ts) > CFG_FPGA_WAIT) {	/* check the time */
				puts ("** Timeout waiting for DONE to clear.\n");
				(*fn->abort) (cookie);	/* abort the burn */
				ret_val = FPGA_FAIL;
				break;
			}
		}

		if (ret_val == FPGA_SUCCESS) {
#ifdef CFG_FPGA_PROG_FEEDBACK
			puts ("Done.\n");
#endif
		}
		/*
		 * Run the post configuration function if there is one.
		 */
		if (*fn->post) {
			(*fn->post) (cookie);
		}

		else {
#ifdef CFG_FPGA_PROG_FEEDBACK
			puts ("Fail.\n");
#endif
		}

	} else {
		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
	}

	return ret_val;
}

static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
{
	int ret_val = FPGA_FAIL;	/* assume the worst */
	Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;

	if (fn) {
		unsigned char *data = (unsigned char *) buf;
		size_t bytecount = 0;
		int cookie = desc->cookie;	/* make a local copy */

		printf ("Starting Dump of FPGA Device %d...\n", cookie);

		(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
		(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */

		/* dump the data */
		while (bytecount < bsize) {
			/* XXX - do we check for an Ctrl-C press in here ??? */

			(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
			(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
			(*fn->rdata) (&(data[bytecount++]), cookie);	/* read the data */
#ifdef CFG_FPGA_PROG_FEEDBACK
			if (bytecount % (bsize / 40) == 0)
				putc ('.');		/* let them know we are alive */
#endif
		}

		(*fn->cs) (FALSE, FALSE, cookie);	/* Deassert the chip select */
		(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
		(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */

#ifdef CFG_FPGA_PROG_FEEDBACK
		putc ('\n');			/* terminate the dotted line */
#endif
		puts ("Done.\n");

		/* XXX - checksum the data? */
	} else {
		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
	}

	return ret_val;
}


static int Spartan3_sp_reloc (Xilinx_desc * desc, ulong reloc_offset)
{
	int ret_val = FPGA_FAIL;	/* assume the worst */
	Xilinx_Spartan3_Slave_Parallel_fns *fn_r, *fn =
			(Xilinx_Spartan3_Slave_Parallel_fns *) (desc->iface_fns);

	if (fn) {
		ulong addr;

		/* Get the relocated table address */
		addr = (ulong) fn + reloc_offset;
		fn_r = (Xilinx_Spartan3_Slave_Parallel_fns *) addr;

		if (!fn_r->relocated) {

			if (memcmp (fn_r, fn,
						sizeof (Xilinx_Spartan3_Slave_Parallel_fns))
				== 0) {
				/* good copy of the table, fix the descriptor pointer */
				desc->iface_fns = fn_r;
			} else {
				PRINTF ("%s: Invalid function table at 0x%p\n",
						__FUNCTION__, fn_r);
				return FPGA_FAIL;
			}

			PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
					desc);

			addr = (ulong) (fn->pre) + reloc_offset;
			fn_r->pre = (Xilinx_pre_fn) addr;

			addr = (ulong) (fn->pgm) + reloc_offset;
			fn_r->pgm = (Xilinx_pgm_fn) addr;

			addr = (ulong) (fn->init) + reloc_offset;
			fn_r->init = (Xilinx_init_fn) addr;

			addr = (ulong) (fn->done) + reloc_offset;
			fn_r->done = (Xilinx_done_fn) addr;

			addr = (ulong) (fn->clk) + reloc_offset;
			fn_r->clk = (Xilinx_clk_fn) addr;

			addr = (ulong) (fn->err) + reloc_offset;
			fn_r->err = (Xilinx_err_fn) addr;

			addr = (ulong) (fn->cs) + reloc_offset;
			fn_r->cs = (Xilinx_cs_fn) addr;

			addr = (ulong) (fn->wr) + reloc_offset;
			fn_r->wr = (Xilinx_wr_fn) addr;

			addr = (ulong) (fn->rdata) + reloc_offset;
			fn_r->rdata = (Xilinx_rdata_fn) addr;

			addr = (ulong) (fn->wdata) + reloc_offset;
			fn_r->wdata = (Xilinx_wdata_fn) addr;

			addr = (ulong) (fn->busy) + reloc_offset;
			fn_r->busy = (Xilinx_busy_fn) addr;

			addr = (ulong) (fn->abort) + reloc_offset;
			fn_r->abort = (Xilinx_abort_fn) addr;

			addr = (ulong) (fn->post) + reloc_offset;
			fn_r->post = (Xilinx_post_fn) addr;

			fn_r->relocated = TRUE;

		} else {
			/* this table has already been moved */
			/* XXX - should check to see if the descriptor is correct */
			desc->iface_fns = fn_r;
		}

		ret_val = FPGA_SUCCESS;
	} else {
		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
	}

	return ret_val;

}

/* ------------------------------------------------------------------------- */

static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
{
	int ret_val = FPGA_FAIL;	/* assume the worst */
	Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns;
	int i;
	unsigned char val;

	PRINTF ("%s: start with interface functions @ 0x%p\n",
			__FUNCTION__, fn);

	if (fn) {
		size_t bytecount = 0;
		unsigned char *data = (unsigned char *) buf;
		int cookie = desc->cookie;	/* make a local copy */
		unsigned long ts;		/* timestamp */

		PRINTF ("%s: Function Table:\n"
				"ptr:\t0x%p\n"
				"struct: 0x%p\n"
				"pgm:\t0x%p\n"
				"init:\t0x%p\n"
				"clk:\t0x%p\n"
				"wr:\t0x%p\n"
				"done:\t0x%p\n\n",
				__FUNCTION__, &fn, fn, fn->pgm, fn->init,
				fn->clk, fn->wr, fn->done);
#ifdef CFG_FPGA_PROG_FEEDBACK
		printf ("Loading FPGA Device %d...\n", cookie);
#endif

		/*
		 * Run the pre configuration function if there is one.
		 */
		if (*fn->pre) {
			(*fn->pre) (cookie);
		}

		/* Establish the initial state */
		(*fn->pgm) (TRUE, TRUE, cookie);	/* Assert the program, commit */

		/* Wait for INIT state (init low)                            */
		ts = get_timer (0);		/* get current time */
		do {
			CONFIG_FPGA_DELAY ();
			if (get_timer (ts) > CFG_FPGA_WAIT) {	/* check the time */
				puts ("** Timeout waiting for INIT to start.\n");
				return FPGA_FAIL;
			}
		} while (!(*fn->init) (cookie));

		/* Get ready for the burn */
		CONFIG_FPGA_DELAY ();
		(*fn->pgm) (FALSE, TRUE, cookie);	/* Deassert the program, commit */

		ts = get_timer (0);		/* get current time */
		/* Now wait for INIT to go high */
		do {
			CONFIG_FPGA_DELAY ();
			if (get_timer (ts) > CFG_FPGA_WAIT) {	/* check the time */
				puts ("** Timeout waiting for INIT to clear.\n");
				return FPGA_FAIL;
			}
		} while ((*fn->init) (cookie));

		/* Load the data */
		while (bytecount < bsize) {

			/* Xilinx detects an error if INIT goes low (active)
			   while DONE is low (inactive) */
			if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
				puts ("** CRC error during FPGA load.\n");
				return (FPGA_FAIL);
			}
			val = data [bytecount ++];
			i = 8;
			do {
				/* Deassert the clock */
				(*fn->clk) (FALSE, TRUE, cookie);
				CONFIG_FPGA_DELAY ();
				/* Write data */
				(*fn->wr) ((val & 0x80), TRUE, cookie);
				CONFIG_FPGA_DELAY ();
				/* Assert the clock */
				(*fn->clk) (TRUE, TRUE, cookie);
				CONFIG_FPGA_DELAY ();
				val <<= 1;
				i --;
			} while (i > 0);

#ifdef CFG_FPGA_PROG_FEEDBACK
			if (bytecount % (bsize / 40) == 0)
				putc ('.');		/* let them know we are alive */
#endif
		}

		CONFIG_FPGA_DELAY ();

#ifdef CFG_FPGA_PROG_FEEDBACK
		putc ('\n');			/* terminate the dotted line */
#endif

		/* now check for done signal */
		ts = get_timer (0);		/* get current time */
		ret_val = FPGA_SUCCESS;
		(*fn->wr) (TRUE, TRUE, cookie);

		while (! (*fn->done) (cookie)) {
			/* XXX - we should have a check in here somewhere to
			 * make sure we aren't busy forever... */

			CONFIG_FPGA_DELAY ();
			(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
			CONFIG_FPGA_DELAY ();
			(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */

			putc ('*');

			if (get_timer (ts) > CFG_FPGA_WAIT) {	/* check the time */
				puts ("** Timeout waiting for DONE to clear.\n");
				ret_val = FPGA_FAIL;
				break;
			}
		}
		putc ('\n');			/* terminate the dotted line */

		/*
		 * Run the post configuration function if there is one.
		 */
		if (*fn->post) {
			(*fn->post) (cookie);
		}

#ifdef CFG_FPGA_PROG_FEEDBACK
		if (ret_val == FPGA_SUCCESS) {
			puts ("Done.\n");
		}
		else {
			puts ("Fail.\n");
		}
#endif

	} else {
		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
	}

	return ret_val;
}

static int Spartan3_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
{
	/* Readback is only available through the Slave Parallel and         */
	/* boundary-scan interfaces.                                         */
	printf ("%s: Slave Serial Dumping is unavailable\n",
			__FUNCTION__);
	return FPGA_FAIL;
}

static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
{
	int ret_val = FPGA_FAIL;	/* assume the worst */
	Xilinx_Spartan3_Slave_Serial_fns *fn_r, *fn =
			(Xilinx_Spartan3_Slave_Serial_fns *) (desc->iface_fns);

	if (fn) {
		ulong addr;

		/* Get the relocated table address */
		addr = (ulong) fn + reloc_offset;
		fn_r = (Xilinx_Spartan3_Slave_Serial_fns *) addr;

		if (!fn_r->relocated) {

			if (memcmp (fn_r, fn,
						sizeof (Xilinx_Spartan3_Slave_Serial_fns))
				== 0) {
				/* good copy of the table, fix the descriptor pointer */
				desc->iface_fns = fn_r;
			} else {
				PRINTF ("%s: Invalid function table at 0x%p\n",
						__FUNCTION__, fn_r);
				return FPGA_FAIL;
			}

			PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
					desc);

			if (fn->pre) {
				addr = (ulong) (fn->pre) + reloc_offset;
				fn_r->pre = (Xilinx_pre_fn) addr;
			}

			addr = (ulong) (fn->pgm) + reloc_offset;
			fn_r->pgm = (Xilinx_pgm_fn) addr;

			addr = (ulong) (fn->init) + reloc_offset;
			fn_r->init = (Xilinx_init_fn) addr;

			addr = (ulong) (fn->done) + reloc_offset;
			fn_r->done = (Xilinx_done_fn) addr;

			addr = (ulong) (fn->clk) + reloc_offset;
			fn_r->clk = (Xilinx_clk_fn) addr;

			addr = (ulong) (fn->wr) + reloc_offset;
			fn_r->wr = (Xilinx_wr_fn) addr;

			if (fn->post) {
				addr = (ulong) (fn->post) + reloc_offset;
				fn_r->post = (Xilinx_post_fn) addr;
			}

			fn_r->relocated = TRUE;

		} else {
			/* this table has already been moved */
			/* XXX - should check to see if the descriptor is correct */
			desc->iface_fns = fn_r;
		}

		ret_val = FPGA_SUCCESS;
	} else {
		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
	}

	return ret_val;

}

#endif
Commit	Line	Data
875c7893 WD	1	/*
	2	* (C) Copyright 2002
	3	* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	*/
	24
	25	/*
	26	* Configuration support for Xilinx Spartan3 devices. Based
	27	* on spartan2.c (Rich Ireland, rireland@enterasys.com).
	28	*/
716c1dcb	29
875c7893 WD	30	#include <common.h> /* core U-Boot definitions */
	31	#include <spartan3.h> /* Spartan-II device family */
	32
0133502e	33	#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN3)
875c7893 WD	34
	35	/* Define FPGA_DEBUG to get debug printf's */
	36	#ifdef FPGA_DEBUG
	37	#define PRINTF(fmt,args...) printf (fmt ,##args)
	38	#else
	39	#define PRINTF(fmt,args...)
	40	#endif
	41
	42	#undef CFG_FPGA_CHECK_BUSY
	43	#undef CFG_FPGA_PROG_FEEDBACK
	44
	45	/* Note: The assumption is that we cannot possibly run fast enough to
	46	* overrun the device (the Slave Parallel mode can free run at 50MHz).
	47	* If there is a need to operate slower, define CONFIG_FPGA_DELAY in
	48	* the board config file to slow things down.
	49	*/
	50	#ifndef CONFIG_FPGA_DELAY
	51	#define CONFIG_FPGA_DELAY()
	52	#endif
	53
	54	#ifndef CFG_FPGA_WAIT
	55	#define CFG_FPGA_WAIT CFG_HZ/100 /* 10 ms */
	56	#endif
	57
	58	static int Spartan3_sp_load( Xilinx_desc desc, void buf, size_t bsize );
	59	static int Spartan3_sp_dump( Xilinx_desc desc, void buf, size_t bsize );
	60	/* static int Spartan3_sp_info( Xilinx_desc desc ); /
	61	static int Spartan3_sp_reloc( Xilinx_desc *desc, ulong reloc_offset );
	62
	63	static int Spartan3_ss_load( Xilinx_desc desc, void buf, size_t bsize );
	64	static int Spartan3_ss_dump( Xilinx_desc desc, void buf, size_t bsize );
	65	/* static int Spartan3_ss_info( Xilinx_desc desc ); /
	66	static int Spartan3_ss_reloc( Xilinx_desc *desc, ulong reloc_offset );
	67
	68	/* ------------------------------------------------------------------------- */
	69	/* Spartan-II Generic Implementation */
	70	int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize)
	71	{
	72	int ret_val = FPGA_FAIL;
	73
	74	switch (desc->iface) {
	75	case slave_serial:
	76	PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
	77	ret_val = Spartan3_ss_load (desc, buf, bsize);
	78	break;
	79
	80	case slave_parallel:
	81	PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
	82	ret_val = Spartan3_sp_load (desc, buf, bsize);
	83	break;
	84
	85	default:
	86	printf ("%s: Unsupported interface type, %d\n",
	87	__FUNCTION__, desc->iface);
	88	}
	89
	90	return ret_val;
	91	}
	92
	93	int Spartan3_dump (Xilinx_desc * desc, void *buf, size_t bsize)
	94	{
	95	int ret_val = FPGA_FAIL;
	96
	97	switch (desc->iface) {
98	case slave_serial:
99	PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
100	ret_val = Spartan3_ss_dump (desc, buf, bsize);
101	break;
102
103	case slave_parallel:
104	PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
105	ret_val = Spartan3_sp_dump (desc, buf, bsize);
106	break;
107
108	default:
109	printf ("%s: Unsupported interface type, %d\n",
110	__FUNCTION__, desc->iface);
111	}
112
113	return ret_val;
114	}
115
116	int Spartan3_info( Xilinx_desc *desc )
117	{
118	return FPGA_SUCCESS;
119	}
120
121
122	int Spartan3_reloc (Xilinx_desc * desc, ulong reloc_offset)
123	{
124	int ret_val = FPGA_FAIL; /* assume a failure */
125
126	if (desc->family != Xilinx_Spartan3) {
127	printf ("%s: Unsupported family type, %d\n",
128	__FUNCTION__, desc->family);
129	return FPGA_FAIL;
130	} else
131	switch (desc->iface) {
132	case slave_serial:
133	ret_val = Spartan3_ss_reloc (desc, reloc_offset);
134	break;
135
136	case slave_parallel:
137	ret_val = Spartan3_sp_reloc (desc, reloc_offset);
138	break;
139
140	default:
141	printf ("%s: Unsupported interface type, %d\n",
142	__FUNCTION__, desc->iface);
143	}
144
145	return ret_val;
146	}
147
148
149	/* ------------------------------------------------------------------------- */
150	/* Spartan-II Slave Parallel Generic Implementation */
151
152	static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
153	{
154	int ret_val = FPGA_FAIL; /* assume the worst */
155	Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
156
157	PRINTF ("%s: start with interface functions @ 0x%p\n",
158	__FUNCTION__, fn);
159
160	if (fn) {
161	size_t bytecount = 0;
162	unsigned char data = (unsigned char ) buf;
163	int cookie = desc->cookie; /* make a local copy */
164	unsigned long ts; /* timestamp */
165
166	PRINTF ("%s: Function Table:\n"
167	"ptr:\t0x%p\n"
168	"struct: 0x%p\n"
169	"pre: 0x%p\n"
170	"pgm:\t0x%p\n"
171	"init:\t0x%p\n"
172	"err:\t0x%p\n"
173	"clk:\t0x%p\n"
174	"cs:\t0x%p\n"
175	"wr:\t0x%p\n"
176	"read data:\t0x%p\n"
177	"write data:\t0x%p\n"
178	"busy:\t0x%p\n"
179	"abort:\t0x%p\n",
180	"post:\t0x%p\n\n",
181	__FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
182	fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
183	fn->abort, fn->post);
184
185	/*
186	* This code is designed to emulate the "Express Style"
187	* Continuous Data Loading in Slave Parallel Mode for
188	* the Spartan-II Family.
189	*/
190	#ifdef CFG_FPGA_PROG_FEEDBACK
191	printf ("Loading FPGA Device %d...\n", cookie);
192	#endif
193	/*
194	* Run the pre configuration function if there is one.
195	*/
196	if (*fn->pre) {
197	(*fn->pre) (cookie);
198	}
199
200	/* Establish the initial state */
201	(fn->pgm) (TRUE, TRUE, cookie); / Assert the program, commit */
202
203	/* Get ready for the burn */
204	CONFIG_FPGA_DELAY ();
205	(fn->pgm) (FALSE, TRUE, cookie); / Deassert the program, commit */
206
207	ts = get_timer (0); /* get current time */
208	/* Now wait for INIT and BUSY to go high */
209	do {
210	CONFIG_FPGA_DELAY ();
211	if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
212	puts ("** Timeout waiting for INIT to clear.\n");
213	(fn->abort) (cookie); / abort the burn */
214	return FPGA_FAIL;
215	}
216	} while ((fn->init) (cookie) && (fn->busy) (cookie));
217
218	(fn->wr) (TRUE, TRUE, cookie); / Assert write, commit */
219	(fn->cs) (TRUE, TRUE, cookie); / Assert chip select, commit */
220	(fn->clk) (TRUE, TRUE, cookie); / Assert the clock pin */
221
222	/* Load the data */
223	while (bytecount < bsize) {
224	/* XXX - do we check for an Ctrl-C press in here ??? */
225	/* XXX - Check the error bit? */
226
227	(fn->wdata) (data[bytecount++], TRUE, cookie); / write the data */
228	CONFIG_FPGA_DELAY ();
229	(fn->clk) (FALSE, TRUE, cookie); / Deassert the clock pin */
230	CONFIG_FPGA_DELAY ();
231	(fn->clk) (TRUE, TRUE, cookie); / Assert the clock pin */
232
233	#ifdef CFG_FPGA_CHECK_BUSY
234	ts = get_timer (0); /* get current time */
235	while ((*fn->busy) (cookie)) {
236	/* XXX - we should have a check in here somewhere to
237	* make sure we aren't busy forever... */
238
239	CONFIG_FPGA_DELAY ();
240	(fn->clk) (FALSE, TRUE, cookie); / Deassert the clock pin */
241	CONFIG_FPGA_DELAY ();
242	(fn->clk) (TRUE, TRUE, cookie); / Assert the clock pin */
243
244	if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
245	puts ("** Timeout waiting for BUSY to clear.\n");
246	(fn->abort) (cookie); / abort the burn */
247	return FPGA_FAIL;
248	}
249	}
250	#endif
251
252	#ifdef CFG_FPGA_PROG_FEEDBACK
253	if (bytecount % (bsize / 40) == 0)
254	putc ('.'); /* let them know we are alive */
255	#endif
256	}
257
258	CONFIG_FPGA_DELAY ();
259	(fn->cs) (FALSE, TRUE, cookie); / Deassert the chip select */
260	(fn->wr) (FALSE, TRUE, cookie); / Deassert the write pin */
261
262	#ifdef CFG_FPGA_PROG_FEEDBACK
263	putc ('\n'); /* terminate the dotted line */
264	#endif
265
266	/* now check for done signal */
267	ts = get_timer (0); /* get current time */
268	ret_val = FPGA_SUCCESS;
269	while ((*fn->done) (cookie) == FPGA_FAIL) {
270	/* XXX - we should have a check in here somewhere to
271	* make sure we aren't busy forever... */
272
273	CONFIG_FPGA_DELAY ();
274	(fn->clk) (FALSE, TRUE, cookie); / Deassert the clock pin */
275	CONFIG_FPGA_DELAY ();
276	(fn->clk) (TRUE, TRUE, cookie); / Assert the clock pin */
277
278	if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
279	puts ("** Timeout waiting for DONE to clear.\n");
280	(fn->abort) (cookie); / abort the burn */
281	ret_val = FPGA_FAIL;
282	break;
283	}
284	}
285
286	if (ret_val == FPGA_SUCCESS) {
287	#ifdef CFG_FPGA_PROG_FEEDBACK
288	puts ("Done.\n");
289	#endif
290	}
291	/*
292	* Run the post configuration function if there is one.
293	*/
294	if (*fn->post) {
295	(*fn->post) (cookie);
296	}
297
298	else {
299	#ifdef CFG_FPGA_PROG_FEEDBACK
300	puts ("Fail.\n");
301	#endif
302	}
303
304	} else {
305	printf ("%s: NULL Interface function table!\n", __FUNCTION__);
306	}
307
308	return ret_val;
309	}
310
311	static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
312	{
313	int ret_val = FPGA_FAIL; /* assume the worst */
314	Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
315
316	if (fn) {
317	unsigned char data = (unsigned char ) buf;
318	size_t bytecount = 0;
319	int cookie = desc->cookie; /* make a local copy */
320
321	printf ("Starting Dump of FPGA Device %d...\n", cookie);
322
323	(fn->cs) (TRUE, TRUE, cookie); / Assert chip select, commit */
324	(fn->clk) (TRUE, TRUE, cookie); / Assert the clock pin */
325
326	/* dump the data */
327	while (bytecount < bsize) {
328	/* XXX - do we check for an Ctrl-C press in here ??? */
329
330	(fn->clk) (FALSE, TRUE, cookie); / Deassert the clock pin */
331	(fn->clk) (TRUE, TRUE, cookie); / Assert the clock pin */
332	(fn->rdata) (&(data[bytecount++]), cookie); / read the data */
333	#ifdef CFG_FPGA_PROG_FEEDBACK
334	if (bytecount % (bsize / 40) == 0)
335	putc ('.'); /* let them know we are alive */
336	#endif
337	}
338
339	(fn->cs) (FALSE, FALSE, cookie); / Deassert the chip select */
340	(fn->clk) (FALSE, TRUE, cookie); / Deassert the clock pin */
341	(fn->clk) (TRUE, TRUE, cookie); / Assert the clock pin */
342
343	#ifdef CFG_FPGA_PROG_FEEDBACK
344	putc ('\n'); /* terminate the dotted line */
345	#endif
346	puts ("Done.\n");
347
348	/* XXX - checksum the data? */
349	} else {
350	printf ("%s: NULL Interface function table!\n", __FUNCTION__);
351	}
352
353	return ret_val;
354	}
355
356
357	static int Spartan3_sp_reloc (Xilinx_desc * desc, ulong reloc_offset)
358	{
359	int ret_val = FPGA_FAIL; /* assume the worst */
360	Xilinx_Spartan3_Slave_Parallel_fns fn_r, fn =
361	(Xilinx_Spartan3_Slave_Parallel_fns *) (desc->iface_fns);
362
363	if (fn) {
364	ulong addr;
365
366	/* Get the relocated table address */
367	addr = (ulong) fn + reloc_offset;
368	fn_r = (Xilinx_Spartan3_Slave_Parallel_fns *) addr;
369
370	if (!fn_r->relocated) {
371
372	if (memcmp (fn_r, fn,
373	sizeof (Xilinx_Spartan3_Slave_Parallel_fns))
374	== 0) {
375	/* good copy of the table, fix the descriptor pointer */
376	desc->iface_fns = fn_r;
377	} else {
378	PRINTF ("%s: Invalid function table at 0x%p\n",
379	__FUNCTION__, fn_r);
380	return FPGA_FAIL;
381	}
382
383	PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
384	desc);
385
386	addr = (ulong) (fn->pre) + reloc_offset;
387	fn_r->pre = (Xilinx_pre_fn) addr;
388
389	addr = (ulong) (fn->pgm) + reloc_offset;
390	fn_r->pgm = (Xilinx_pgm_fn) addr;
391
392	addr = (ulong) (fn->init) + reloc_offset;
393	fn_r->init = (Xilinx_init_fn) addr;
394
395	addr = (ulong) (fn->done) + reloc_offset;
396	fn_r->done = (Xilinx_done_fn) addr;
397
398	addr = (ulong) (fn->clk) + reloc_offset;
399	fn_r->clk = (Xilinx_clk_fn) addr;
400
401	addr = (ulong) (fn->err) + reloc_offset;
402	fn_r->err = (Xilinx_err_fn) addr;
403
404	addr = (ulong) (fn->cs) + reloc_offset;
405	fn_r->cs = (Xilinx_cs_fn) addr;
406
407	addr = (ulong) (fn->wr) + reloc_offset;
408	fn_r->wr = (Xilinx_wr_fn) addr;
409
410	addr = (ulong) (fn->rdata) + reloc_offset;
411	fn_r->rdata = (Xilinx_rdata_fn) addr;
412
413	addr = (ulong) (fn->wdata) + reloc_offset;
414	fn_r->wdata = (Xilinx_wdata_fn) addr;
415
416	addr = (ulong) (fn->busy) + reloc_offset;
417	fn_r->busy = (Xilinx_busy_fn) addr;
418
419	addr = (ulong) (fn->abort) + reloc_offset;
420	fn_r->abort = (Xilinx_abort_fn) addr;
421
422	addr = (ulong) (fn->post) + reloc_offset;
423	fn_r->post = (Xilinx_post_fn) addr;
424
425	fn_r->relocated = TRUE;
426
427	} else {
428	/* this table has already been moved */
429	/* XXX - should check to see if the descriptor is correct */
430	desc->iface_fns = fn_r;
431	}
432
433	ret_val = FPGA_SUCCESS;
434	} else {
435	printf ("%s: NULL Interface function table!\n", __FUNCTION__);
436	}
437
438	return ret_val;
439
440	}
441
442	/* ------------------------------------------------------------------------- */
443
444	static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
445	{
446	int ret_val = FPGA_FAIL; /* assume the worst */
447	Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns;
448	int i;
437fc732	449	unsigned char val;
875c7893 WD	450
	451	PRINTF ("%s: start with interface functions @ 0x%p\n",
	452	__FUNCTION__, fn);
	453
	454	if (fn) {
	455	size_t bytecount = 0;
	456	unsigned char data = (unsigned char ) buf;
	457	int cookie = desc->cookie; /* make a local copy */
	458	unsigned long ts; /* timestamp */
	459
	460	PRINTF ("%s: Function Table:\n"
	461	"ptr:\t0x%p\n"
	462	"struct: 0x%p\n"
	463	"pgm:\t0x%p\n"
	464	"init:\t0x%p\n"
	465	"clk:\t0x%p\n"
	466	"wr:\t0x%p\n"
	467	"done:\t0x%p\n\n",
	468	__FUNCTION__, &fn, fn, fn->pgm, fn->init,
	469	fn->clk, fn->wr, fn->done);
	470	#ifdef CFG_FPGA_PROG_FEEDBACK
	471	printf ("Loading FPGA Device %d...\n", cookie);
	472	#endif
	473
	474	/*
	475	* Run the pre configuration function if there is one.
	476	*/
	477	if (*fn->pre) {
	478	(*fn->pre) (cookie);
	479	}
	480
	481	/* Establish the initial state */
	482	(fn->pgm) (TRUE, TRUE, cookie); / Assert the program, commit */
	483
	484	/* Wait for INIT state (init low) */
	485	ts = get_timer (0); /* get current time */
	486	do {
	487	CONFIG_FPGA_DELAY ();
	488	if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
	489	puts ("** Timeout waiting for INIT to start.\n");
	490	return FPGA_FAIL;
	491	}
	492	} while (!(*fn->init) (cookie));
	493
	494	/* Get ready for the burn */
	495	CONFIG_FPGA_DELAY ();
	496	(fn->pgm) (FALSE, TRUE, cookie); / Deassert the program, commit */
	497
	498	ts = get_timer (0); /* get current time */
	499	/* Now wait for INIT to go high */
	500	do {
	501	CONFIG_FPGA_DELAY ();
	502	if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
	503	puts ("** Timeout waiting for INIT to clear.\n");
	504	return FPGA_FAIL;
	505	}
	506	} while ((*fn->init) (cookie));
	507
	508	/* Load the data */
	509	while (bytecount < bsize) {
	510
	511	/* Xilinx detects an error if INIT goes low (active)
	512	while DONE is low (inactive) */
	513	if ((fn->done) (cookie) == 0 && (fn->init) (cookie)) {
514	puts ("** CRC error during FPGA load.\n");
515	return (FPGA_FAIL);
516	}
517	val = data [bytecount ++];
518	i = 8;
519	do {
520	/* Deassert the clock */
521	(*fn->clk) (FALSE, TRUE, cookie);
522	CONFIG_FPGA_DELAY ();
523	/* Write data */
6ecbb7a3	524	(*fn->wr) ((val & 0x80), TRUE, cookie);
875c7893 WD	525	CONFIG_FPGA_DELAY ();
	526	/* Assert the clock */
	527	(*fn->clk) (TRUE, TRUE, cookie);
	528	CONFIG_FPGA_DELAY ();
	529	val <<= 1;
	530	i --;
	531	} while (i > 0);
	532
	533	#ifdef CFG_FPGA_PROG_FEEDBACK
	534	if (bytecount % (bsize / 40) == 0)
	535	putc ('.'); /* let them know we are alive */
	536	#endif
	537	}
	538
	539	CONFIG_FPGA_DELAY ();
	540
	541	#ifdef CFG_FPGA_PROG_FEEDBACK
	542	putc ('\n'); /* terminate the dotted line */
	543	#endif
	544
	545	/* now check for done signal */
	546	ts = get_timer (0); /* get current time */
	547	ret_val = FPGA_SUCCESS;
	548	(*fn->wr) (TRUE, TRUE, cookie);
	549
	550	while (! (*fn->done) (cookie)) {
	551	/* XXX - we should have a check in here somewhere to
	552	* make sure we aren't busy forever... */
	553
	554	CONFIG_FPGA_DELAY ();
	555	(fn->clk) (FALSE, TRUE, cookie); / Deassert the clock pin */
	556	CONFIG_FPGA_DELAY ();
	557	(fn->clk) (TRUE, TRUE, cookie); / Assert the clock pin */
	558
	559	putc ('*');
	560
	561	if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
	562	puts ("** Timeout waiting for DONE to clear.\n");
	563	ret_val = FPGA_FAIL;
	564	break;
	565	}
	566	}
	567	putc ('\n'); /* terminate the dotted line */
	568
21d39d59 MF	569	/*
	570	* Run the post configuration function if there is one.
	571	*/
	572	if (*fn->post) {
	573	(*fn->post) (cookie);
	574	}
	575
875c7893 WD	576	#ifdef CFG_FPGA_PROG_FEEDBACK
	577	if (ret_val == FPGA_SUCCESS) {
	578	puts ("Done.\n");
	579	}
	580	else {
	581	puts ("Fail.\n");
	582	}
	583	#endif
	584
	585	} else {
	586	printf ("%s: NULL Interface function table!\n", __FUNCTION__);
	587	}
	588
	589	return ret_val;
	590	}
	591
	592	static int Spartan3_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
	593	{
	594	/* Readback is only available through the Slave Parallel and */
	595	/* boundary-scan interfaces. */
	596	printf ("%s: Slave Serial Dumping is unavailable\n",
	597	__FUNCTION__);
	598	return FPGA_FAIL;
	599	}
	600
	601	static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
	602	{
	603	int ret_val = FPGA_FAIL; /* assume the worst */
	604	Xilinx_Spartan3_Slave_Serial_fns fn_r, fn =
	605	(Xilinx_Spartan3_Slave_Serial_fns *) (desc->iface_fns);
	606
	607	if (fn) {
	608	ulong addr;
	609
	610	/* Get the relocated table address */
	611	addr = (ulong) fn + reloc_offset;
	612	fn_r = (Xilinx_Spartan3_Slave_Serial_fns *) addr;
	613
	614	if (!fn_r->relocated) {
	615
	616	if (memcmp (fn_r, fn,
	617	sizeof (Xilinx_Spartan3_Slave_Serial_fns))
	618	== 0) {
	619	/* good copy of the table, fix the descriptor pointer */
	620	desc->iface_fns = fn_r;
	621	} else {
	622	PRINTF ("%s: Invalid function table at 0x%p\n",
	623	__FUNCTION__, fn_r);
	624	return FPGA_FAIL;
	625	}
	626
	627	PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
	628	desc);
	629
21d39d59 MF	630	if (fn->pre) {
	631	addr = (ulong) (fn->pre) + reloc_offset;
	632	fn_r->pre = (Xilinx_pre_fn) addr;
	633	}
875c7893 WD	634
	635	addr = (ulong) (fn->pgm) + reloc_offset;
	636	fn_r->pgm = (Xilinx_pgm_fn) addr;
	637
	638	addr = (ulong) (fn->init) + reloc_offset;
	639	fn_r->init = (Xilinx_init_fn) addr;
	640
	641	addr = (ulong) (fn->done) + reloc_offset;
	642	fn_r->done = (Xilinx_done_fn) addr;
	643
	644	addr = (ulong) (fn->clk) + reloc_offset;
	645	fn_r->clk = (Xilinx_clk_fn) addr;
	646
	647	addr = (ulong) (fn->wr) + reloc_offset;
	648	fn_r->wr = (Xilinx_wr_fn) addr;
	649
21d39d59 MF	650	if (fn->post) {
	651	addr = (ulong) (fn->post) + reloc_offset;
	652	fn_r->post = (Xilinx_post_fn) addr;
	653	}
	654
875c7893 WD	655	fn_r->relocated = TRUE;
	656
	657	} else {
	658	/* this table has already been moved */
	659	/* XXX - should check to see if the descriptor is correct */
	660	desc->iface_fns = fn_r;
	661	}
	662
	663	ret_val = FPGA_SUCCESS;
	664	} else {
	665	printf ("%s: NULL Interface function table!\n", __FUNCTION__);
	666	}
	667
	668	return ret_val;
	669
	670	}
	671
	672	#endif