]>
Commit | Line | Data |
---|---|---|
dd84058d | 1 | CONFIG_PPC=y |
278b90ce | 2 | CONFIG_SYS_TEXT_BASE=0xFE000000 |
ff3bb0c4 | 3 | CONFIG_SYS_CLK_FREQ=66666667 |
dd84058d | 4 | CONFIG_MPC83xx=y |
93de2530 | 5 | CONFIG_HIGH_BATS=y |
16aaca21 | 6 | CONFIG_TARGET_MPC8313ERDB_NOR=y |
21c1502a MS |
7 | CONFIG_CORE_PLL_RATIO_2_1=y |
8 | CONFIG_PCI_HOST_MODE_ENABLE=y | |
9 | CONFIG_PCI_INT_ARBITER1_ENABLE=y | |
10 | CONFIG_BOOT_MEMORY_SPACE_LOW=y | |
11 | CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y | |
12 | CONFIG_TSEC1_MODE_RGMII=y | |
13 | CONFIG_TSEC2_MODE_RGMII=y | |
30915ab9 MS |
14 | CONFIG_BAT0=y |
15 | CONFIG_BAT0_NAME="DDR" | |
16 | CONFIG_BAT0_BASE=0x00000000 | |
17 | CONFIG_BAT0_LENGTH_256_MBYTES=y | |
18 | CONFIG_BAT0_ACCESS_RW=y | |
19 | CONFIG_BAT0_USER_MODE_VALID=y | |
20 | CONFIG_BAT0_SUPERVISOR_MODE_VALID=y | |
21 | CONFIG_BAT1=y | |
22 | CONFIG_BAT1_NAME="PCI1_MEM" | |
23 | CONFIG_BAT1_BASE=0x80000000 | |
24 | CONFIG_BAT1_LENGTH_256_MBYTES=y | |
25 | CONFIG_BAT1_ACCESS_RW=y | |
26 | CONFIG_BAT1_USER_MODE_VALID=y | |
27 | CONFIG_BAT1_SUPERVISOR_MODE_VALID=y | |
28 | CONFIG_BAT2=y | |
29 | CONFIG_BAT2_NAME="PCI1_MMIO_BASE" | |
30 | CONFIG_BAT2_BASE=0x90000000 | |
31 | CONFIG_BAT2_LENGTH_256_MBYTES=y | |
32 | CONFIG_BAT2_ACCESS_RW=y | |
33 | CONFIG_BAT2_ICACHE_INHIBITED=y | |
34 | CONFIG_BAT2_ICACHE_GUARDED=y | |
35 | CONFIG_BAT2_DCACHE_INHIBITED=y | |
36 | CONFIG_BAT2_DCACHE_GUARDED=y | |
37 | CONFIG_BAT2_USER_MODE_VALID=y | |
38 | CONFIG_BAT2_SUPERVISOR_MODE_VALID=y | |
39 | CONFIG_BAT5=y | |
40 | CONFIG_BAT5_NAME="IMMR" | |
41 | CONFIG_BAT5_BASE=0xE0000000 | |
42 | CONFIG_BAT5_LENGTH_256_MBYTES=y | |
43 | CONFIG_BAT5_ACCESS_RW=y | |
44 | CONFIG_BAT5_ICACHE_INHIBITED=y | |
45 | CONFIG_BAT5_ICACHE_GUARDED=y | |
46 | CONFIG_BAT5_DCACHE_INHIBITED=y | |
47 | CONFIG_BAT5_DCACHE_GUARDED=y | |
48 | CONFIG_BAT5_USER_MODE_VALID=y | |
49 | CONFIG_BAT5_SUPERVISOR_MODE_VALID=y | |
50 | CONFIG_BAT6=y | |
51 | CONFIG_BAT6_NAME="STACK_IN_DCACHE" | |
52 | CONFIG_BAT6_BASE=0xF0000000 | |
53 | CONFIG_BAT6_LENGTH_256_MBYTES=y | |
54 | CONFIG_BAT6_ACCESS_RW=y | |
55 | CONFIG_BAT6_ICACHE_GUARDED=y | |
56 | CONFIG_BAT6_DCACHE_GUARDED=y | |
57 | CONFIG_BAT6_USER_MODE_VALID=y | |
58 | CONFIG_BAT6_SUPERVISOR_MODE_VALID=y | |
9c5df7a2 MS |
59 | CONFIG_LBLAW0=y |
60 | CONFIG_LBLAW0_BASE=0xFE000000 | |
61 | CONFIG_LBLAW0_NAME="FLASH" | |
62 | CONFIG_LBLAW0_LENGTH_16_MBYTES=y | |
63 | CONFIG_LBLAW1=y | |
64 | CONFIG_LBLAW1_BASE=0xE2800000 | |
65 | CONFIG_LBLAW1_NAME="NAND" | |
66 | CONFIG_LBLAW1_LENGTH_32_KBYTES=y | |
67 | CONFIG_LBLAW2=y | |
68 | CONFIG_LBLAW2_BASE=0xF0000000 | |
69 | CONFIG_LBLAW2_NAME="VSC7385" | |
70 | CONFIG_LBLAW2_LENGTH_128_KBYTES=y | |
71 | CONFIG_LBLAW3=y | |
72 | CONFIG_LBLAW3_BASE=0xFA000000 | |
73 | CONFIG_LBLAW3_NAME="BCSR" | |
74 | CONFIG_LBLAW3_LENGTH_32_KBYTES=y | |
344a0e43 TR |
75 | CONFIG_ELBC_BR_OR_NAND_PRELIM_1=y |
76 | CONFIG_ELBC_BR0_OR0=y | |
77 | CONFIG_BR0_OR0_NAME="FLASH" | |
78 | CONFIG_BR0_OR0_BASE=0xFE000000 | |
79 | CONFIG_BR0_PORTSIZE_16BIT=y | |
80 | CONFIG_OR0_AM_8_MBYTES=y | |
81 | CONFIG_OR0_SCY_9=y | |
82 | CONFIG_OR0_XACS_EXTENDED=y | |
83 | CONFIG_OR0_EHTR_1_CYCLE=y | |
84 | CONFIG_OR0_EAD_EXTRA=y | |
85 | CONFIG_ELBC_BR1_OR1=y | |
86 | CONFIG_BR1_OR1_NAME="NAND" | |
87 | CONFIG_BR1_OR1_BASE=0xE2800000 | |
88 | CONFIG_BR1_ERRORCHECKING_BOTH=y | |
89 | CONFIG_BR1_MACHINE_FCM=y | |
90 | CONFIG_OR1_SCY_1=y | |
91 | CONFIG_OR1_CSCT_8_CYCLE=y | |
92 | CONFIG_OR1_CST_ONE_CLOCK=y | |
93 | CONFIG_OR1_CHT_TWO_CLOCK=y | |
94 | CONFIG_OR1_TRLX_RELAXED=y | |
95 | CONFIG_OR1_EHTR_8_CYCLE=y | |
96 | CONFIG_ELBC_BR2_OR2=y | |
97 | CONFIG_BR2_OR2_NAME="VSC7385" | |
98 | CONFIG_BR2_OR2_BASE=0xF0000000 | |
99 | CONFIG_OR2_AM_128_KBYTES=y | |
100 | CONFIG_OR2_SCY_15=y | |
101 | CONFIG_OR2_CSNT_EARLIER=y | |
102 | CONFIG_OR2_XACS_EXTENDED=y | |
103 | CONFIG_OR2_SETA_EXTERNAL=y | |
104 | CONFIG_OR2_TRLX_RELAXED=y | |
105 | CONFIG_OR2_EHTR_8_CYCLE=y | |
106 | CONFIG_OR2_EAD_EXTRA=y | |
107 | CONFIG_ELBC_BR3_OR3=y | |
108 | CONFIG_BR3_OR3_NAME="BCSR" | |
109 | CONFIG_BR3_OR3_BASE=0xFA000000 | |
110 | CONFIG_OR3_SCY_15=y | |
111 | CONFIG_OR3_CSNT_EARLIER=y | |
112 | CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y | |
113 | CONFIG_OR3_XACS_EXTENDED=y | |
114 | CONFIG_OR3_TRLX_RELAXED=y | |
115 | CONFIG_OR3_EHTR_8_CYCLE=y | |
116 | CONFIG_OR3_EAD_EXTRA=y | |
be5abb0a MS |
117 | CONFIG_HID0_FINAL_EMCP=y |
118 | CONFIG_HID0_FINAL_DPM=y | |
119 | CONFIG_HID0_FINAL_ICE=y | |
120 | CONFIG_HID2_HBE=y | |
73df96a3 MS |
121 | CONFIG_ACR_PIPE_DEP_4=y |
122 | CONFIG_ACR_RPTCNT_4=y | |
344a0e43 TR |
123 | CONFIG_LCRR_EADC_1=y |
124 | CONFIG_LCRR_CLKDIV_4=y | |
73223f0e SG |
125 | CONFIG_OF_BOARD_SETUP=y |
126 | CONFIG_OF_STDOUT_VIA_ALIAS=y | |
bd328eb3 | 127 | CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" |
bb597c0e | 128 | CONFIG_BOOTDELAY=6 |
8ccf98b1 | 129 | CONFIG_MISC_INIT_R=y |
02ddc147 | 130 | CONFIG_BOARD_EARLY_INIT_R=y |
adad96e6 | 131 | CONFIG_HUSH_PARSER=y |
ad12dc18 | 132 | CONFIG_CMD_IMLS=y |
e4aa8edb | 133 | CONFIG_CMD_GPIO=y |
88663126 TR |
134 | CONFIG_CMD_I2C=y |
135 | CONFIG_CMD_NAND=y | |
6500ec7a | 136 | CONFIG_CMD_PCI=y |
ef0f2f57 | 137 | # CONFIG_CMD_SETEXPR is not set |
78d1e1d0 | 138 | CONFIG_CMD_DHCP=y |
89cb2b5f | 139 | CONFIG_CMD_MII=y |
78d1e1d0 | 140 | CONFIG_CMD_PING=y |
c9032ce1 | 141 | CONFIG_CMD_DATE=y |
d56b4b19 | 142 | CONFIG_CMD_MTDPARTS=y |
43ede0bc TR |
143 | CONFIG_MTDIDS_DEFAULT="nand0=e2800000.flash" |
144 | CONFIG_MTDPARTS_DEFAULT="mtdparts=e2800000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" | |
8728c97e | 145 | # CONFIG_MMC is not set |
e856bdcf | 146 | CONFIG_MTD_NOR_FLASH=y |
2fe88d45 AF |
147 | CONFIG_FLASH_CFI_DRIVER=y |
148 | CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y | |
149 | CONFIG_SYS_FLASH_PROTECTION=y | |
150 | CONFIG_SYS_FLASH_CFI=y | |
a8ca5c8a | 151 | CONFIG_PHY_MARVELL=y |
17151052 | 152 | CONFIG_TSEC_ENET=y |
9e39003e | 153 | CONFIG_SYS_NS16550=y |
69e173eb | 154 | CONFIG_OF_LIBFDT=y |