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Commit | Line | Data |
---|---|---|
c420ef67 SG |
1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_ROCKCHIP=y | |
278b90ce | 3 | CONFIG_SYS_TEXT_BASE=0x00100000 |
c420ef67 | 4 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
c420ef67 | 5 | CONFIG_ROCKCHIP_RK3288=y |
8728c97e | 6 | # CONFIG_SPL_MMC_SUPPORT is not set |
c420ef67 | 7 | CONFIG_TARGET_CHROMEBOOK_MINNIE=y |
358b6a20 TR |
8 | CONFIG_DEBUG_UART_BASE=0xff690000 |
9 | CONFIG_DEBUG_UART_CLOCK=24000000 | |
10 | CONFIG_SPL_STACK_R_ADDR=0x80000 | |
c420ef67 SG |
11 | CONFIG_SPL_SPI_FLASH_SUPPORT=y |
12 | CONFIG_SPL_SPI_SUPPORT=y | |
fb82fe38 | 13 | CONFIG_DEBUG_UART=y |
86cf1c82 | 14 | CONFIG_NR_DRAM_BANKS=1 |
48f6232e | 15 | # CONFIG_ANDROID_BOOT_IMAGE is not set |
c420ef67 | 16 | CONFIG_SILENT_CONSOLE=y |
a2a5053a | 17 | CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb" |
c420ef67 | 18 | # CONFIG_DISPLAY_CPUINFO is not set |
78eba69d | 19 | CONFIG_DISPLAY_BOARDINFO_LATE=y |
c420ef67 SG |
20 | CONFIG_SPL_STACK_R=y |
21 | CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 | |
55500438 | 22 | CONFIG_SPL_SPI_LOAD=y |
88663126 | 23 | CONFIG_CMD_GPIO=y |
b331cd62 | 24 | CONFIG_CMD_GPT=y |
88663126 | 25 | CONFIG_CMD_I2C=y |
c420ef67 SG |
26 | CONFIG_CMD_MMC=y |
27 | CONFIG_CMD_SF=y | |
719d36ee | 28 | CONFIG_CMD_SF_TEST=y |
88663126 | 29 | CONFIG_CMD_SPI=y |
c3d098e7 | 30 | CONFIG_CMD_USB=y |
c420ef67 | 31 | # CONFIG_CMD_SETEXPR is not set |
c420ef67 SG |
32 | CONFIG_CMD_CACHE=y |
33 | CONFIG_CMD_TIME=y | |
34 | CONFIG_CMD_PMIC=y | |
35 | CONFIG_CMD_REGULATOR=y | |
b0cf7339 | 36 | # CONFIG_SPL_DOS_PARTITION is not set |
bd42a942 | 37 | # CONFIG_SPL_EFI_PARTITION is not set |
b331cd62 | 38 | CONFIG_SPL_PARTITION_UUIDS=y |
c420ef67 | 39 | CONFIG_SPL_OF_CONTROL=y |
8c5cad05 | 40 | CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie" |
c420ef67 | 41 | CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" |
18780951 | 42 | CONFIG_SPL_OF_PLATDATA=y |
c420ef67 SG |
43 | CONFIG_REGMAP=y |
44 | CONFIG_SPL_REGMAP=y | |
45 | CONFIG_SYSCON=y | |
46 | CONFIG_SPL_SYSCON=y | |
47 | # CONFIG_SPL_SIMPLE_BUS is not set | |
48 | CONFIG_CLK=y | |
49 | CONFIG_SPL_CLK=y | |
65c96757 AK |
50 | CONFIG_FASTBOOT_FLASH=y |
51 | CONFIG_FASTBOOT_FLASH_MMC_DEV=0 | |
52 | CONFIG_FASTBOOT_CMD_OEM_FORMAT=y | |
c420ef67 SG |
53 | CONFIG_ROCKCHIP_GPIO=y |
54 | CONFIG_I2C_CROS_EC_TUNNEL=y | |
55 | CONFIG_SYS_I2C_ROCKCHIP=y | |
56 | CONFIG_I2C_MUX=y | |
57 | CONFIG_DM_KEYBOARD=y | |
58 | CONFIG_CROS_EC_KEYB=y | |
59 | CONFIG_CROS_EC=y | |
60 | CONFIG_CROS_EC_SPI=y | |
61 | CONFIG_PWRSEQ=y | |
55ed3b46 | 62 | CONFIG_MMC_DW=y |
fed44087 | 63 | CONFIG_MMC_DW_ROCKCHIP=y |
c420ef67 SG |
64 | CONFIG_PINCTRL=y |
65 | CONFIG_SPL_PINCTRL=y | |
66 | # CONFIG_SPL_PINCTRL_FULL is not set | |
51c7f348 | 67 | CONFIG_PINCTRL_ROCKCHIP_RK3288=y |
c420ef67 SG |
68 | CONFIG_DM_PMIC=y |
69 | # CONFIG_SPL_PMIC_CHILDREN is not set | |
453c5a92 | 70 | CONFIG_PMIC_RK8XX=y |
c420ef67 | 71 | CONFIG_DM_REGULATOR_FIXED=y |
453c5a92 | 72 | CONFIG_REGULATOR_RK8XX=y |
c420ef67 SG |
73 | CONFIG_PWM_ROCKCHIP=y |
74 | CONFIG_RAM=y | |
75 | CONFIG_SPL_RAM=y | |
c420ef67 | 76 | CONFIG_DEBUG_UART_SHIFT=2 |
c420ef67 SG |
77 | CONFIG_ROCKCHIP_SERIAL=y |
78 | CONFIG_ROCKCHIP_SPI=y | |
79 | CONFIG_SYSRESET=y | |
ecad7051 | 80 | CONFIG_USB=y |
6574864d | 81 | CONFIG_ROCKCHIP_USB2_PHY=y |
7c8f00e4 | 82 | CONFIG_USB_STORAGE=y |
ecad7051 | 83 | CONFIG_USB_GADGET=y |
a95aee6a MR |
84 | CONFIG_USB_GADGET_MANUFACTURER="Rockchip" |
85 | CONFIG_USB_GADGET_VENDOR_NUM=0x2207 | |
86 | CONFIG_USB_GADGET_PRODUCT_NUM=0x320a | |
ecad7051 | 87 | CONFIG_USB_GADGET_DWC2_OTG=y |
4f60e5d3 | 88 | CONFIG_USB_FUNCTION_MASS_STORAGE=y |
c420ef67 SG |
89 | CONFIG_DM_VIDEO=y |
90 | CONFIG_DISPLAY=y | |
91 | CONFIG_VIDEO_ROCKCHIP=y | |
b98f0a3d | 92 | CONFIG_DISPLAY_ROCKCHIP_EDP=y |
fb82fe38 | 93 | CONFIG_DISPLAY_ROCKCHIP_HDMI=y |
c420ef67 SG |
94 | CONFIG_CONSOLE_SCROLL_LINES=10 |
95 | CONFIG_USE_TINY_PRINTF=y | |
96 | CONFIG_CMD_DHRYSTONE=y | |
97 | CONFIG_ERRNO_STR=y | |
c420ef67 | 98 | # CONFIG_SPL_OF_LIBFDT is not set |