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Commit | Line | Data |
---|---|---|
695693b2 | 1 | CONFIG_ARM=y |
a2ac2b96 | 2 | CONFIG_SKIP_LOWLEVEL_INIT=y |
abf8d963 | 3 | CONFIG_COUNTER_FREQUENCY=24000000 |
695693b2 | 4 | CONFIG_ARCH_ROCKCHIP=y |
98463903 | 5 | CONFIG_TEXT_BASE=0x00a00000 |
daec31e5 NC |
6 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
7 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | |
695693b2 | 8 | CONFIG_NR_DRAM_BANKS=2 |
54c5c2b8 | 9 | CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" |
695693b2 | 10 | CONFIG_ROCKCHIP_RK3568=y |
daec31e5 NC |
11 | CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y |
12 | CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y | |
13 | CONFIG_SPL_MMC=y | |
14 | CONFIG_SPL_SERIAL=y | |
daec31e5 | 15 | CONFIG_SPL_STACK_R_ADDR=0x600000 |
695693b2 JC |
16 | CONFIG_TARGET_EVB_RK3568=y |
17 | CONFIG_DEBUG_UART_BASE=0xFE660000 | |
18 | CONFIG_DEBUG_UART_CLOCK=24000000 | |
49c8ef0e | 19 | CONFIG_SYS_LOAD_ADDR=0xc00800 |
d46e86d2 | 20 | CONFIG_DEBUG_UART=y |
eaf6ea6a TR |
21 | CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y |
22 | CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 | |
daec31e5 NC |
23 | CONFIG_FIT=y |
24 | CONFIG_FIT_VERBOSE=y | |
25 | CONFIG_SPL_LOAD_FIT=y | |
695693b2 JC |
26 | CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" |
27 | # CONFIG_DISPLAY_CPUINFO is not set | |
28 | CONFIG_DISPLAY_BOARDINFO_LATE=y | |
ca8a329a TR |
29 | CONFIG_SPL_MAX_SIZE=0x20000 |
30 | CONFIG_SPL_PAD_TO=0x7f8000 | |
6600b355 TR |
31 | CONFIG_SPL_HAS_BSS_LINKER_SECTION=y |
32 | CONFIG_SPL_BSS_START_ADDR=0x4000000 | |
9b5f9aeb | 33 | CONFIG_SPL_BSS_MAX_SIZE=0x4000 |
daec31e5 | 34 | # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set |
f113d7d3 TR |
35 | # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set |
36 | CONFIG_SPL_STACK=0x400000 | |
daec31e5 | 37 | CONFIG_SPL_STACK_R=y |
daec31e5 | 38 | CONFIG_SPL_ATF=y |
695693b2 JC |
39 | CONFIG_CMD_GPT=y |
40 | CONFIG_CMD_MMC=y | |
41 | # CONFIG_CMD_SETEXPR is not set | |
daec31e5 NC |
42 | # CONFIG_SPL_DOS_PARTITION is not set |
43 | CONFIG_SPL_OF_CONTROL=y | |
44 | CONFIG_OF_LIVE=y | |
695693b2 | 45 | CONFIG_NET_RANDOM_ETHADDR=y |
daec31e5 NC |
46 | CONFIG_SPL_REGMAP=y |
47 | CONFIG_SPL_SYSCON=y | |
48 | CONFIG_SPL_CLK=y | |
695693b2 JC |
49 | CONFIG_ROCKCHIP_GPIO=y |
50 | CONFIG_SYS_I2C_ROCKCHIP=y | |
51 | CONFIG_MISC=y | |
d5bfef2f | 52 | CONFIG_SUPPORT_EMMC_RPMB=y |
695693b2 JC |
53 | CONFIG_MMC_DW=y |
54 | CONFIG_MMC_DW_ROCKCHIP=y | |
55 | CONFIG_MMC_SDHCI=y | |
56 | CONFIG_MMC_SDHCI_SDMA=y | |
57 | CONFIG_MMC_SDHCI_ROCKCHIP=y | |
695693b2 JC |
58 | CONFIG_ETH_DESIGNWARE=y |
59 | CONFIG_GMAC_ROCKCHIP=y | |
60 | CONFIG_REGULATOR_PWM=y | |
61 | CONFIG_PWM_ROCKCHIP=y | |
daec31e5 | 62 | CONFIG_SPL_RAM=y |
695693b2 JC |
63 | CONFIG_DM_RESET=y |
64 | CONFIG_BAUDRATE=1500000 | |
65 | CONFIG_DEBUG_UART_SHIFT=2 | |
66 | CONFIG_SYSRESET=y | |
67 | CONFIG_ERRNO_STR=y |