projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| d9c3417b | 1 | CONFIG_ARM=y |
| a2ac2b96 | 2 | CONFIG_SKIP_LOWLEVEL_INIT=y |
| abf8d963 | 3 | CONFIG_COUNTER_FREQUENCY=24000000 |
| d9c3417b | 4 | CONFIG_ARCH_ROCKCHIP=y |
| 98463903 | 5 | CONFIG_TEXT_BASE=0x00200000 |
| 83061dbd | 6 | CONFIG_SPL_GPIO=y |
| 554e5514 | 7 | CONFIG_NR_DRAM_BANKS=1 |
| fcb5117d TR |
8 | CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y |
| 9 | CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 | |
| c960c0fd | 10 | CONFIG_SF_DEFAULT_SPEED=20000000 |
| d9c3417b | 11 | CONFIG_ENV_OFFSET=0x3F8000 |
| 2bba7807 | 12 | CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e" |
| fcb5117d | 13 | CONFIG_DM_RESET=y |
| d9c3417b | 14 | CONFIG_ROCKCHIP_RK3328=y |
| 15 | CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y | |
| 16 | CONFIG_TPL_LIBCOMMON_SUPPORT=y | |
| 17 | CONFIG_TPL_LIBGENERIC_SUPPORT=y | |
| d9c3417b | 18 | CONFIG_SPL_STACK_R_ADDR=0x4000000 |
| fcb5117d TR |
19 | CONFIG_SPL_STACK=0x400000 |
| 20 | CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 | |
| d9c3417b | 21 | CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 |
| d9c3417b | 22 | CONFIG_DEBUG_UART_BASE=0xFF130000 |
| 23 | CONFIG_DEBUG_UART_CLOCK=24000000 | |
| d46e86d2 | 24 | CONFIG_SYS_LOAD_ADDR=0x800800 |
| d9c3417b | 25 | CONFIG_DEBUG_UART=y |
| d9c3417b | 26 | # CONFIG_ANDROID_BOOT_IMAGE is not set |
| 27 | CONFIG_FIT=y | |
| 28 | CONFIG_FIT_VERBOSE=y | |
| 1376592f | 29 | CONFIG_SPL_FIT_SIGNATURE=y |
| d9c3417b | 30 | CONFIG_SPL_LOAD_FIT=y |
| 1376592f | 31 | CONFIG_LEGACY_IMAGE_FORMAT=y |
| d9c3417b | 32 | CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb" |
| d9c3417b | 33 | # CONFIG_DISPLAY_CPUINFO is not set |
| 34 | CONFIG_DISPLAY_BOARDINFO_LATE=y | |
| 0817daa7 | 35 | CONFIG_MISC_INIT_R=y |
| ca8a329a TR |
36 | CONFIG_SPL_MAX_SIZE=0x40000 |
| 37 | CONFIG_SPL_PAD_TO=0x7f8000 | |
| 6600b355 TR |
38 | CONFIG_SPL_HAS_BSS_LINKER_SECTION=y |
| 39 | CONFIG_SPL_BSS_START_ADDR=0x2000000 | |
| 9b5f9aeb | 40 | CONFIG_SPL_BSS_MAX_SIZE=0x2000 |
| d9c3417b | 41 | # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set |
| f113d7d3 | 42 | # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set |
| d9c3417b | 43 | CONFIG_SPL_STACK_R=y |
| 7635defa | 44 | CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 |
| 933b2f09 | 45 | CONFIG_SPL_POWER=y |
| d9c3417b | 46 | CONFIG_SPL_ATF=y |
| 47 | CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y | |
| 41e47b42 | 48 | CONFIG_TPL_SYS_MALLOC_SIMPLE=y |
| d9c3417b | 49 | CONFIG_CMD_BOOTZ=y |
| 1376592f | 50 | CONFIG_CMD_GPIO=y |
| d9c3417b | 51 | CONFIG_CMD_GPT=y |
| 52 | CONFIG_CMD_MMC=y | |
| 53 | CONFIG_CMD_USB=y | |
| 54 | CONFIG_CMD_TIME=y | |
| 1376592f | 55 | CONFIG_CMD_REGULATOR=y |
| d9c3417b | 56 | CONFIG_SPL_OF_CONTROL=y |
| 57 | CONFIG_TPL_OF_CONTROL=y | |
| d9c3417b | 58 | CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" |
| 59 | CONFIG_TPL_OF_PLATDATA=y | |
| 60 | CONFIG_ENV_IS_IN_MMC=y | |
| 61 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | |
| 7d080773 | 62 | CONFIG_SYS_MMC_ENV_DEV=1 |
| d9c3417b | 63 | CONFIG_TPL_DM=y |
| 1376592f | 64 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| d9c3417b | 65 | CONFIG_REGMAP=y |
| 66 | CONFIG_SPL_REGMAP=y | |
| 67 | CONFIG_TPL_REGMAP=y | |
| 68 | CONFIG_SYSCON=y | |
| 69 | CONFIG_SPL_SYSCON=y | |
| 70 | CONFIG_TPL_SYSCON=y | |
| 71 | CONFIG_CLK=y | |
| 72 | CONFIG_SPL_CLK=y | |
| 73 | CONFIG_FASTBOOT_BUF_ADDR=0x800800 | |
| 74 | CONFIG_FASTBOOT_CMD_OEM_FORMAT=y | |
| 75 | CONFIG_ROCKCHIP_GPIO=y | |
| 76 | CONFIG_SYS_I2C_ROCKCHIP=y | |
| 5d334b70 | 77 | CONFIG_MISC=y |
| 1376592f | 78 | CONFIG_ROCKCHIP_EFUSE=y |
| d9c3417b | 79 | CONFIG_MMC_DW=y |
| 80 | CONFIG_MMC_DW_ROCKCHIP=y | |
| 33380a5a | 81 | CONFIG_PHY_REALTEK=y |
| 1376592f | 82 | CONFIG_DM_MDIO=y |
| 33380a5a | 83 | CONFIG_DM_ETH_PHY=y |
| 1376592f | 84 | CONFIG_PHY_GIGE=y |
| d9c3417b | 85 | CONFIG_ETH_DESIGNWARE=y |
| 86 | CONFIG_GMAC_ROCKCHIP=y | |
| b6fd3c63 | 87 | CONFIG_PHY_ROCKCHIP_INNO_USB2=y |
| d9c3417b | 88 | CONFIG_PINCTRL=y |
| 89 | CONFIG_SPL_PINCTRL=y | |
| 90 | CONFIG_DM_PMIC=y | |
| 91 | CONFIG_PMIC_RK8XX=y | |
| 92 | CONFIG_SPL_DM_REGULATOR=y | |
| d9c3417b | 93 | CONFIG_DM_REGULATOR_FIXED=y |
| 7635defa | 94 | CONFIG_SPL_DM_REGULATOR_FIXED=y |
| d9c3417b | 95 | CONFIG_REGULATOR_RK8XX=y |
| 96 | CONFIG_PWM_ROCKCHIP=y | |
| 97 | CONFIG_RAM=y | |
| 98 | CONFIG_SPL_RAM=y | |
| 99 | CONFIG_TPL_RAM=y | |
| 1376592f JK |
100 | CONFIG_DM_RNG=y |
| 101 | CONFIG_RNG_ROCKCHIP=y | |
| d9c3417b | 102 | CONFIG_BAUDRATE=1500000 |
| 103 | CONFIG_DEBUG_UART_SHIFT=2 | |
| 9591b635 | 104 | CONFIG_SYS_NS16550_MEM32=y |
| 74f11b55 TR |
105 | CONFIG_SYSINFO=y |
| 106 | CONFIG_SYSINFO_SMBIOS=y | |
| d9c3417b | 107 | CONFIG_SYSRESET=y |
| 108 | # CONFIG_TPL_SYSRESET is not set | |
| 109 | CONFIG_USB=y | |
| 110 | CONFIG_USB_XHCI_HCD=y | |
| d9c3417b | 111 | CONFIG_USB_EHCI_HCD=y |
| 112 | CONFIG_USB_EHCI_GENERIC=y | |
| 113 | CONFIG_USB_OHCI_HCD=y | |
| 114 | CONFIG_USB_OHCI_GENERIC=y | |
| 115 | CONFIG_USB_DWC2=y | |
| 116 | CONFIG_USB_DWC3=y | |
| 117 | # CONFIG_USB_DWC3_GADGET is not set | |
| df896743 | 118 | CONFIG_USB_DWC3_GENERIC=y |
| d9c3417b | 119 | CONFIG_USB_GADGET=y |
| 120 | CONFIG_USB_GADGET_DWC2_OTG=y | |
| 121 | CONFIG_SPL_TINY_MEMSET=y | |
| 122 | CONFIG_TPL_TINY_MEMSET=y | |
| 123 | CONFIG_ERRNO_STR=y |