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Commit | Line | Data |
---|---|---|
ae9996c8 SR |
1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_SOCFPGA=y | |
3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 | |
4 | CONFIG_SPL_DM=y | |
5 | CONFIG_DM_GPIO=y | |
6 | CONFIG_TARGET_SOCFPGA_SR1500=y | |
4edb9458 | 7 | CONFIG_SPL_STACK_R_ADDR=0x00800000 |
ae9996c8 SR |
8 | CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500" |
9 | CONFIG_SPL=y | |
10 | CONFIG_SPL_STACK_R=y | |
73223f0e | 11 | CONFIG_FIT=y |
ae9996c8 SR |
12 | # CONFIG_CMD_IMLS is not set |
13 | # CONFIG_CMD_FLASH is not set | |
4edb9458 | 14 | CONFIG_SPL_DM_SEQ_ALIAS=y |
ae9996c8 | 15 | CONFIG_DWAPB_GPIO=y |
4edb9458 | 16 | CONFIG_DM_MMC=y |
ae9996c8 | 17 | CONFIG_SPI_FLASH=y |
4edb9458 | 18 | # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set |
ae9996c8 SR |
19 | CONFIG_DM_ETH=y |
20 | CONFIG_ETH_DESIGNWARE=y | |
21 | CONFIG_SYS_NS16550=y |