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a8f88918 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 | * Alex Zuepke <azu@sysgo.de> | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | /* | |
30 | * CPU specific code | |
31 | */ | |
32 | ||
33 | #include <common.h> | |
34 | #include <command.h> | |
35 | #include <clps7111.h> | |
39539887 | 36 | #include <asm/hardware.h> |
a8f88918 WD |
37 | |
38 | int cpu_init (void) | |
39 | { | |
40 | /* | |
a8c7c708 | 41 | * setup up stacks if necessary |
a8f88918 WD |
42 | */ |
43 | #ifdef CONFIG_USE_IRQ | |
f6e20fc6 | 44 | IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; |
a8c7c708 | 45 | FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; |
a8f88918 | 46 | #endif |
a8c7c708 | 47 | return 0; |
a8f88918 WD |
48 | } |
49 | ||
50 | int cleanup_before_linux (void) | |
51 | { | |
52 | /* | |
53 | * this function is called just before we call linux | |
54 | * it prepares the processor for linux | |
55 | * | |
56 | * we turn off caches etc ... | |
57 | * and we set the CPU-speed to 73 MHz - see start.S for details | |
58 | */ | |
59 | ||
c570b2fd | 60 | #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) |
a8f88918 WD |
61 | unsigned long i; |
62 | ||
63 | disable_interrupts (); | |
39539887 | 64 | |
a8f88918 WD |
65 | /* turn off I-cache */ |
66 | asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); | |
67 | i &= ~0x1000; | |
68 | asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); | |
69 | ||
70 | /* flush I-cache */ | |
71 | asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); | |
a8f88918 WD |
72 | #ifdef CONFIG_ARM7_REVD |
73 | /* go to high speed */ | |
74 | IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; | |
39539887 WD |
75 | #endif |
76 | #elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) | |
77 | disable_interrupts (); | |
78 | /* Nothing more needed */ | |
79 | #else | |
80 | #error No cleanup_before_linux() defined for this CPU type | |
a8f88918 WD |
81 | #endif |
82 | return 0; | |
83 | } | |
84 | ||
85 | int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
86 | { | |
a8f88918 WD |
87 | disable_interrupts (); |
88 | reset_cpu (0); | |
89 | /*NOTREACHED*/ | |
90 | return (0); | |
91 | } | |
92 | ||
39539887 WD |
93 | /* |
94 | * Instruction and Data cache enable and disable functions | |
95 | * | |
96 | */ | |
97 | ||
c570b2fd | 98 | #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) |
39539887 WD |
99 | /* read co-processor 15, register #1 (control register) */ |
100 | static unsigned long read_p15_c1(void) | |
101 | { | |
102 | unsigned long value; | |
103 | ||
104 | __asm__ __volatile__( | |
105 | "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" | |
106 | : "=r" (value) | |
107 | : | |
108 | : "memory"); | |
109 | /* printf("p15/c1 is = %08lx\n", value); */ | |
110 | return value; | |
111 | } | |
112 | ||
113 | /* write to co-processor 15, register #1 (control register) */ | |
114 | static void write_p15_c1(unsigned long value) | |
115 | { | |
116 | /* printf("write %08lx to p15/c1\n", value); */ | |
117 | __asm__ __volatile__( | |
118 | "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" | |
119 | : | |
120 | : "r" (value) | |
121 | : "memory"); | |
122 | ||
123 | read_p15_c1(); | |
124 | } | |
125 | ||
126 | static void cp_delay (void) | |
127 | { | |
128 | volatile int i; | |
129 | ||
130 | /* copro seems to need some delay between reading and writing */ | |
131 | for (i = 0; i < 100; i++); | |
132 | } | |
133 | ||
134 | /* See also ARM Ref. Man. */ | |
135 | #define C1_MMU (1<<0) /* mmu off/on */ | |
136 | #define C1_ALIGN (1<<1) /* alignment faults off/on */ | |
137 | #define C1_IDC (1<<2) /* icache and/or dcache off/on */ | |
138 | #define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */ | |
139 | #define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ | |
140 | #define C1_SYS_PROT (1<<8) /* system protection */ | |
141 | #define C1_ROM_PROT (1<<9) /* ROM protection */ | |
142 | #define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ | |
143 | ||
a8f88918 WD |
144 | void icache_enable (void) |
145 | { | |
146 | ulong reg; | |
147 | ||
148 | reg = read_p15_c1 (); | |
149 | cp_delay (); | |
150 | write_p15_c1 (reg | C1_IDC); | |
151 | } | |
152 | ||
153 | void icache_disable (void) | |
154 | { | |
155 | ulong reg; | |
156 | ||
157 | reg = read_p15_c1 (); | |
158 | cp_delay (); | |
159 | write_p15_c1 (reg & ~C1_IDC); | |
160 | } | |
161 | ||
162 | int icache_status (void) | |
163 | { | |
164 | return (read_p15_c1 () & C1_IDC) != 0; | |
165 | } | |
166 | ||
167 | void dcache_enable (void) | |
168 | { | |
169 | ulong reg; | |
170 | ||
171 | reg = read_p15_c1 (); | |
172 | cp_delay (); | |
173 | write_p15_c1 (reg | C1_IDC); | |
174 | } | |
175 | ||
176 | void dcache_disable (void) | |
177 | { | |
178 | ulong reg; | |
179 | ||
180 | reg = read_p15_c1 (); | |
181 | cp_delay (); | |
182 | write_p15_c1 (reg & ~C1_IDC); | |
183 | } | |
184 | ||
185 | int dcache_status (void) | |
186 | { | |
187 | return (read_p15_c1 () & C1_IDC) != 0; | |
188 | } | |
39539887 WD |
189 | |
190 | #elif defined(CONFIG_S3C4510B) | |
191 | ||
192 | void icache_enable (void) | |
193 | { | |
194 | s32 i; | |
195 | ||
196 | /* disable all cache bits */ | |
197 | CLR_REG( REG_SYSCFG, 0x3F); | |
198 | ||
199 | /* 8KB cache, write enable */ | |
200 | SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); | |
201 | ||
202 | /* clear TAG RAM bits */ | |
203 | for ( i = 0; i < 256; i++) | |
204 | PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); | |
205 | ||
206 | /* clear SET0 RAM */ | |
207 | for(i=0; i < 1024; i++) | |
208 | PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); | |
209 | ||
210 | /* clear SET1 RAM */ | |
211 | for(i=0; i < 1024; i++) | |
212 | PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); | |
213 | ||
214 | /* enable cache */ | |
215 | SET_REG( REG_SYSCFG, CACHE_ENABLE); | |
216 | ||
217 | } | |
218 | ||
219 | void icache_disable (void) | |
220 | { | |
221 | /* disable all cache bits */ | |
222 | CLR_REG( REG_SYSCFG, 0x3F); | |
223 | } | |
224 | ||
225 | int icache_status (void) | |
226 | { | |
227 | return GET_REG( REG_SYSCFG) & CACHE_ENABLE; | |
228 | } | |
229 | ||
230 | void dcache_enable (void) | |
231 | { | |
232 | /* we don't have seperate instruction/data caches */ | |
233 | icache_enable(); | |
234 | } | |
235 | ||
236 | void dcache_disable (void) | |
237 | { | |
238 | /* we don't have seperate instruction/data caches */ | |
239 | icache_disable(); | |
240 | } | |
241 | ||
242 | int dcache_status (void) | |
243 | { | |
244 | /* we don't have seperate instruction/data caches */ | |
245 | return icache_status(); | |
246 | } | |
247 | ||
248 | #else | |
249 | #error No icache/dcache enable/disable functions defined for this CPU type | |
250 | #endif |