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dc7c9a1a WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Lineo, Inc. <www.lineo.com> | |
4 | * Bernhard Kuhn <bkuhn@lineo.com> | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 | * Marius Groeger <mgroeger@sysgo.de> | |
9 | * | |
10 | * (C) Copyright 2002 | |
11 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
12 | * Alex Zuepke <azu@sysgo.de> | |
13 | * | |
14 | * See file CREDITS for list of people who contributed to this | |
15 | * project. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or | |
18 | * modify it under the terms of the GNU General Public License as | |
19 | * published by the Free Software Foundation; either version 2 of | |
20 | * the License, or (at your option) any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software | |
29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
30 | * MA 02111-1307 USA | |
31 | */ | |
32 | ||
33 | #include <common.h> | |
a85f9f21 | 34 | /*#include <asm/io.h>*/ |
b783edae | 35 | #include <asm/arch/hardware.h> |
a85f9f21 | 36 | /*#include <asm/proc/ptrace.h>*/ |
dc7c9a1a | 37 | |
6d0f6bcf JCPV |
38 | /* the number of clocks per CONFIG_SYS_HZ */ |
39 | #define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) | |
dc7c9a1a WD |
40 | |
41 | /* macro to read the 16 bit timer */ | |
d9df1f4e | 42 | #define READ_TIMER (tmr->TC_CV & 0x0000ffff) |
dc7c9a1a WD |
43 | AT91PS_TC tmr; |
44 | ||
dc7c9a1a WD |
45 | static ulong timestamp; |
46 | static ulong lastinc; | |
47 | ||
b54384e3 | 48 | int timer_init (void) |
dc7c9a1a | 49 | { |
d9df1f4e WD |
50 | tmr = AT91C_BASE_TC0; |
51 | ||
52 | /* enables TC1.0 clock */ | |
53 | *AT91C_PMC_PCER = 1 << AT91C_ID_TC0; /* enable clock */ | |
dc7c9a1a | 54 | |
d9df1f4e WD |
55 | *AT91C_TCB0_BCR = 0; |
56 | *AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE; | |
57 | tmr->TC_CCR = AT91C_TC_CLKDIS; | |
9455b7f3 WD |
58 | #define AT91C_TC_CMR_CPCTRG (1 << 14) |
59 | /* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */ | |
60 | tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG; | |
dc7c9a1a | 61 | |
d9df1f4e WD |
62 | tmr->TC_IDR = ~0ul; |
63 | tmr->TC_RC = TIMER_LOAD_VAL; | |
9455b7f3 | 64 | lastinc = 0; |
d9df1f4e WD |
65 | tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN; |
66 | timestamp = 0; | |
dc7c9a1a | 67 | |
d9df1f4e | 68 | return (0); |
dc7c9a1a WD |
69 | } |
70 | ||
71 | /* | |
72 | * timer without interrupts | |
73 | */ | |
74 | ||
d9df1f4e | 75 | void reset_timer (void) |
dc7c9a1a | 76 | { |
d9df1f4e | 77 | reset_timer_masked (); |
dc7c9a1a WD |
78 | } |
79 | ||
80 | ulong get_timer (ulong base) | |
81 | { | |
d9df1f4e | 82 | return get_timer_masked () - base; |
dc7c9a1a WD |
83 | } |
84 | ||
85 | void set_timer (ulong t) | |
86 | { | |
d9df1f4e | 87 | timestamp = t; |
dc7c9a1a WD |
88 | } |
89 | ||
d9df1f4e | 90 | void udelay (unsigned long usec) |
dc7c9a1a | 91 | { |
d9df1f4e | 92 | udelay_masked(usec); |
dc7c9a1a WD |
93 | } |
94 | ||
d9df1f4e | 95 | void reset_timer_masked (void) |
dc7c9a1a | 96 | { |
d9df1f4e WD |
97 | /* reset time */ |
98 | lastinc = READ_TIMER; | |
99 | timestamp = 0; | |
dc7c9a1a WD |
100 | } |
101 | ||
9455b7f3 | 102 | ulong get_timer_raw (void) |
dc7c9a1a | 103 | { |
d9df1f4e WD |
104 | ulong now = READ_TIMER; |
105 | ||
106 | if (now >= lastinc) { | |
107 | /* normal mode */ | |
108 | timestamp += now - lastinc; | |
109 | } else { | |
110 | /* we have an overflow ... */ | |
111 | timestamp += now + TIMER_LOAD_VAL - lastinc; | |
112 | } | |
113 | lastinc = now; | |
114 | ||
115 | return timestamp; | |
dc7c9a1a WD |
116 | } |
117 | ||
9455b7f3 WD |
118 | ulong get_timer_masked (void) |
119 | { | |
120 | return get_timer_raw()/TIMER_LOAD_VAL; | |
121 | } | |
122 | ||
d9df1f4e | 123 | void udelay_masked (unsigned long usec) |
dc7c9a1a | 124 | { |
d9df1f4e | 125 | ulong tmo; |
101e8dfa WD |
126 | ulong endtime; |
127 | signed long diff; | |
d9df1f4e | 128 | |
6d0f6bcf | 129 | tmo = CONFIG_SYS_HZ_CLOCK / 1000; |
9455b7f3 | 130 | tmo *= usec; |
d9df1f4e WD |
131 | tmo /= 1000; |
132 | ||
101e8dfa | 133 | endtime = get_timer_raw () + tmo; |
d9df1f4e | 134 | |
101e8dfa WD |
135 | do { |
136 | ulong now = get_timer_raw (); | |
137 | diff = endtime - now; | |
138 | } while (diff >= 0); | |
d9df1f4e | 139 | } |
dc7c9a1a | 140 | |
d9df1f4e WD |
141 | /* |
142 | * This function is derived from PowerPC code (read timebase as long long). | |
143 | * On ARM it just returns the timer value. | |
144 | */ | |
145 | unsigned long long get_ticks(void) | |
146 | { | |
147 | return get_timer(0); | |
148 | } | |
dc7c9a1a | 149 | |
d9df1f4e WD |
150 | /* |
151 | * This function is derived from PowerPC code (timebase clock frequency). | |
152 | * On ARM it returns the number of timer ticks per second. | |
153 | */ | |
154 | ulong get_tbclk (void) | |
155 | { | |
156 | ulong tbclk; | |
dc7c9a1a | 157 | |
6d0f6bcf | 158 | tbclk = CONFIG_SYS_HZ; |
d9df1f4e | 159 | return tbclk; |
dc7c9a1a | 160 | } |