]>
Commit | Line | Data |
---|---|---|
281e00a3 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
8 | * Alex Zuepke <azu@sysgo.de> | |
9 | * | |
10 | * (C) Copyright 2002 | |
11 | * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> | |
12 | * | |
13 | * See file CREDITS for list of people who contributed to this | |
14 | * project. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License as | |
18 | * published by the Free Software Foundation; either version 2 of | |
19 | * the License, or (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
29 | * MA 02111-1307 USA | |
30 | */ | |
31 | ||
32 | #include <common.h> | |
33 | #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) | |
34 | ||
35 | #include <arm920t.h> | |
36 | #if defined(CONFIG_S3C2400) | |
37 | #include <s3c2400.h> | |
38 | #elif defined(CONFIG_S3C2410) | |
39 | #include <s3c2410.h> | |
40 | #endif | |
41 | ||
281e00a3 WD |
42 | int timer_load_val = 0; |
43 | ||
44 | /* macro to read the 16 bit timer */ | |
45 | static inline ulong READ_TIMER(void) | |
46 | { | |
47 | S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); | |
48 | ||
49 | return (timers->TCNTO4 & 0xffff); | |
50 | } | |
51 | ||
52 | static ulong timestamp; | |
53 | static ulong lastdec; | |
54 | ||
55 | int interrupt_init (void) | |
56 | { | |
57 | S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); | |
58 | ||
59 | /* use PWM Timer 4 because it has no output */ | |
60 | /* prescaler for Timer 4 is 16 */ | |
61 | timers->TCFG0 = 0x0f00; | |
62 | if (timer_load_val == 0) | |
63 | { | |
64 | /* | |
65 | * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 | |
66 | * (default) and prescaler = 16. Should be 10390 | |
67 | * @33.25MHz and 15625 @ 50 MHz | |
68 | */ | |
69 | timer_load_val = get_PCLK()/(2 * 16 * 100); | |
70 | } | |
71 | /* load value for 10 ms timeout */ | |
72 | lastdec = timers->TCNTB4 = timer_load_val; | |
73 | /* auto load, manual update of Timer 4 */ | |
74 | timers->TCON = (timers->TCON & ~0x0700000) | 0x600000; | |
75 | /* auto load, start Timer 4 */ | |
76 | timers->TCON = (timers->TCON & ~0x0700000) | 0x500000; | |
77 | timestamp = 0; | |
78 | ||
79 | return (0); | |
80 | } | |
81 | ||
82 | /* | |
83 | * timer without interrupts | |
84 | */ | |
85 | ||
86 | void reset_timer (void) | |
87 | { | |
88 | reset_timer_masked (); | |
89 | } | |
90 | ||
91 | ulong get_timer (ulong base) | |
92 | { | |
93 | return get_timer_masked () - base; | |
94 | } | |
95 | ||
96 | void set_timer (ulong t) | |
97 | { | |
98 | timestamp = t; | |
99 | } | |
100 | ||
101 | void udelay (unsigned long usec) | |
102 | { | |
103 | ulong tmo; | |
104 | ulong start = get_timer(0); | |
105 | ||
106 | tmo = usec / 1000; | |
107 | tmo *= (timer_load_val * 100); | |
108 | tmo /= 1000; | |
109 | ||
110 | while ((ulong)(get_timer_masked () - start) < tmo) | |
111 | /*NOP*/; | |
112 | } | |
113 | ||
114 | void reset_timer_masked (void) | |
115 | { | |
116 | /* reset time */ | |
117 | lastdec = READ_TIMER(); | |
118 | timestamp = 0; | |
119 | } | |
120 | ||
121 | ulong get_timer_masked (void) | |
122 | { | |
123 | ulong now = READ_TIMER(); | |
124 | ||
125 | if (lastdec >= now) { | |
126 | /* normal mode */ | |
127 | timestamp += lastdec - now; | |
128 | } else { | |
129 | /* we have an overflow ... */ | |
130 | timestamp += lastdec + timer_load_val - now; | |
131 | } | |
132 | lastdec = now; | |
133 | ||
134 | return timestamp; | |
135 | } | |
136 | ||
137 | void udelay_masked (unsigned long usec) | |
138 | { | |
139 | ulong tmo; | |
101e8dfa WD |
140 | ulong endtime; |
141 | signed long diff; | |
281e00a3 | 142 | |
101e8dfa WD |
143 | if (usec >= 1000) { |
144 | tmo = usec / 1000; | |
145 | tmo *= (timer_load_val * 100); | |
146 | tmo /= 1000; | |
147 | } else { | |
148 | tmo = usec * (timer_load_val * 100); | |
149 | tmo /= (1000*1000); | |
150 | } | |
281e00a3 | 151 | |
101e8dfa | 152 | endtime = get_timer_masked () + tmo; |
281e00a3 | 153 | |
101e8dfa WD |
154 | do { |
155 | ulong now = get_timer_masked (); | |
156 | diff = endtime - now; | |
157 | } while (diff >= 0); | |
281e00a3 WD |
158 | } |
159 | ||
160 | /* | |
161 | * This function is derived from PowerPC code (read timebase as long long). | |
162 | * On ARM it just returns the timer value. | |
163 | */ | |
164 | unsigned long long get_ticks(void) | |
165 | { | |
166 | return get_timer(0); | |
167 | } | |
168 | ||
169 | /* | |
170 | * This function is derived from PowerPC code (timebase clock frequency). | |
171 | * On ARM it returns the number of timer ticks per second. | |
172 | */ | |
173 | ulong get_tbclk (void) | |
174 | { | |
175 | ulong tbclk; | |
176 | ||
177 | #if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB) | |
178 | tbclk = timer_load_val * 100; | |
32cb2c70 WD |
179 | #elif defined(CONFIG_SBC2410X) || \ |
180 | defined(CONFIG_SMDK2410) || \ | |
181 | defined(CONFIG_VCMA9) | |
6d0f6bcf | 182 | tbclk = CONFIG_SYS_HZ; |
281e00a3 WD |
183 | #else |
184 | # error "tbclk not configured" | |
185 | #endif | |
186 | ||
187 | return tbclk; | |
188 | } | |
189 | ||
b304c968 WD |
190 | /* |
191 | * reset the cpu by setting up the watchdog timer and let him time out | |
192 | */ | |
193 | void reset_cpu (ulong ignored) | |
194 | { | |
3c2b3d45 | 195 | volatile S3C24X0_WATCHDOG * watchdog; |
b304c968 WD |
196 | |
197 | #ifdef CONFIG_TRAB | |
3c2b3d45 WD |
198 | extern void disable_vfd (void); |
199 | ||
b304c968 WD |
200 | disable_vfd(); |
201 | #endif | |
202 | ||
203 | watchdog = S3C24X0_GetBase_WATCHDOG(); | |
204 | ||
205 | /* Disable watchdog */ | |
206 | watchdog->WTCON = 0x0000; | |
207 | ||
208 | /* Initialize watchdog timer count register */ | |
209 | watchdog->WTCNT = 0x0001; | |
210 | ||
211 | /* Enable watchdog timer; assert reset at timer timeout */ | |
212 | watchdog->WTCON = 0x0021; | |
213 | ||
214 | while(1); /* loop forever and wait for reset to happen */ | |
215 | ||
216 | /*NOTREACHED*/ | |
217 | } | |
218 | ||
be19bd5c HW |
219 | #ifdef CONFIG_USE_IRQ |
220 | void s3c2410_irq(void) | |
221 | { | |
222 | S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT(); | |
223 | u_int32_t intpnd = irq->INTPND; | |
224 | ||
225 | } | |
226 | #endif /* USE_IRQ */ | |
227 | ||
281e00a3 | 228 | #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ |