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* Patches by David Müller, 14 Nov 2003:
[people/ms/u-boot.git] / cpu / arm920t / usb_ohci.c
CommitLineData
149dded2
WD		 1/*
2 * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400.
3 *
4 * (C) Copyright 2003
5 * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 *
25 * Note: Part of this code has been derived from linux
26 *
27 */
28/*
29 * IMPORTANT NOTES
30 * 1 - you MUST define LITTLEENDIAN in the configuration file for the
31 * board or this driver will NOT work!
32 * 2 - this driver is intended for use with USB Mass Storage Devices
33 * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
34 */
35
36#include <common.h>
a2663ea4 37/* #include <pci.h> no PCI on the S3C24X0 */
149dded2
WD		 38
39#ifdef CONFIG_USB_OHCI
40
a2663ea4 41#if defined(CONFIG_S3C2400)
149dded2 42#include <s3c2400.h>
a2663ea4
WD		 43#elif defined(CONFIG_S3C2410)
44#include <s3c2410.h>
45#endif
46
149dded2
WD		 47#include <malloc.h>
48#include <usb.h>
49#include "usb_ohci.h"
50
51#define OHCI_USE_NPS /* force NoPowerSwitching mode */
52#undef OHCI_VERBOSE_DEBUG /* not always helpful */
53
54
55/* For initializing controller (mask in an HCFS mode too) */
56#define OHCI_CONTROL_INIT \
57 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
58
149dded2
WD		 59#define readl(a) (*((vu_long *)(a)))
60#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
61
62#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
63
64#undef DEBUG
65#ifdef DEBUG
66#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
67#else
68#define dbg(format, arg...) do {} while(0)
69#endif /* DEBUG */
70#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
71#undef SHOW_INFO
72#ifdef SHOW_INFO
73#define info(format, arg...) printf("INFO: " format "\n", ## arg)
74#else
75#define info(format, arg...) do {} while(0)
76#endif
77
78#define m16_swap(x) swap_16(x)
79#define m32_swap(x) swap_32(x)
80
81/* global ohci_t */
82static ohci_t gohci;
83/* this must be aligned to a 256 byte boundary */
84struct ohci_hcca ghcca[1];
85/* a pointer to the aligned storage */
86struct ohci_hcca *phcca;
87/* this allocates EDs for all possible endpoints */
88struct ohci_device ohci_dev;
89/* urb_priv */
90urb_priv_t urb_priv;
8a42eac7 91/* RHSC flag */
92int got_rhsc;
93/* device which was disconnected */
94struct usb_device *devgone;
149dded2
WD		 95
96/*-------------------------------------------------------------------------*/
97
98/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
99 * The erratum (#4) description is incorrect. AMD's workaround waits
100 * till some bits (mostly reserved) are clear; ok for all revs.
101 */
102#define OHCI_QUIRK_AMD756 0xabcd
103#define read_roothub(hc, register, mask) ({ \
104 u32 temp = readl (&hc->regs->roothub.register); \
105 if (hc->flags & OHCI_QUIRK_AMD756) \
106 while (temp & mask) \
107 temp = readl (&hc->regs->roothub.register); \
108 temp; })
109
110static u32 roothub_a (struct ohci *hc)
111 { return read_roothub (hc, a, 0xfc0fe000); }
112static inline u32 roothub_b (struct ohci *hc)
113 { return readl (&hc->regs->roothub.b); }
114static inline u32 roothub_status (struct ohci *hc)
115 { return readl (&hc->regs->roothub.status); }
116static u32 roothub_portstatus (struct ohci *hc, int i)
117 { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
118
119
120/* forward declaration */
121static int hc_interrupt (void);
122static void
123td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
124 int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
125
126/*-------------------------------------------------------------------------*
127 * URB support functions
128 *-------------------------------------------------------------------------*/
129
130/* free HCD-private data associated with this URB */
131
132static void urb_free_priv (urb_priv_t * urb)
133{
134 int i;
135 int last;
136 struct td * td;
137
138 last = urb->length - 1;
139 if (last >= 0) {
140 for (i = 0; i <= last; i++) {
141 td = urb->td[i];
142 if (td) {
143 td->usb_dev = NULL;
144 urb->td[i] = NULL;
145 }
146 }
147 }
148}
149
150/*-------------------------------------------------------------------------*/
151
152#ifdef DEBUG
153static int sohci_get_current_frame_number (struct usb_device * dev);
154
155/* debug| print the main components of an URB
156 * small: 0) header + data packets 1) just header */
157
158static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
159 int transfer_len, struct devrequest * setup, char * str, int small)
160{
161 urb_priv_t * purb = &urb_priv;
162
163 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
164 str,
42d1f039
WD		 165 sohci_get_current_frame_number (dev),
166 usb_pipedevice (pipe),
167 usb_pipeendpoint (pipe),
168 usb_pipeout (pipe)? 'O': 'I',
169 usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
170 (usb_pipecontrol (pipe)? "CTRL": "BULK"),
171 purb->actual_length,
172 transfer_len, dev->status);
149dded2
WD		 173#ifdef OHCI_VERBOSE_DEBUG
174 if (!small) {
175 int i, len;
176
177 if (usb_pipecontrol (pipe)) {
178 printf (__FILE__ ": cmd(8):");
179 for (i = 0; i < 8 ; i++)
180 printf (" %02x", ((__u8 *) setup) [i]);
181 printf ("\n");
182 }
183 if (transfer_len > 0 && buffer) {
184 printf (__FILE__ ": data(%d/%d):",
185 purb->actual_length,
186 transfer_len);
187 len = usb_pipeout (pipe)?
188 transfer_len: purb->actual_length;
189 for (i = 0; i < 16 && i < len; i++)
190 printf (" %02x", ((__u8 *) buffer) [i]);
191 printf ("%s\n", i < len? "...": "");
192 }
193 }
194#endif
195}
196
197/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
198void ep_print_int_eds (ohci_t *ohci, char * str) {
199 int i, j;
200 __u32 * ed_p;
201 for (i= 0; i < 32; i++) {
202 j = 5;
203 ed_p = &(ohci->hcca->int_table [i]);
204 if (*ed_p == 0)
205 continue;
206 printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
207 while (*ed_p != 0 && j--) {
208 ed_t *ed = (ed_t *)m32_swap(ed_p);
209 printf (" ed: %4x;", ed->hwINFO);
210 ed_p = &ed->hwNextED;
211 }
212 printf ("\n");
213 }
214}
215
216static void ohci_dump_intr_mask (char *label, __u32 mask)
217{
218 dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
219 label,
220 mask,
221 (mask & OHCI_INTR_MIE) ? " MIE" : "",
222 (mask & OHCI_INTR_OC) ? " OC" : "",
223 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
224 (mask & OHCI_INTR_FNO) ? " FNO" : "",
225 (mask & OHCI_INTR_UE) ? " UE" : "",
226 (mask & OHCI_INTR_RD) ? " RD" : "",
227 (mask & OHCI_INTR_SF) ? " SF" : "",
228 (mask & OHCI_INTR_WDH) ? " WDH" : "",
229 (mask & OHCI_INTR_SO) ? " SO" : ""
230 );
231}
232
233static void maybe_print_eds (char *label, __u32 value)
234{
235 ed_t *edp = (ed_t *)value;
236
237 if (value) {
238 dbg ("%s %08x", label, value);
239 dbg ("%08x", edp->hwINFO);
240 dbg ("%08x", edp->hwTailP);
241 dbg ("%08x", edp->hwHeadP);
242 dbg ("%08x", edp->hwNextED);
243 }
244}
245
246static char * hcfs2string (int state)
247{
248 switch (state) {
249 case OHCI_USB_RESET: return "reset";
250 case OHCI_USB_RESUME: return "resume";
251 case OHCI_USB_OPER: return "operational";
252 case OHCI_USB_SUSPEND: return "suspend";
253 }
254 return "?";
255}
256
257/* dump control and status registers */
258static void ohci_dump_status (ohci_t *controller)
259{
260 struct ohci_regs *regs = controller->regs;
261 __u32 temp;
262
263 temp = readl (&regs->revision) & 0xff;
264 if (temp != 0x10)
265 dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
266
267 temp = readl (&regs->control);
268 dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
269 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
270 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
271 (temp & OHCI_CTRL_IR) ? " IR" : "",
272 hcfs2string (temp & OHCI_CTRL_HCFS),
273 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
274 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
275 (temp & OHCI_CTRL_IE) ? " IE" : "",
276 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
277 temp & OHCI_CTRL_CBSR
278 );
279
280 temp = readl (&regs->cmdstatus);
281 dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
282 (temp & OHCI_SOC) >> 16,
283 (temp & OHCI_OCR) ? " OCR" : "",
284 (temp & OHCI_BLF) ? " BLF" : "",
285 (temp & OHCI_CLF) ? " CLF" : "",
286 (temp & OHCI_HCR) ? " HCR" : ""
287 );
288
289 ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
290 ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
291
292 maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
293
294 maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
295 maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
296
297 maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
298 maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
299
300 maybe_print_eds ("donehead", readl (&regs->donehead));
301}
302
303static void ohci_dump_roothub (ohci_t *controller, int verbose)
304{
305 __u32 temp, ndp, i;
306
307 temp = roothub_a (controller);
308 ndp = (temp & RH_A_NDP);
309
310 if (verbose) {
311 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
312 ((temp & RH_A_POTPGT) >> 24) & 0xff,
313 (temp & RH_A_NOCP) ? " NOCP" : "",
314 (temp & RH_A_OCPM) ? " OCPM" : "",
315 (temp & RH_A_DT) ? " DT" : "",
316 (temp & RH_A_NPS) ? " NPS" : "",
317 (temp & RH_A_PSM) ? " PSM" : "",
318 ndp
319 );
320 temp = roothub_b (controller);
321 dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
322 temp,
323 (temp & RH_B_PPCM) >> 16,
324 (temp & RH_B_DR)
325 );
326 temp = roothub_status (controller);
327 dbg ("roothub.status: %08x%s%s%s%s%s%s",
328 temp,
329 (temp & RH_HS_CRWE) ? " CRWE" : "",
330 (temp & RH_HS_OCIC) ? " OCIC" : "",
331 (temp & RH_HS_LPSC) ? " LPSC" : "",
332 (temp & RH_HS_DRWE) ? " DRWE" : "",
333 (temp & RH_HS_OCI) ? " OCI" : "",
334 (temp & RH_HS_LPS) ? " LPS" : ""
335 );
336 }
337
338 for (i = 0; i < ndp; i++) {
339 temp = roothub_portstatus (controller, i);
340 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
341 i,
342 temp,
343 (temp & RH_PS_PRSC) ? " PRSC" : "",
344 (temp & RH_PS_OCIC) ? " OCIC" : "",
345 (temp & RH_PS_PSSC) ? " PSSC" : "",
346 (temp & RH_PS_PESC) ? " PESC" : "",
347 (temp & RH_PS_CSC) ? " CSC" : "",
348
349 (temp & RH_PS_LSDA) ? " LSDA" : "",
350 (temp & RH_PS_PPS) ? " PPS" : "",
351 (temp & RH_PS_PRS) ? " PRS" : "",
352 (temp & RH_PS_POCI) ? " POCI" : "",
353 (temp & RH_PS_PSS) ? " PSS" : "",
354
355 (temp & RH_PS_PES) ? " PES" : "",
356 (temp & RH_PS_CCS) ? " CCS" : ""
357 );
358 }
359}
360
361static void ohci_dump (ohci_t *controller, int verbose)
362{
363 dbg ("OHCI controller usb-%s state", controller->slot_name);
364
365 /* dumps some of the state we know about */
366 ohci_dump_status (controller);
367 if (verbose)
368 ep_print_int_eds (controller, "hcca");
369 dbg ("hcca frame #%04x", controller->hcca->frame_no);
370 ohci_dump_roothub (controller, 1);
371}
372
373
374#endif /* DEBUG */
375
376/*-------------------------------------------------------------------------*
377 * Interface functions (URB)
378 *-------------------------------------------------------------------------*/
379
380/* get a transfer request */
381
382int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
383 int transfer_len, struct devrequest *setup, int interval)
384{
385 ohci_t *ohci;
386 ed_t * ed;
387 urb_priv_t *purb_priv;
388 int i, size = 0;
389
390 ohci = &gohci;
391
392 /* when controller's hung, permit only roothub cleanup attempts
393 * such as powering down ports */
394 if (ohci->disabled) {
395 err("sohci_submit_job: EPIPE");
396 return -1;
397 }
398
399 /* every endpoint has a ed, locate and fill it */
400 if (!(ed = ep_add_ed (dev, pipe))) {
401 err("sohci_submit_job: ENOMEM");
402 return -1;
403 }
404
405 /* for the private part of the URB we need the number of TDs (size) */
406 switch (usb_pipetype (pipe)) {
407 case PIPE_BULK: /* one TD for every 4096 Byte */
408 size = (transfer_len - 1) / 4096 + 1;
409 break;
410 case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
411 size = (transfer_len == 0)? 2:
412 (transfer_len - 1) / 4096 + 3;
413 break;
414 }
415
416 if (size >= (N_URB_TD - 1)) {
417 err("need %d TDs, only have %d", size, N_URB_TD);
418 return -1;
419 }
420 purb_priv = &urb_priv;
421 purb_priv->pipe = pipe;
422
423 /* fill the private part of the URB */
424 purb_priv->length = size;
425 purb_priv->ed = ed;
426 purb_priv->actual_length = 0;
427
428 /* allocate the TDs */
429 /* note that td[0] was allocated in ep_add_ed */
430 for (i = 0; i < size; i++) {
431 purb_priv->td[i] = td_alloc (dev);
432 if (!purb_priv->td[i]) {
433 purb_priv->length = i;
434 urb_free_priv (purb_priv);
435 err("sohci_submit_job: ENOMEM");
436 return -1;
437 }
438 }
439
440 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
441 urb_free_priv (purb_priv);
442 err("sohci_submit_job: EINVAL");
443 return -1;
444 }
445
446 /* link the ed into a chain if is not already */
447 if (ed->state != ED_OPER)
448 ep_link (ohci, ed);
449
450 /* fill the TDs and link it to the ed */
451 td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
452
453 return 0;
454}
455
456/*-------------------------------------------------------------------------*/
457
458#ifdef DEBUG
459/* tell us the current USB frame number */
460
461static int sohci_get_current_frame_number (struct usb_device *usb_dev)
462{
463 ohci_t *ohci = &gohci;
464
465 return m16_swap (ohci->hcca->frame_no);
466}
467#endif
468
469/*-------------------------------------------------------------------------*
470 * ED handling functions
471 *-------------------------------------------------------------------------*/
472
473/* link an ed into one of the HC chains */
474
475static int ep_link (ohci_t *ohci, ed_t *edi)
476{
477 volatile ed_t *ed = edi;
478
479 ed->state = ED_OPER;
480
481 switch (ed->type) {
482 case PIPE_CONTROL:
483 ed->hwNextED = 0;
484 if (ohci->ed_controltail == NULL) {
485 writel (ed, &ohci->regs->ed_controlhead);
486 } else {
487 ohci->ed_controltail->hwNextED = m32_swap (ed);
488 }
489 ed->ed_prev = ohci->ed_controltail;
490 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
491 !ohci->ed_rm_list[1] && !ohci->sleeping) {
492 ohci->hc_control |= OHCI_CTRL_CLE;
493 writel (ohci->hc_control, &ohci->regs->control);
494 }
495 ohci->ed_controltail = edi;
496 break;
497
498 case PIPE_BULK:
499 ed->hwNextED = 0;
500 if (ohci->ed_bulktail == NULL) {
501 writel (ed, &ohci->regs->ed_bulkhead);
502 } else {
503 ohci->ed_bulktail->hwNextED = m32_swap (ed);
504 }
505 ed->ed_prev = ohci->ed_bulktail;
506 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
507 !ohci->ed_rm_list[1] && !ohci->sleeping) {
508 ohci->hc_control |= OHCI_CTRL_BLE;
509 writel (ohci->hc_control, &ohci->regs->control);
510 }
511 ohci->ed_bulktail = edi;
512 break;
513 }
514 return 0;
515}
516
517/*-------------------------------------------------------------------------*/
518
519/* unlink an ed from one of the HC chains.
520 * just the link to the ed is unlinked.
521 * the link from the ed still points to another operational ed or 0
522 * so the HC can eventually finish the processing of the unlinked ed */
523
524static int ep_unlink (ohci_t *ohci, ed_t *ed)
525{
526 ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
527
528 switch (ed->type) {
529 case PIPE_CONTROL:
530 if (ed->ed_prev == NULL) {
531 if (!ed->hwNextED) {
532 ohci->hc_control &= ~OHCI_CTRL_CLE;
533 writel (ohci->hc_control, &ohci->regs->control);
534 }
535 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
536 } else {
537 ed->ed_prev->hwNextED = ed->hwNextED;
538 }
539 if (ohci->ed_controltail == ed) {
540 ohci->ed_controltail = ed->ed_prev;
541 } else {
542 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
543 }
544 break;
545
546 case PIPE_BULK:
547 if (ed->ed_prev == NULL) {
548 if (!ed->hwNextED) {
549 ohci->hc_control &= ~OHCI_CTRL_BLE;
550 writel (ohci->hc_control, &ohci->regs->control);
551 }
552 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
553 } else {
554 ed->ed_prev->hwNextED = ed->hwNextED;
555 }
556 if (ohci->ed_bulktail == ed) {
557 ohci->ed_bulktail = ed->ed_prev;
558 } else {
559 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
560 }
561 break;
562 }
563 ed->state = ED_UNLINK;
564 return 0;
565}
566
567
568/*-------------------------------------------------------------------------*/
569
570/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
571 * but the USB stack is a little bit stateless so we do it at every transaction
572 * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
573 * in all other cases the state is left unchanged
574 * the ed info fields are setted anyway even though most of them should not change */
575
576static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
577{
578 td_t *td;
579 ed_t *ed_ret;
580 volatile ed_t *ed;
581
582 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
583 (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
584
585 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
586 err("ep_add_ed: pending delete");
587 /* pending delete request */
588 return NULL;
589 }
590
591 if (ed->state == ED_NEW) {
592 ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
42d1f039 593 /* dummy td; end of td list for ed */
149dded2
WD		 594 td = td_alloc (usb_dev);
595 ed->hwTailP = m32_swap (td);
596 ed->hwHeadP = ed->hwTailP;
597 ed->state = ED_UNLINK;
598 ed->type = usb_pipetype (pipe);
599 ohci_dev.ed_cnt++;
600 }
601
602 ed->hwINFO = m32_swap (usb_pipedevice (pipe)
603 | usb_pipeendpoint (pipe) << 7
604 | (usb_pipeisoc (pipe)? 0x8000: 0)
605 | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
606 | usb_pipeslow (pipe) << 13
607 | usb_maxpacket (usb_dev, pipe) << 16);
608
609 return ed_ret;
610}
611
612/*-------------------------------------------------------------------------*
613 * TD handling functions
614 *-------------------------------------------------------------------------*/
615
616/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
617
618static void td_fill (ohci_t *ohci, unsigned int info,
619 void *data, int len,
620 struct usb_device *dev, int index, urb_priv_t *urb_priv)
621{
622 volatile td_t *td, *td_pt;
623#ifdef OHCI_FILL_TRACE
624 int i;
625#endif
626
627 if (index > urb_priv->length) {
628 err("index > length");
629 return;
630 }
631 /* use this td as the next dummy */
632 td_pt = urb_priv->td [index];
633 td_pt->hwNextTD = 0;
634
635 /* fill the old dummy TD */
636 td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
637
638 td->ed = urb_priv->ed;
639 td->next_dl_td = NULL;
640 td->index = index;
641 td->data = (__u32)data;
642#ifdef OHCI_FILL_TRACE
643 if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
644 for (i = 0; i < len; i++)
645 printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
646 printf("\n");
647 }
648#endif
649 if (!len)
650 data = 0;
651
652 td->hwINFO = m32_swap (info);
653 td->hwCBP = m32_swap (data);
654 if (data)
655 td->hwBE = m32_swap (data + len - 1);
656 else
657 td->hwBE = 0;
658 td->hwNextTD = m32_swap (td_pt);
659 td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
660
661 /* append to queue */
662 td->ed->hwTailP = td->hwNextTD;
663}
664
665/*-------------------------------------------------------------------------*/
666
667/* prepare all TDs of a transfer */
668
669static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
670 int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
671{
672 ohci_t *ohci = &gohci;
673 int data_len = transfer_len;
674 void *data;
675 int cnt = 0;
676 __u32 info = 0;
42d1f039 677 unsigned int toggle = 0;
149dded2
WD		 678
679 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
42d1f039
WD		 680 if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
681 toggle = TD_T_TOGGLE;
149dded2 682 } else {
42d1f039 683 toggle = TD_T_DATA0;
149dded2
WD		 684 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
685 }
686 urb->td_cnt = 0;
687 if (data_len)
688 data = buffer;
689 else
690 data = 0;
691
692 switch (usb_pipetype (pipe)) {
693 case PIPE_BULK:
694 info = usb_pipeout (pipe)?
695 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
696 while(data_len > 4096) {
697 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
698 data += 4096; data_len -= 4096; cnt++;
699 }
700 info = usb_pipeout (pipe)?
701 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
702 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
703 cnt++;
704
705 if (!ohci->sleeping)
706 writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
707 break;
708
709 case PIPE_CONTROL:
710 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
711 td_fill (ohci, info, setup, 8, dev, cnt++, urb);
712 if (data_len > 0) {
713 info = usb_pipeout (pipe)?
714 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
715 /* NOTE: mishandles transfers >8K, some >4K */
716 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
717 }
718 info = usb_pipeout (pipe)?
719 TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
720 td_fill (ohci, info, data, 0, dev, cnt++, urb);
721 if (!ohci->sleeping)
722 writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
723 break;
724 }
725 if (urb->length != cnt)
726 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
727}
728
729/*-------------------------------------------------------------------------*
730 * Done List handling functions
731 *-------------------------------------------------------------------------*/
732
733
734/* calculate the transfer length and update the urb */
735
736static void dl_transfer_length(td_t * td)
737{
738 __u32 tdINFO, tdBE, tdCBP;
42d1f039 739 urb_priv_t *lurb_priv = &urb_priv;
149dded2
WD		 740
741 tdINFO = m32_swap (td->hwINFO);
42d1f039
WD		 742 tdBE = m32_swap (td->hwBE);
743 tdCBP = m32_swap (td->hwCBP);
149dded2
WD		 744
745
746 if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
747 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
748 if (tdBE != 0) {
749 if (td->hwCBP == 0)
750 lurb_priv->actual_length += tdBE - td->data + 1;
751 else
752 lurb_priv->actual_length += tdCBP - td->data;
753 }
754 }
755}
756
757/*-------------------------------------------------------------------------*/
758
759/* replies to the request have to be on a FIFO basis so
760 * we reverse the reversed done-list */
761
762static td_t * dl_reverse_done_list (ohci_t *ohci)
763{
764 __u32 td_list_hc;
765 td_t *td_rev = NULL;
766 td_t *td_list = NULL;
42d1f039 767 urb_priv_t *lurb_priv = NULL;
149dded2
WD		 768
769 td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
770 ohci->hcca->done_head = 0;
771
772 while (td_list_hc) {
773 td_list = (td_t *)td_list_hc;
774
775 if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
776 lurb_priv = &urb_priv;
777 dbg(" USB-error/status: %x : %p",
778 TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
779 if (td_list->ed->hwHeadP & m32_swap (0x1)) {
780 if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
781 td_list->ed->hwHeadP =
782 (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
783 (td_list->ed->hwHeadP & m32_swap (0x2));
784 lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
785 } else
786 td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
787 }
788 }
789
790 td_list->next_dl_td = td_rev;
791 td_rev = td_list;
792 td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
793 }
794 return td_list;
795}
796
797/*-------------------------------------------------------------------------*/
798
799/* td done list */
800static int dl_done_list (ohci_t *ohci, td_t *td_list)
801{
42d1f039 802 td_t *td_list_next = NULL;
149dded2
WD		 803 ed_t *ed;
804 int cc = 0;
805 int stat = 0;
806 /* urb_t *urb; */
807 urb_priv_t *lurb_priv;
42d1f039 808 __u32 tdINFO, edHeadP, edTailP;
149dded2 809
42d1f039
WD		 810 while (td_list) {
811 td_list_next = td_list->next_dl_td;
149dded2 812
42d1f039
WD		 813 lurb_priv = &urb_priv;
814 tdINFO = m32_swap (td_list->hwINFO);
149dded2 815
42d1f039 816 ed = td_list->ed;
149dded2 817
42d1f039 818 dl_transfer_length(td_list);
149dded2 819
42d1f039
WD		 820 /* error code of transfer */
821 cc = TD_CC_GET (tdINFO);
149dded2
WD		 822 if (cc != 0) {
823 dbg("ConditionCode %#x", cc);
824 stat = cc_to_error[cc];
825 }
826
42d1f039
WD		 827 if (ed->state != ED_NEW) {
828 edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
829 edTailP = m32_swap (ed->hwTailP);
149dded2
WD		 830
831 /* unlink eds if they are not busy */
42d1f039
WD		 832 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
833 ep_unlink (ohci, ed);
834 }
149dded2 835
42d1f039
WD		 836 td_list = td_list_next;
837 }
149dded2
WD		 838 return stat;
839}
840
841/*-------------------------------------------------------------------------*
842 * Virtual Root Hub
843 *-------------------------------------------------------------------------*/
844
845/* Device descriptor */
846static __u8 root_hub_dev_des[] =
847{
848 0x12, /* __u8 bLength; */
849 0x01, /* __u8 bDescriptorType; Device */
850 0x10, /* __u16 bcdUSB; v1.1 */
851 0x01,
852 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
853 0x00, /* __u8 bDeviceSubClass; */
854 0x00, /* __u8 bDeviceProtocol; */
855 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
856 0x00, /* __u16 idVendor; */
857 0x00,
858 0x00, /* __u16 idProduct; */
42d1f039 859 0x00,
149dded2 860 0x00, /* __u16 bcdDevice; */
42d1f039 861 0x00,
149dded2
WD		 862 0x00, /* __u8 iManufacturer; */
863 0x01, /* __u8 iProduct; */
864 0x00, /* __u8 iSerialNumber; */
865 0x01 /* __u8 bNumConfigurations; */
866};
867
868
869/* Configuration descriptor */
870static __u8 root_hub_config_des[] =
871{
872 0x09, /* __u8 bLength; */
873 0x02, /* __u8 bDescriptorType; Configuration */
874 0x19, /* __u16 wTotalLength; */
875 0x00,
876 0x01, /* __u8 bNumInterfaces; */
877 0x01, /* __u8 bConfigurationValue; */
878 0x00, /* __u8 iConfiguration; */
879 0x40, /* __u8 bmAttributes;
42d1f039 880 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
149dded2
WD		 881 0x00, /* __u8 MaxPower; */
882
883 /* interface */
884 0x09, /* __u8 if_bLength; */
885 0x04, /* __u8 if_bDescriptorType; Interface */
886 0x00, /* __u8 if_bInterfaceNumber; */
887 0x00, /* __u8 if_bAlternateSetting; */
888 0x01, /* __u8 if_bNumEndpoints; */
889 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
890 0x00, /* __u8 if_bInterfaceSubClass; */
891 0x00, /* __u8 if_bInterfaceProtocol; */
892 0x00, /* __u8 if_iInterface; */
893
894 /* endpoint */
895 0x07, /* __u8 ep_bLength; */
896 0x05, /* __u8 ep_bDescriptorType; Endpoint */
897 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
42d1f039
WD		 898 0x03, /* __u8 ep_bmAttributes; Interrupt */
899 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
900 0x00,
149dded2
WD		 901 0xff /* __u8 ep_bInterval; 255 ms */
902};
903
904static unsigned char root_hub_str_index0[] =
905{
906 0x04, /* __u8 bLength; */
907 0x03, /* __u8 bDescriptorType; String-descriptor */
908 0x09, /* __u8 lang ID */
909 0x04, /* __u8 lang ID */
910};
911
912static unsigned char root_hub_str_index1[] =
913{
914 28, /* __u8 bLength; */
915 0x03, /* __u8 bDescriptorType; String-descriptor */
916 'O', /* __u8 Unicode */
917 0, /* __u8 Unicode */
918 'H', /* __u8 Unicode */
919 0, /* __u8 Unicode */
920 'C', /* __u8 Unicode */
921 0, /* __u8 Unicode */
922 'I', /* __u8 Unicode */
923 0, /* __u8 Unicode */
924 ' ', /* __u8 Unicode */
925 0, /* __u8 Unicode */
926 'R', /* __u8 Unicode */
927 0, /* __u8 Unicode */
928 'o', /* __u8 Unicode */
929 0, /* __u8 Unicode */
930 'o', /* __u8 Unicode */
931 0, /* __u8 Unicode */
932 't', /* __u8 Unicode */
933 0, /* __u8 Unicode */
934 ' ', /* __u8 Unicode */
935 0, /* __u8 Unicode */
936 'H', /* __u8 Unicode */
937 0, /* __u8 Unicode */
938 'u', /* __u8 Unicode */
939 0, /* __u8 Unicode */
940 'b', /* __u8 Unicode */
941 0, /* __u8 Unicode */
942};
943
944/* Hub class-specific descriptor is constructed dynamically */
945
946
947/*-------------------------------------------------------------------------*/
948
949#define OK(x) len = (x); break
950#ifdef DEBUG
951#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
952#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
953#else
954#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
955#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
956#endif
957#define RD_RH_STAT roothub_status(&gohci)
958#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
959
960/* request to virtual root hub */
961
8a42eac7 962int rh_check_port_status(ohci_t *controller)
963{
964 __u32 temp, ndp, i;
965 int res;
966
967 res = -1;
968 temp = roothub_a (controller);
969 ndp = (temp & RH_A_NDP);
970 for (i = 0; i < ndp; i++) {
971 temp = roothub_portstatus (controller, i);
972 /* check for a device disconnect */
973 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
974 (RH_PS_PESC | RH_PS_CSC)) &&
975 ((temp & RH_PS_CCS) == 0)) {
976 res = i;
977 break;
978 }
979 }
980 return res;
981}
982
983static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
984 void *buffer, int transfer_len, struct devrequest *cmd)
149dded2
WD		 985{
986 void * data = buffer;
987 int leni = transfer_len;
988 int len = 0;
989 int stat = 0;
990 __u32 datab[4];
991 __u8 *data_buf = (__u8 *)datab;
42d1f039 992 __u16 bmRType_bReq;
149dded2
WD		 993 __u16 wValue;
994 __u16 wIndex;
995 __u16 wLength;
996
997#ifdef DEBUG
998urb_priv.actual_length = 0;
999pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
1000#else
1001 wait_ms(1);
1002#endif
1003 if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
1004 info("Root-Hub submit IRQ: NOT implemented");
1005 return 0;
1006 }
1007
1008 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
1009 wValue = m16_swap (cmd->value);
1010 wIndex = m16_swap (cmd->index);
1011 wLength = m16_swap (cmd->length);
1012
1013 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1014 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1015
1016 switch (bmRType_bReq) {
1017 /* Request Destination:
1018 without flags: Device,
1019 RH_INTERFACE: interface,
1020 RH_ENDPOINT: endpoint,
1021 RH_CLASS means HUB here,
1022 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
1023 */
1024
1025 case RH_GET_STATUS:
1026 *(__u16 *) data_buf = m16_swap (1); OK (2);
1027 case RH_GET_STATUS | RH_INTERFACE:
1028 *(__u16 *) data_buf = m16_swap (0); OK (2);
1029 case RH_GET_STATUS | RH_ENDPOINT:
1030 *(__u16 *) data_buf = m16_swap (0); OK (2);
1031 case RH_GET_STATUS | RH_CLASS:
1032 *(__u32 *) data_buf = m32_swap (
1033 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1034 OK (4);
1035 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
1036 *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
1037
1038 case RH_CLEAR_FEATURE | RH_ENDPOINT:
1039 switch (wValue) {
1040 case (RH_ENDPOINT_STALL): OK (0);
1041 }
1042 break;
1043
1044 case RH_CLEAR_FEATURE | RH_CLASS:
1045 switch (wValue) {
1046 case RH_C_HUB_LOCAL_POWER:
1047 OK(0);
1048 case (RH_C_HUB_OVER_CURRENT):
1049 WR_RH_STAT(RH_HS_OCIC); OK (0);
1050 }
1051 break;
1052
1053 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1054 switch (wValue) {
1055 case (RH_PORT_ENABLE):
1056 WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
1057 case (RH_PORT_SUSPEND):
1058 WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
1059 case (RH_PORT_POWER):
1060 WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
1061 case (RH_C_PORT_CONNECTION):
1062 WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
1063 case (RH_C_PORT_ENABLE):
1064 WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
1065 case (RH_C_PORT_SUSPEND):
1066 WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
1067 case (RH_C_PORT_OVER_CURRENT):
1068 WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
1069 case (RH_C_PORT_RESET):
1070 WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
1071 }
1072 break;
1073
1074 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1075 switch (wValue) {
1076 case (RH_PORT_SUSPEND):
1077 WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
1078 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1079 if (RD_RH_PORTSTAT & RH_PS_CCS)
1080 WR_RH_PORTSTAT (RH_PS_PRS);
1081 OK (0);
1082 case (RH_PORT_POWER):
1083 WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
1084 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1085 if (RD_RH_PORTSTAT & RH_PS_CCS)
1086 WR_RH_PORTSTAT (RH_PS_PES );
1087 OK (0);
1088 }
1089 break;
1090
1091 case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
1092
1093 case RH_GET_DESCRIPTOR:
1094 switch ((wValue & 0xff00) >> 8) {
1095 case (0x01): /* device descriptor */
1096 len = min_t(unsigned int,
1097 leni,
1098 min_t(unsigned int,
1099 sizeof (root_hub_dev_des),
1100 wLength));
1101 data_buf = root_hub_dev_des; OK(len);
1102 case (0x02): /* configuration descriptor */
1103 len = min_t(unsigned int,
1104 leni,
1105 min_t(unsigned int,
1106 sizeof (root_hub_config_des),
1107 wLength));
1108 data_buf = root_hub_config_des; OK(len);
1109 case (0x03): /* string descriptors */
1110 if(wValue==0x0300) {
1111 len = min_t(unsigned int,
1112 leni,
1113 min_t(unsigned int,
1114 sizeof (root_hub_str_index0),
1115 wLength));
1116 data_buf = root_hub_str_index0;
1117 OK(len);
1118 }
1119 if(wValue==0x0301) {
1120 len = min_t(unsigned int,
1121 leni,
1122 min_t(unsigned int,
1123 sizeof (root_hub_str_index1),
1124 wLength));
1125 data_buf = root_hub_str_index1;
1126 OK(len);
1127 }
1128 default:
1129 stat = USB_ST_STALLED;
1130 }
1131 break;
1132
1133 case RH_GET_DESCRIPTOR | RH_CLASS:
1134 {
1135 __u32 temp = roothub_a (&gohci);
1136
1137 data_buf [0] = 9; /* min length; */
1138 data_buf [1] = 0x29;
1139 data_buf [2] = temp & RH_A_NDP;
1140 data_buf [3] = 0;
1141 if (temp & RH_A_PSM) /* per-port power switching? */
1142 data_buf [3] |= 0x1;
1143 if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1144 data_buf [3] |= 0x10;
1145 else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
1146 data_buf [3] |= 0x8;
1147
1148 /* corresponds to data_buf[4-7] */
1149 datab [1] = 0;
1150 data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1151 temp = roothub_b (&gohci);
1152 data_buf [7] = temp & RH_B_DR;
1153 if (data_buf [2] < 7) {
1154 data_buf [8] = 0xff;
1155 } else {
1156 data_buf [0] += 2;
1157 data_buf [8] = (temp & RH_B_DR) >> 8;
1158 data_buf [10] = data_buf [9] = 0xff;
1159 }
1160
1161 len = min_t(unsigned int, leni,
1162 min_t(unsigned int, data_buf [0], wLength));
1163 OK (len);
1164 }
1165
1166 case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
1167
1168 case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
1169
1170 default:
1171 dbg ("unsupported root hub command");
1172 stat = USB_ST_STALLED;
1173 }
1174
1175#ifdef DEBUG
1176 ohci_dump_roothub (&gohci, 1);
1177#else
1178 wait_ms(1);
1179#endif
1180
1181 len = min_t(int, len, leni);
1182 if (data != data_buf)
1183 memcpy (data, data_buf, len);
42d1f039 1184 dev->act_len = len;
149dded2
WD		 1185 dev->status = stat;
1186
1187#ifdef DEBUG
1188 if (transfer_len)
1189 urb_priv.actual_length = transfer_len;
1190 pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1191#else
1192 wait_ms(1);
1193#endif
1194
1195 return stat;
1196}
1197
1198/*-------------------------------------------------------------------------*/
1199
1200/* common code for handling submit messages - used for all but root hub */
1201/* accesses. */
1202int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1203 int transfer_len, struct devrequest *setup, int interval)
1204{
1205 int stat = 0;
1206 int maxsize = usb_maxpacket(dev, pipe);
1207 int timeout;
1208
8a42eac7 1209 /* device pulled? Shortcut the action. */
1210 if (devgone == dev) {
1211 dev->status = USB_ST_CRC_ERR;
1212 return 0;
1213 }
1214
149dded2
WD		 1215#ifdef DEBUG
1216 urb_priv.actual_length = 0;
1217 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1218#else
1219 wait_ms(1);
1220#endif
1221 if (!maxsize) {
1222 err("submit_common_message: pipesize for pipe %lx is zero",
1223 pipe);
1224 return -1;
1225 }
1226
1227 if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
1228 err("sohci_submit_job failed");
1229 return -1;
1230 }
1231
1232 wait_ms(10);
1233 /* ohci_dump_status(&gohci); */
42d1f039 1234
a43278a4 1235 /* allow more time for a BULK device to react - some are slow */
b0639ca3 1236#define BULK_TO 5000 /* timeout in milliseconds */
a43278a4
WD		 1237 if (usb_pipetype (pipe) == PIPE_BULK)
1238 timeout = BULK_TO;
1239 else
1240 timeout = 100;
1241
149dded2 1242 /* wait for it to complete */
149dded2
WD		 1243 for (;;) {
1244 /* check whether the controller is done */
1245 stat = hc_interrupt();
1246 if (stat < 0) {
8a42eac7 1247 stat = USB_ST_CRC_ERR;
149dded2
WD		 1248 break;
1249 }
1250 if (stat >= 0 && stat != 0xff) {
1251 /* 0xff is returned for an SF-interrupt */
1252 break;
1253 }
1254 if (--timeout) {
1255 wait_ms(1);
1256 } else {
8a42eac7 1257 err("CTL:TIMEOUT ");
1258 stat = USB_ST_CRC_ERR;
149dded2
WD		 1259 break;
1260 }
1261 }
8a42eac7 1262 /* we got an Root Hub Status Change interrupt */
1263 if (got_rhsc) {
1264#ifdef DEBUG
1265 ohci_dump_roothub (&gohci, 1);
1266#endif
1267 got_rhsc = 0;
1268 /* abuse timeout */
1269 timeout = rh_check_port_status(&gohci);
1270 if (timeout >= 0) {
1271#if 0 /* this does nothing useful, but leave it here in case that changes */
1272 /* the called routine adds 1 to the passed value */
1273 usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
1274#endif
1275 /*
1276 * XXX
1277 * This is potentially dangerous because it assumes
1278 * that only one device is ever plugged in!
1279 */
1280 devgone = dev;
1281 }
1282 }
1283
149dded2 1284 dev->status = stat;
42d1f039 1285 dev->act_len = transfer_len;
149dded2
WD		 1286
1287#ifdef DEBUG
1288 pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
1289#else
1290 wait_ms(1);
1291#endif
1292
1293 /* free TDs in urb_priv */
1294 urb_free_priv (&urb_priv);
1295 return 0;
1296}
1297
1298/* submit routines called from usb.c */
1299int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1300 int transfer_len)
1301{
1302 info("submit_bulk_msg");
1303 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1304}
1305
1306int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1307 int transfer_len, struct devrequest *setup)
1308{
1309 int maxsize = usb_maxpacket(dev, pipe);
1310
1311 info("submit_control_msg");
1312#ifdef DEBUG
1313 urb_priv.actual_length = 0;
1314 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1315#else
1316 wait_ms(1);
1317#endif
1318 if (!maxsize) {
1319 err("submit_control_message: pipesize for pipe %lx is zero",
1320 pipe);
1321 return -1;
1322 }
8a42eac7 1323 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1324 gohci.rh.dev = dev;
149dded2
WD		 1325 /* root hub - redirect */
1326 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1327 setup);
8a42eac7 1328 }
149dded2
WD		 1329
1330 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1331}
1332
1333int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1334 int transfer_len, int interval)
1335{
1336 info("submit_int_msg");
1337 return -1;
1338}
1339
1340/*-------------------------------------------------------------------------*
1341 * HC functions
1342 *-------------------------------------------------------------------------*/
1343
1344/* reset the HC and BUS */
1345
1346static int hc_reset (ohci_t *ohci)
1347{
1348 int timeout = 30;
1349 int smm_timeout = 50; /* 0,5 sec */
1350
1351 if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1352 writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1353 info("USB HC TakeOver from SMM");
1354 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1355 wait_ms (10);
1356 if (--smm_timeout == 0) {
1357 err("USB HC TakeOver failed!");
1358 return -1;
1359 }
1360 }
1361 }
1362
1363 /* Disable HC interrupts */
1364 writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1365
1366 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
1367 ohci->slot_name,
1368 readl (&ohci->regs->control));
1369
42d1f039 1370 /* Reset USB (needed by some controllers) */
149dded2
WD		 1371 writel (0, &ohci->regs->control);
1372
1373 /* HC Reset requires max 10 us delay */
1374 writel (OHCI_HCR, &ohci->regs->cmdstatus);
1375 while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1376 if (--timeout == 0) {
1377 err("USB HC reset timed out!");
1378 return -1;
1379 }
1380 udelay (1);
1381 }
1382 return 0;
1383}
1384
1385/*-------------------------------------------------------------------------*/
1386
1387/* Start an OHCI controller, set the BUS operational
1388 * enable interrupts
1389 * connect the virtual root hub */
1390
1391static int hc_start (ohci_t * ohci)
1392{
42d1f039
WD		 1393 __u32 mask;
1394 unsigned int fminterval;
149dded2
WD		 1395
1396 ohci->disabled = 1;
1397
1398 /* Tell the controller where the control and bulk lists are
1399 * The lists are empty now. */
1400
1401 writel (0, &ohci->regs->ed_controlhead);
1402 writel (0, &ohci->regs->ed_bulkhead);
1403
1404 writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1405
42d1f039 1406 fminterval = 0x2edf;
149dded2
WD		 1407 writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1408 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1409 writel (fminterval, &ohci->regs->fminterval);
1410 writel (0x628, &ohci->regs->lsthresh);
1411
42d1f039
WD		 1412 /* start controller operations */
1413 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
149dded2 1414 ohci->disabled = 0;
42d1f039 1415 writel (ohci->hc_control, &ohci->regs->control);
149dded2 1416
8a42eac7 1417 /* disable all interrupts */
1418 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1419 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1420 OHCI_INTR_OC | OHCI_INTR_MIE);
1421 writel (mask, &ohci->regs->intrdisable);
1422 /* clear all interrupts */
1423 mask &= ~OHCI_INTR_MIE;
149dded2 1424 writel (mask, &ohci->regs->intrstatus);
8a42eac7 1425 /* Choose the interrupts we care about now - but w/o MIE */
1426 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1427 writel (mask, &ohci->regs->intrenable);
149dded2
WD		 1428
1429#ifdef OHCI_USE_NPS
1430 /* required for AMD-756 and some Mac platforms */
1431 writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
1432 &ohci->regs->roothub.a);
1433 writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1434#endif /* OHCI_USE_NPS */
1435
1436#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
1437 /* POTPGT delay is bits 24-31, in 2 ms units. */
1438 mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1439
1440 /* connect the virtual root hub */
1441 ohci->rh.devnum = 0;
1442
1443 return 0;
1444}
1445
1446/*-------------------------------------------------------------------------*/
1447
1448/* an interrupt happens */
1449
1450static int
1451hc_interrupt (void)
1452{
1453 ohci_t *ohci = &gohci;
1454 struct ohci_regs *regs = ohci->regs;
42d1f039 1455 int ints;
149dded2
WD		 1456 int stat = -1;
1457
1458 if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
1459 ints = OHCI_INTR_WDH;
1460 } else {
1461 ints = readl (&regs->intrstatus);
1462 }
1463
1464 /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1465
8a42eac7 1466 if (ints & OHCI_INTR_RHSC) {
1467 got_rhsc = 1;
1468 }
1469
149dded2
WD		 1470 if (ints & OHCI_INTR_UE) {
1471 ohci->disabled++;
1472 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1473 ohci->slot_name);
1474 /* e.g. due to PCI Master/Target Abort */
1475
1476#ifdef DEBUG
1477 ohci_dump (ohci, 1);
1478#else
1479 wait_ms(1);
1480#endif
1481 /* FIXME: be optimistic, hope that bug won't repeat often. */
1482 /* Make some non-interrupt context restart the controller. */
1483 /* Count and limit the retries though; either hardware or */
1484 /* software errors can go forever... */
1485 hc_reset (ohci);
1486 return -1;
1487 }
1488
1489 if (ints & OHCI_INTR_WDH) {
1490 wait_ms(1);
1491 writel (OHCI_INTR_WDH, &regs->intrdisable);
1492 stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1493 writel (OHCI_INTR_WDH, &regs->intrenable);
1494 }
1495
1496 if (ints & OHCI_INTR_SO) {
1497 dbg("USB Schedule overrun\n");
1498 writel (OHCI_INTR_SO, &regs->intrenable);
1499 stat = -1;
1500 }
1501
1502 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1503 if (ints & OHCI_INTR_SF) {
1504 unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
1505 wait_ms(1);
1506 writel (OHCI_INTR_SF, &regs->intrdisable);
1507 if (ohci->ed_rm_list[frame] != NULL)
1508 writel (OHCI_INTR_SF, &regs->intrenable);
1509 stat = 0xff;
1510 }
1511
1512 writel (ints, &regs->intrstatus);
1513 return stat;
1514}
1515
1516/*-------------------------------------------------------------------------*/
1517
1518/*-------------------------------------------------------------------------*/
1519
1520/* De-allocate all resources.. */
1521
1522static void hc_release_ohci (ohci_t *ohci)
1523{
1524 dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1525
1526 if (!ohci->disabled)
1527 hc_reset (ohci);
1528}
1529
1530/*-------------------------------------------------------------------------*/
1531
1532/*
1533 * low level initalisation routine, called from usb.c
1534 */
1535static char ohci_inited = 0;
1536
1537int usb_lowlevel_init(void)
1538{
1539 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
1540 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
1541
42d1f039
WD		 1542 /*
1543 * Set the 48 MHz UPLL clocking. Values are taken from
1544 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
1545 */
1546 clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
1547 gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
149dded2 1548
42d1f039
WD		 1549 /*
1550 * Enable USB host clock.
1551 */
1552 clk_power->CLKCON |= (1 << 4);
149dded2
WD		 1553
1554 memset (&gohci, 0, sizeof (ohci_t));
1555 memset (&urb_priv, 0, sizeof (urb_priv_t));
1556
1557 /* align the storage */
1558 if ((__u32)&ghcca[0] & 0xff) {
1559 err("HCCA not aligned!!");
1560 return -1;
1561 }
1562 phcca = &ghcca[0];
1563 info("aligned ghcca %p", phcca);
1564 memset(&ohci_dev, 0, sizeof(struct ohci_device));
1565 if ((__u32)&ohci_dev.ed[0] & 0x7) {
1566 err("EDs not aligned!!");
1567 return -1;
1568 }
1569 memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1570 if ((__u32)gtd & 0x7) {
1571 err("TDs not aligned!!");
1572 return -1;
1573 }
1574 ptd = gtd;
1575 gohci.hcca = phcca;
42d1f039 1576 memset (phcca, 0, sizeof (struct ohci_hcca));
149dded2
WD		 1577
1578 gohci.disabled = 1;
1579 gohci.sleeping = 0;
1580 gohci.irq = -1;
1581 gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE;
1582
1583 gohci.flags = 0;
1584 gohci.slot_name = "s3c2400";
1585
1586 if (hc_reset (&gohci) < 0) {
1587 hc_release_ohci (&gohci);
42d1f039
WD		 1588 /* Initialization failed */
1589 clk_power->CLKCON &= ~(1 << 4);
149dded2
WD		 1590 return -1;
1591 }
1592
1593 /* FIXME this is a second HC reset; why?? */
1594 writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
1595 wait_ms (10);
1596
1597 if (hc_start (&gohci) < 0) {
1598 err ("can't start usb-%s", gohci.slot_name);
1599 hc_release_ohci (&gohci);
42d1f039
WD		 1600 /* Initialization failed */
1601 clk_power->CLKCON &= ~(1 << 4);
149dded2
WD		 1602 return -1;
1603 }
1604
1605#ifdef DEBUG
1606 ohci_dump (&gohci, 1);
1607#else
1608 wait_ms(1);
1609#endif
1610 ohci_inited = 1;
1611 return 0;
1612}
1613
1614int usb_lowlevel_stop(void)
1615{
1616 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
1617
1618 /* this gets called really early - before the controller has */
1619 /* even been initialized! */
1620 if (!ohci_inited)
1621 return 0;
1622 /* TODO release any interrupts, etc. */
1623 /* call hc_release_ohci() here ? */
1624 hc_reset (&gohci);
1625 /* may not want to do this */
1626 clk_power->CLKCON &= ~(1 << 4);
1627 return 0;
1628}
1629
1630#endif /* CONFIG_USB_OHCI */
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