[people/ms/u-boot.git] / cpu / arm926ejs / at91 / spi.c

/*
 * Driver for ATMEL DataFlash support
 * Author : Hamid Ikdoumi (Atmel)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_spi.h>

#include <dataflash.h>

#define AT91_SPI_PCS0_DATAFLASH_CARD	0xE	/* Chip Select 0: NPCS0%1110 */
#define AT91_SPI_PCS1_DATAFLASH_CARD	0xD	/* Chip Select 0: NPCS0%1101 */
#define AT91_SPI_PCS3_DATAFLASH_CARD	0x7	/* Chip Select 3: NPCS3%0111 */

void AT91F_SpiInit(void)
{
	/* Reset the SPI */
	writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR);

	/* Configure SPI in Master Mode with No CS selected !!! */
	writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS,
	       AT91_BASE_SPI + AT91_SPI_MR);

	/* Configure CS0 */
	writel(AT91_SPI_NCPHA |
	       (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
	       (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
	       ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
	       AT91_BASE_SPI + AT91_SPI_CSR(0));

#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
	/* Configure CS1 */
	writel(AT91_SPI_NCPHA |
	       (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
	       (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
	       ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
	       AT91_BASE_SPI + AT91_SPI_CSR(1));
#endif

#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
	/* Configure CS3 */
	writel(AT91_SPI_NCPHA |
	       (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
	       (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
	       ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
	       AT91_BASE_SPI + AT91_SPI_CSR(3));
#endif

	/* SPI_Enable */
	writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);

	while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS));

	/*
	 * Add tempo to get SPI in a safe state.
	 * Should not be needed for new silicon (Rev B)
	 */
	udelay(500000);
	readl(AT91_BASE_SPI + AT91_SPI_SR);
	readl(AT91_BASE_SPI + AT91_SPI_RDR);

}

void AT91F_SpiEnable(int cs)
{
	unsigned long mode;

	switch (cs) {
	case 0:	/* Configure SPI CS0 for Serial DataFlash AT45DBxx */
		mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
		mode &= 0xFFF0FFFF;
		writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
		       AT91_BASE_SPI + AT91_SPI_MR);
		break;
	case 1:	/* Configure SPI CS1 for Serial DataFlash AT45DBxx */
		mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
		mode &= 0xFFF0FFFF;
		writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
		       AT91_BASE_SPI + AT91_SPI_MR);
		break;
	case 3:
		mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
		mode &= 0xFFF0FFFF;
		writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
		       AT91_BASE_SPI + AT91_SPI_MR);
		break;
	}

	/* SPI_Enable */
	writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
}

unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);

unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
{
	unsigned int timeout;

	pDesc->state = BUSY;

	writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);

	/* Initialize the Transmit and Receive Pointer */
	writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR);
	writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR);

	/* Intialize the Transmit and Receive Counters */
	writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR);
	writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR);

	if (pDesc->tx_data_size != 0) {
		/* Initialize the Next Transmit and Next Receive Pointer */
		writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR);
		writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR);

		/* Intialize the Next Transmit and Next Receive Counters */
		writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR);
		writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR);
	}

	/* arm simple, non interrupt dependent timer */
	reset_timer_masked();
	timeout = 0;

	writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR);
	while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
		((timeout = get_timer_masked()) < CONFIG_SYS_SPI_WRITE_TOUT));
	writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
	pDesc->state = IDLE;

	if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {
		printf("Error Timeout\n\r");
		return DATAFLASH_ERROR;
	}

	return DATAFLASH_OK;
}
Commit	Line	Data
fefb6c10 SP	1	/*
	2	* Driver for ATMEL DataFlash support
	3	* Author : Hamid Ikdoumi (Atmel)
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 of
	8	* the License, or (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	* MA 02111-1307 USA
	19	*
	20	*/
	21
fefb6c10	22	#include <common.h>
983c1db0 SP	23	#include <asm/arch/hardware.h>
	24	#include <asm/arch/gpio.h>
	25	#include <asm/arch/io.h>
	26	#include <asm/arch/at91_pio.h>
	27	#include <asm/arch/at91_spi.h>
fefb6c10	28
fefb6c10 SP	29	#include <dataflash.h>
fefb6c10 SP	30
983c1db0 SP	31	#define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
	32	#define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 0: NPCS0%1101 */
	33	#define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
fefb6c10 SP	34
	35	void AT91F_SpiInit(void)
	36	{
	37	/* Reset the SPI */
983c1db0	38	writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR);
fefb6c10 SP	39
fefb6c10 SP	40	/* Configure SPI in Master Mode with No CS selected !!! */
983c1db0 SP	41	writel(AT91_SPI_MSTR \| AT91_SPI_MODFDIS \| AT91_SPI_PCS,
983c1db0 SP	42	AT91_BASE_SPI + AT91_SPI_MR);
fefb6c10 SP	43
fefb6c10 SP	44	/* Configure CS0 */
983c1db0 SP	45	writel(AT91_SPI_NCPHA \|
	46	(AT91_SPI_DLYBS & DATAFLASH_TCSS) \|
	47	(AT91_SPI_DLYBCT & DATAFLASH_TCHS) \|
	48	((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
	49	AT91_BASE_SPI + AT91_SPI_CSR(0));
	50
6d0f6bcf	51	#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
983c1db0 SP	52	/* Configure CS1 */
	53	writel(AT91_SPI_NCPHA \|
	54	(AT91_SPI_DLYBS & DATAFLASH_TCSS) \|
	55	(AT91_SPI_DLYBCT & DATAFLASH_TCHS) \|
	56	((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
	57	AT91_BASE_SPI + AT91_SPI_CSR(1));
	58	#endif
	59
6d0f6bcf	60	#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
983c1db0 SP	61	/* Configure CS3 */
	62	writel(AT91_SPI_NCPHA \|
	63	(AT91_SPI_DLYBS & DATAFLASH_TCSS) \|
	64	(AT91_SPI_DLYBCT & DATAFLASH_TCHS) \|
	65	((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
	66	AT91_BASE_SPI + AT91_SPI_CSR(3));
	67	#endif
	68
	69	/* SPI_Enable */
	70	writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
	71
	72	while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS));
	73
	74	/*
	75	* Add tempo to get SPI in a safe state.
	76	* Should not be needed for new silicon (Rev B)
	77	*/
	78	udelay(500000);
	79	readl(AT91_BASE_SPI + AT91_SPI_SR);
	80	readl(AT91_BASE_SPI + AT91_SPI_RDR);
	81
fefb6c10 SP	82	}
	83
	84	void AT91F_SpiEnable(int cs)
	85	{
983c1db0	86	unsigned long mode;
1762f13b	87
fefb6c10 SP	88	switch (cs) {
fefb6c10 SP	89	case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
983c1db0 SP	90	mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
	91	mode &= 0xFFF0FFFF;
	92	writel(mode \| ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
	93	AT91_BASE_SPI + AT91_SPI_MR);
	94	break;
	95	case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */
	96	mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
	97	mode &= 0xFFF0FFFF;
	98	writel(mode \| ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
	99	AT91_BASE_SPI + AT91_SPI_MR);
fefb6c10 SP	100	break;
fefb6c10 SP	101	case 3:
983c1db0 SP	102	mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
	103	mode &= 0xFFF0FFFF;
	104	writel(mode \| ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
	105	AT91_BASE_SPI + AT91_SPI_MR);
fefb6c10 SP	106	break;
	107	}
	108
	109	/* SPI_Enable */
983c1db0	110	writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
fefb6c10 SP	111	}
fefb6c10 SP	112
983c1db0 SP	113	unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
983c1db0 SP	114
fefb6c10 SP	115	unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
	116	{
	117	unsigned int timeout;
	118
	119	pDesc->state = BUSY;
	120
983c1db0 SP	121	writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
983c1db0 SP	122
fefb6c10	123	/* Initialize the Transmit and Receive Pointer */
983c1db0 SP	124	writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR);
983c1db0 SP	125	writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR);
fefb6c10 SP	126
fefb6c10 SP	127	/* Intialize the Transmit and Receive Counters */
983c1db0 SP	128	writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR);
983c1db0 SP	129	writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR);
fefb6c10 SP	130
	131	if (pDesc->tx_data_size != 0) {
	132	/* Initialize the Next Transmit and Next Receive Pointer */
983c1db0 SP	133	writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR);
983c1db0 SP	134	writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR);
fefb6c10 SP	135
fefb6c10 SP	136	/* Intialize the Next Transmit and Next Receive Counters */
983c1db0 SP	137	writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR);
983c1db0 SP	138	writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR);
fefb6c10 SP	139	}
	140
	141	/* arm simple, non interrupt dependent timer */
	142	reset_timer_masked();
	143	timeout = 0;
	144
983c1db0 SP	145	writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR);
983c1db0 SP	146	while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
6d0f6bcf	147	((timeout = get_timer_masked()) < CONFIG_SYS_SPI_WRITE_TOUT));
983c1db0	148	writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
fefb6c10 SP	149	pDesc->state = IDLE;
fefb6c10 SP	150
6d0f6bcf	151	if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {
fefb6c10 SP	152	printf("Error Timeout\n\r");
	153	return DATAFLASH_ERROR;
	154	}
	155
	156	return DATAFLASH_OK;
	157	}