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1 | /* |
2 | * (C) Copyright 2008 Texas Insturments | |
3 | * | |
4 | * (C) Copyright 2002 | |
5 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
6 | * Marius Groeger <mgroeger@sysgo.de> | |
7 | * | |
8 | * (C) Copyright 2002 | |
9 | * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> | |
10 | * | |
11 | * See file CREDITS for list of people who contributed to this | |
12 | * project. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | * MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | /* | |
31 | * CPU specific code | |
32 | */ | |
33 | ||
34 | #include <common.h> | |
35 | #include <command.h> | |
36 | #include <asm/arch/sys_proto.h> | |
37 | ||
38 | #ifdef CONFIG_USE_IRQ | |
39 | DECLARE_GLOBAL_DATA_PTR; | |
40 | #endif | |
41 | ||
42 | #ifndef CONFIG_L2_OFF | |
43 | void l2cache_disable(void); | |
44 | #endif | |
45 | ||
46 | static void cache_flush(void); | |
47 | ||
48 | /* read co-processor 15, register #1 (control register) */ | |
49 | static unsigned long read_p15_c1(void) | |
50 | { | |
51 | unsigned long value; | |
52 | ||
53 | __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0\ | |
54 | @ read control reg\n":"=r"(value) | |
55 | ::"memory"); | |
56 | return value; | |
57 | } | |
58 | ||
59 | /* write to co-processor 15, register #1 (control register) */ | |
60 | static void write_p15_c1(unsigned long value) | |
61 | { | |
62 | __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0\ | |
63 | @ write it back\n"::"r"(value) | |
64 | : "memory"); | |
65 | ||
66 | read_p15_c1(); | |
67 | } | |
68 | ||
69 | static void cp_delay(void) | |
70 | { | |
71 | /* Many OMAP regs need at least 2 nops */ | |
72 | asm("nop"); | |
73 | asm("nop"); | |
74 | } | |
75 | ||
76 | /* See also ARM Ref. Man. */ | |
77 | #define C1_MMU (1<<0) /* mmu off/on */ | |
78 | #define C1_ALIGN (1<<1) /* alignment faults off/on */ | |
79 | #define C1_DC (1<<2) /* dcache off/on */ | |
80 | #define C1_WB (1<<3) /* merging write buffer on/off */ | |
81 | #define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ | |
82 | #define C1_SYS_PROT (1<<8) /* system protection */ | |
83 | #define C1_ROM_PROT (1<<9) /* ROM protection */ | |
84 | #define C1_IC (1<<12) /* icache off/on */ | |
85 | #define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ | |
86 | #define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ | |
87 | ||
88 | int cpu_init(void) | |
89 | { | |
90 | /* | |
91 | * setup up stacks if necessary | |
92 | */ | |
93 | #ifdef CONFIG_USE_IRQ | |
94 | IRQ_STACK_START = | |
95 | _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; | |
96 | FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; | |
97 | #endif | |
98 | return 0; | |
99 | } | |
100 | ||
101 | int cleanup_before_linux(void) | |
102 | { | |
103 | unsigned int i; | |
104 | ||
105 | /* | |
106 | * this function is called just before we call linux | |
107 | * it prepares the processor for linux | |
108 | * | |
109 | * we turn off caches etc ... | |
110 | */ | |
111 | disable_interrupts(); | |
112 | ||
113 | /* turn off I/D-cache */ | |
114 | icache_disable(); | |
115 | dcache_disable(); | |
116 | ||
117 | /* invalidate I-cache */ | |
118 | cache_flush(); | |
119 | ||
120 | #ifndef CONFIG_L2_OFF | |
121 | /* turn off L2 cache */ | |
122 | l2cache_disable(); | |
123 | /* invalidate L2 cache also */ | |
124 | v7_flush_dcache_all(get_device_type()); | |
125 | #endif | |
126 | i = 0; | |
127 | /* mem barrier to sync up things */ | |
128 | asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); | |
129 | ||
130 | #ifndef CONFIG_L2_OFF | |
131 | l2cache_enable(); | |
132 | #endif | |
133 | ||
134 | return 0; | |
135 | } | |
136 | ||
137 | int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
138 | { | |
139 | disable_interrupts(); | |
140 | reset_cpu(0); | |
141 | ||
142 | /* NOTREACHED */ | |
143 | return 0; | |
144 | } | |
145 | ||
146 | void icache_enable(void) | |
147 | { | |
148 | ulong reg; | |
149 | ||
150 | reg = read_p15_c1(); /* get control reg. */ | |
151 | cp_delay(); | |
152 | write_p15_c1(reg | C1_IC); | |
153 | } | |
154 | ||
155 | void icache_disable(void) | |
156 | { | |
157 | ulong reg; | |
158 | ||
159 | reg = read_p15_c1(); | |
160 | cp_delay(); | |
161 | write_p15_c1(reg & ~C1_IC); | |
162 | } | |
163 | ||
164 | void dcache_disable (void) | |
165 | { | |
166 | ulong reg; | |
167 | ||
168 | reg = read_p15_c1 (); | |
169 | cp_delay (); | |
170 | write_p15_c1 (reg & ~C1_DC); | |
171 | } | |
172 | ||
173 | void l2cache_enable() | |
174 | { | |
175 | unsigned long i; | |
176 | volatile unsigned int j; | |
177 | ||
178 | /* ES2 onwards we can disable/enable L2 ourselves */ | |
179 | if (get_cpu_rev() == CPU_3430_ES2) { | |
180 | __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); | |
181 | __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); | |
182 | __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); | |
183 | } else { | |
184 | /* Save r0, r12 and restore them after usage */ | |
185 | __asm__ __volatile__("mov %0, r12":"=r"(j)); | |
186 | __asm__ __volatile__("mov %0, r0":"=r"(i)); | |
187 | ||
188 | /* | |
189 | * GP Device ROM code API usage here | |
190 | * r12 = AUXCR Write function and r0 value | |
191 | */ | |
192 | __asm__ __volatile__("mov r12, #0x3"); | |
193 | __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); | |
194 | __asm__ __volatile__("orr r0, r0, #0x2"); | |
195 | /* SMI instruction to call ROM Code API */ | |
196 | __asm__ __volatile__(".word 0xE1600070"); | |
197 | __asm__ __volatile__("mov r0, %0":"=r"(i)); | |
198 | __asm__ __volatile__("mov r12, %0":"=r"(j)); | |
199 | } | |
200 | ||
201 | } | |
202 | ||
203 | void l2cache_disable() | |
204 | { | |
205 | unsigned long i; | |
206 | volatile unsigned int j; | |
207 | ||
208 | /* ES2 onwards we can disable/enable L2 ourselves */ | |
209 | if (get_cpu_rev() == CPU_3430_ES2) { | |
210 | __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); | |
211 | __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); | |
212 | __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); | |
213 | } else { | |
214 | /* Save r0, r12 and restore them after usage */ | |
215 | __asm__ __volatile__("mov %0, r12":"=r"(j)); | |
216 | __asm__ __volatile__("mov %0, r0":"=r"(i)); | |
217 | ||
218 | /* | |
219 | * GP Device ROM code API usage here | |
220 | * r12 = AUXCR Write function and r0 value | |
221 | */ | |
222 | __asm__ __volatile__("mov r12, #0x3"); | |
223 | __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); | |
224 | __asm__ __volatile__("bic r0, r0, #0x2"); | |
225 | /* SMI instruction to call ROM Code API */ | |
226 | __asm__ __volatile__(".word 0xE1600070"); | |
227 | __asm__ __volatile__("mov r0, %0":"=r"(i)); | |
228 | __asm__ __volatile__("mov r12, %0":"=r"(j)); | |
229 | } | |
230 | } | |
231 | ||
232 | int icache_status(void) | |
233 | { | |
234 | return (read_p15_c1() & C1_IC) != 0; | |
235 | } | |
236 | ||
237 | static void cache_flush(void) | |
238 | { | |
239 | asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); | |
240 | } |