[people/ms/u-boot.git] / cpu / arm_cortexa8 / start.S

/*
 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
 *
 * Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
 *
 * Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
 * Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
 * Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
 * Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
 * Copyright (c) 2003	Kshitij <kshitij@ti.com>
 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>

.globl _start
_start: b	reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

_undefined_instruction: .word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq
_pad:			.word 0x12345678 /* now 16*4=64 */
.global _end_vect
_end_vect:

	.balignl 16,0xdeadbeef
/*************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * setup Memory and board specific bits prior to relocation.
 * relocate armboot to ram
 * setup stack
 *
 *************************************************************************/

_TEXT_BASE:
	.word	TEXT_BASE

.globl _armboot_start
_armboot_start:
	.word _start

/*
 * These are defined in the board-specific linker script.
 */
.globl _bss_start
_bss_start:
	.word __bss_start

.globl _bss_end
_bss_end:
	.word _end

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0, cpsr
	bic	r0, r0, #0x1f
	orr	r0, r0, #0xd3
	msr	cpsr,r0

#if (CONFIG_OMAP34XX)
	/* Copy vectors to mask ROM indirect addr */
	adr	r0, _start		@ r0 <- current position of code
	add	r0, r0, #4		@ skip reset vector
	mov	r2, #64			@ r2 <- size to copy
	add	r2, r0, r2		@ r2 <- source end address
	mov	r1, #SRAM_OFFSET0	@ build vect addr
	mov	r3, #SRAM_OFFSET1
	add	r1, r1, r3
	mov	r3, #SRAM_OFFSET2
	add	r1, r1, r3
next:
	ldmia	r0!, {r3 - r10}		@ copy from source address [r0]
	stmia	r1!, {r3 - r10}		@ copy to   target address [r1]
	cmp	r0, r2			@ until source end address [r2]
	bne	next			@ loop until equal */
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
	/* No need to copy/exec the clock code - DPLL adjust already done
	 * in NAND/oneNAND Boot.
	 */
	bl	cpy_clk_code		@ put dpll adjust code behind vectors
#endif /* NAND Boot */
#endif
	/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
#endif

#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate:				@ relocate U-Boot to RAM
	adr	r0, _start		@ r0 <- current position of code
	ldr	r1, _TEXT_BASE		@ test if we run from flash or RAM
	cmp	r0, r1			@ don't reloc during debug
	beq	stack_setup

	ldr	r2, _armboot_start
	ldr	r3, _bss_start
	sub	r2, r3, r2		@ r2 <- size of armboot
	add	r2, r0, r2		@ r2 <- source end address

copy_loop:				@ copy 32 bytes at a time
	ldmia	r0!, {r3 - r10}		@ copy from source address [r0]
	stmia	r1!, {r3 - r10}		@ copy to   target address [r1]
	cmp	r0, r2			@ until source end addreee [r2]
	ble	copy_loop
#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */

	/* Set up the stack */
stack_setup:
	ldr	r0, _TEXT_BASE		@ upper 128 KiB: relocated uboot
	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo
#ifdef CONFIG_USE_IRQ
	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
#endif
	sub	sp, r0, #12		@ leave 3 words for abort-stack
	and	sp, sp, #~7		@ 8 byte alinged for (ldr/str)d

	/* Clear BSS (if any). Is below tx (watch load addr - need space) */
clear_bss:
	ldr	r0, _bss_start		@ find start of bss segment
	ldr	r1, _bss_end		@ stop here
	mov	r2, #0x00000000		@ clear value
clbss_l:
	str	r2, [r0]		@ clear BSS location
	cmp	r0, r1			@ are we at the end yet
	add	r0, r0, #4		@ increment clear index pointer
	bne	clbss_l			@ keep clearing till at end

	ldr	pc, _start_armboot	@ jump to C code

_start_armboot: .word start_armboot


/*************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************/
cpu_init_crit:
	/*
	 * Invalidate L1 I/D
	 */
	mov	r0, #0			@ set up for MCR
	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
	orr	r0, r0, #0x00000800	@ set bit 12 (Z---) BTB
	mcr	p15, 0, r0, c1, c0, 0

	/*
	 * Jump to board specific initialization...
	 * The Mask ROM will have already initialized
	 * basic memory. Go here to bump up clock rate and handle
	 * wake up conditions.
	 */
	mov	ip, lr			@ persevere link reg across call
	bl	lowlevel_init		@ go setup pll,mux,memory
	mov	lr, ip			@ restore link
	mov	pc, lr			@ back to my caller
/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13
#define I_BIT	 0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current
						@ user stack
	stmia	sp, {r0 - r12}			@ Save user registers (now in
						@ svc mode) r0-r12

	ldr	r2, _armboot_start
	sub	r2, r2, #(CONFIG_SYS_MALLOC_LEN)
	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE + 8)	@ set base 2 words into abort
						@ stack
	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc
						@ and cpsr (into parm regs)
	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
	mov	r0, sp				@ save current stack into r0
						@ (param register)
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add	r8, sp, #S_PC			@ !! R8 NEEDS to be saved !!
						@ a reserved stack spot would
						@ be good.
	stmdb	r8, {sp, lr}^			@ Calling SP, LR
	str	lr, [r8, #0]			@ Save calling PC
	mrs	r6, spsr
	str	r6, [r8, #4]			@ Save CPSR
	str	r0, [r8, #8]			@ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4			@ return & move spsr_svc into
						@ cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, _armboot_start		@ setup our mode stack (enter
						@ in banked mode)
	sub	r13, r13, #(CONFIG_SYS_MALLOC_LEN)	@ move past malloc pool
	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move to reserved a couple
						@ spots for abort stack

	str	lr, [r13]			@ save caller lr in position 0
						@ of saved stack
	mrs	lr, spsr			@ get the spsr
	str	lr, [r13, #4]			@ save spsr in position 1 of
						@ saved stack

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	@ msr	spsr_c, r13
	msr	spsr, r13			@ switch modes, make sure
						@ moves will execute
	mov	lr, pc				@ capture return pc
	movs	pc, lr				@ jump to next instruction &
						@ switch modes.
	.endm

	.macro get_bad_stack_swi
	sub	r13, r13, #4			@ space on current stack for
						@ scratch reg.
	str	r0, [r13]			@ save R0's value.
	ldr	r0, _armboot_start		@ get data regions start
	sub	r0, r0, #(CONFIG_SYS_MALLOC_LEN)	@ move past malloc pool
	sub	r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8)	@ move past gbl and a couple
						@ spots for abort stack
	str	lr, [r0]			@ save caller lr in position 0
						@ of saved stack
	mrs	r0, spsr			@ get the spsr
	str	lr, [r0, #4]			@ save spsr in position 1 of
						@ saved stack
	ldr	r0, [r13]			@ restore r0
	add	r13, r13, #4			@ pop stack entry
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm

/*
 * exception handlers
 */
	.align	5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack_swi
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effective fiq_save_user_regs */
	irq_save_user_regs
	bl	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif

/*
 *	v7_flush_dcache_all()
 *
 *	Flush the whole D-cache.
 *
 *	Corrupted registers: r0-r5, r7, r9-r11
 *
 *	- mm	- mm_struct describing address space
 */
	.align 5
.global v7_flush_dcache_all
v7_flush_dcache_all:
	stmfd	r13!, {r0 - r5, r7, r9 - r12, r14}

	mov	r7, r0				@ take a backup of device type
	cmp	r0, #0x3			@ check if the device type is
						@ GP
	moveq r12, #0x1				@ set up to invalide L2
smi:	.word 0x01600070			@ Call SMI monitor (smieq)
	cmp	r7, #0x3			@ compare again in case its
						@ lost
	beq	finished_inval			@ if GP device, inval done
						@ above

	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
	ands	r3, r0, #0x7000000		@ extract loc from clidr
	mov	r3, r3, lsr #23			@ left align loc bit field
	beq	finished_inval			@ if loc is 0, then no need to
						@ clean
	mov	r10, #0				@ start clean at cache level 0
inval_loop1:
	add	r2, r10, r10, lsr #1		@ work out 3x current cache
						@ level
	mov	r1, r0, lsr r2			@ extract cache type bits from
						@ clidr
	and	r1, r1, #7			@ mask of the bits for current
						@ cache only
	cmp	r1, #2				@ see what cache we have at
						@ this level
	blt	skip_inval			@ skip if no cache, or just
						@ i-cache
	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
						@ in cssr
	mov	r2, #0				@ operand for mcr SBZ
	mcr	p15, 0, r2, c7, c5, 4		@ flush prefetch buffer to
						@ sych the new cssr&csidr,
						@ with armv7 this is 'isb',
						@ but we compile with armv5
	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
	and	r2, r1, #7			@ extract the length of the
						@ cache lines
	add	r2, r2, #4			@ add 4 (line length offset)
	ldr	r4, =0x3ff
	ands	r4, r4, r1, lsr #3		@ find maximum number on the
						@ way size
	clz	r5, r4				@ find bit position of way
						@ size increment
	ldr	r7, =0x7fff
	ands	r7, r7, r1, lsr #13		@ extract max number of the
						@ index size
inval_loop2:
	mov	r9, r4				@ create working copy of max
						@ way size
inval_loop3:
	orr	r11, r10, r9, lsl r5		@ factor way and cache number
						@ into r11
	orr	r11, r11, r7, lsl r2		@ factor index number into r11
	mcr	p15, 0, r11, c7, c6, 2		@ invalidate by set/way
	subs	r9, r9, #1			@ decrement the way
	bge	inval_loop3
	subs	r7, r7, #1			@ decrement the index
	bge	inval_loop2
skip_inval:
	add	r10, r10, #2			@ increment cache number
	cmp	r3, r10
	bgt	inval_loop1
finished_inval:
	mov	r10, #0				@ swith back to cache level 0
	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
						@ in cssr
	mcr	p15, 0, r10, c7, c5, 4		@ flush prefetch buffer,
						@ with armv7 this is 'isb',
						@ but we compile with armv5

	ldmfd	r13!, {r0 - r5, r7, r9 - r12, pc}


	.align	5
.global reset_cpu
reset_cpu:
	ldr	r1, rstctl			@ get addr for global reset
						@ reg
	mov	r3, #0x2			@ full reset pll + mpu
	str	r3, [r1]			@ force reset
	mov	r0, r0
_loop_forever:
	b	_loop_forever
rstctl:
	.word	PRM_RSTCTRL
Commit	Line	Data
0b02b184 DB	1	/*
	2	* armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
	3	*
	4	* Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
	5	*
	6	* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
	7	* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
792a09eb	8	* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
0b02b184 DB	9	* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
	10	* Copyright (c) 2003 Kshitij <kshitij@ti.com>
	11	* Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
	12	*
	13	* See file CREDITS for list of people who contributed to this
	14	* project.
	15	*
	16	* This program is free software; you can redistribute it and/or
	17	* modify it under the terms of the GNU General Public License as
	18	* published by the Free Software Foundation; either version 2 of
	19	* the License, or (at your option) any later version.
	20	*
	21	* This program is distributed in the hope that it will be useful,
	22	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	24	* GNU General Public License for more details.
	25	*
	26	* You should have received a copy of the GNU General Public License
	27	* along with this program; if not, write to the Free Software
	28	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	29	* MA 02111-1307 USA
	30	*/
	31
	32	#include <config.h>
	33	#include <version.h>
	34
	35	.globl _start
	36	_start: b reset
	37	ldr pc, _undefined_instruction
	38	ldr pc, _software_interrupt
	39	ldr pc, _prefetch_abort
	40	ldr pc, _data_abort
	41	ldr pc, _not_used
	42	ldr pc, _irq
	43	ldr pc, _fiq
	44
	45	_undefined_instruction: .word undefined_instruction
	46	_software_interrupt: .word software_interrupt
	47	_prefetch_abort: .word prefetch_abort
	48	_data_abort: .word data_abort
	49	_not_used: .word not_used
	50	_irq: .word irq
	51	_fiq: .word fiq
	52	_pad: .word 0x12345678 /* now 164=64 /
	53	.global _end_vect
	54	_end_vect:
	55
	56	.balignl 16,0xdeadbeef
	57	/*************************************************************************
	58	*
	59	* Startup Code (reset vector)
	60	*
	61	* do important init only if we don't start from memory!
	62	* setup Memory and board specific bits prior to relocation.
	63	* relocate armboot to ram
	64	* setup stack
	65	*
	66	*************************************************************************/
	67
	68	_TEXT_BASE:
	69	.word TEXT_BASE
	70
	71	.globl _armboot_start
	72	_armboot_start:
73	.word _start
74
75	/*
76	* These are defined in the board-specific linker script.
77	*/
78	.globl _bss_start
79	_bss_start:
80	.word __bss_start
81
82	.globl _bss_end
83	_bss_end:
84	.word _end
85
86	#ifdef CONFIG_USE_IRQ
87	/* IRQ stack memory (calculated at run-time) */
88	.globl IRQ_STACK_START
89	IRQ_STACK_START:
90	.word 0x0badc0de
91
92	/* IRQ stack memory (calculated at run-time) */
93	.globl FIQ_STACK_START
94	FIQ_STACK_START:
95	.word 0x0badc0de
96	#endif
97
98	/*
99	* the actual reset code
100	*/
101
102	reset:
103	/*
104	* set the cpu to SVC32 mode
105	*/
106	mrs r0, cpsr
107	bic r0, r0, #0x1f
108	orr r0, r0, #0xd3
109	msr cpsr,r0
110
111	#if (CONFIG_OMAP34XX)
112	/* Copy vectors to mask ROM indirect addr */
113	adr r0, _start @ r0 <- current position of code
114	add r0, r0, #4 @ skip reset vector
115	mov r2, #64 @ r2 <- size to copy
116	add r2, r0, r2 @ r2 <- source end address
117	mov r1, #SRAM_OFFSET0 @ build vect addr
118	mov r3, #SRAM_OFFSET1
119	add r1, r1, r3
120	mov r3, #SRAM_OFFSET2
121	add r1, r1, r3
122	next:
123	ldmia r0!, {r3 - r10} @ copy from source address [r0]
124	stmia r1!, {r3 - r10} @ copy to target address [r1]
125	cmp r0, r2 @ until source end address [r2]
126	bne next @ loop until equal */
127	#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
128	/* No need to copy/exec the clock code - DPLL adjust already done
129	* in NAND/oneNAND Boot.
130	*/
131	bl cpy_clk_code @ put dpll adjust code behind vectors
132	#endif /* NAND Boot */
133	#endif
134	/* the mask ROM code should have PLL and others stable */
135	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
136	bl cpu_init_crit
137	#endif
138
139	#ifndef CONFIG_SKIP_RELOCATE_UBOOT
140	relocate: @ relocate U-Boot to RAM
141	adr r0, _start @ r0 <- current position of code
142	ldr r1, _TEXT_BASE @ test if we run from flash or RAM
143	cmp r0, r1 @ don't reloc during debug
144	beq stack_setup
145
146	ldr r2, _armboot_start
147	ldr r3, _bss_start
148	sub r2, r3, r2 @ r2 <- size of armboot
149	add r2, r0, r2 @ r2 <- source end address
150
151	copy_loop: @ copy 32 bytes at a time
152	ldmia r0!, {r3 - r10} @ copy from source address [r0]
153	stmia r1!, {r3 - r10} @ copy to target address [r1]
154	cmp r0, r2 @ until source end addreee [r2]
155	ble copy_loop
156	#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
157
158	/* Set up the stack */
159	stack_setup:
160	ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot
161	sub r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
162	sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo
163	#ifdef CONFIG_USE_IRQ
164	sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
165	#endif
166	sub sp, r0, #12 @ leave 3 words for abort-stack
167	and sp, sp, #~7 @ 8 byte alinged for (ldr/str)d
168
169	/* Clear BSS (if any). Is below tx (watch load addr - need space) */
170	clear_bss:
171	ldr r0, _bss_start @ find start of bss segment
172	ldr r1, _bss_end @ stop here
173	mov r2, #0x00000000 @ clear value
174	clbss_l:
175	str r2, [r0] @ clear BSS location
176	cmp r0, r1 @ are we at the end yet
177	add r0, r0, #4 @ increment clear index pointer
178	bne clbss_l @ keep clearing till at end
179
180	ldr pc, _start_armboot @ jump to C code
181
182	_start_armboot: .word start_armboot
183
184
185	/*************************************************************************
186	*
187	* CPU_init_critical registers
188	*
189	* setup important registers
190	* setup memory timing
191	*
192	*************************************************************************/
193	cpu_init_crit:
194	/*
195	* Invalidate L1 I/D
196	*/
197	mov r0, #0 @ set up for MCR
198	mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
199	mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
200
201	/*
202	* disable MMU stuff and caches
203	*/
204	mrc p15, 0, r0, c1, c0, 0
205	bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
206	bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
207	orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
208	orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB
209	mcr p15, 0, r0, c1, c0, 0
210
211	/*
212	* Jump to board specific initialization...
213	* The Mask ROM will have already initialized
214	* basic memory. Go here to bump up clock rate and handle
215	* wake up conditions.
216	*/
217	mov ip, lr @ persevere link reg across call
218	bl lowlevel_init @ go setup pll,mux,memory
219	mov lr, ip @ restore link
220	mov pc, lr @ back to my caller
221	/*
222	*************************************************************************
223	*
224	* Interrupt handling
225	*
226	*************************************************************************
227	*/
228	@
229	@ IRQ stack frame.
230	@
231	#define S_FRAME_SIZE 72
232
233	#define S_OLD_R0 68
234	#define S_PSR 64
235	#define S_PC 60
236	#define S_LR 56
237	#define S_SP 52
238
239	#define S_IP 48
240	#define S_FP 44
241	#define S_R10 40
242	#define S_R9 36
243	#define S_R8 32
244	#define S_R7 28
245	#define S_R6 24
246	#define S_R5 20
247	#define S_R4 16
248	#define S_R3 12
249	#define S_R2 8
250	#define S_R1 4
251	#define S_R0 0
252
253	#define MODE_SVC 0x13
254	#define I_BIT 0x80
255
256	/*
257	* use bad_save_user_regs for abort/prefetch/undef/swi ...
258	* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
259	*/
260
261	.macro bad_save_user_regs
262	sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
263	@ user stack
264	stmia sp, {r0 - r12} @ Save user registers (now in
265	@ svc mode) r0-r12
266
267	ldr r2, _armboot_start
268	sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
269	sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ set base 2 words into abort
270	@ stack
271	ldmia r2, {r2 - r3} @ get values for "aborted" pc
272	@ and cpsr (into parm regs)
273	add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
274
275	add r5, sp, #S_SP
276	mov r1, lr
277	stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
278	mov r0, sp @ save current stack into r0
279	@ (param register)
280	.endm
281
282	.macro irq_save_user_regs
283	sub sp, sp, #S_FRAME_SIZE
284	stmia sp, {r0 - r12} @ Calling r0-r12
285	add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
286	@ a reserved stack spot would
287	@ be good.
288	stmdb r8, {sp, lr}^ @ Calling SP, LR
289	str lr, [r8, #0] @ Save calling PC
290	mrs r6, spsr
291	str r6, [r8, #4] @ Save CPSR
292	str r0, [r8, #8] @ Save OLD_R0
293	mov r0, sp
294	.endm
295
296	.macro irq_restore_user_regs
297	ldmia sp, {r0 - lr}^ @ Calling r0 - lr
298	mov r0, r0
299	ldr lr, [sp, #S_PC] @ Get PC
300	add sp, sp, #S_FRAME_SIZE
301	subs pc, lr, #4 @ return & move spsr_svc into
302	@ cpsr
303	.endm
304
305	.macro get_bad_stack
306	ldr r13, _armboot_start @ setup our mode stack (enter
307	@ in banked mode)
308	sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
309	sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move to reserved a couple
310	@ spots for abort stack
311
312	str lr, [r13] @ save caller lr in position 0
313	@ of saved stack
314	mrs lr, spsr @ get the spsr
315	str lr, [r13, #4] @ save spsr in position 1 of
316	@ saved stack
317
318	mov r13, #MODE_SVC @ prepare SVC-Mode
319	@ msr spsr_c, r13
320	msr spsr, r13 @ switch modes, make sure
321	@ moves will execute
322	mov lr, pc @ capture return pc
323	movs pc, lr @ jump to next instruction &
324	@ switch modes.
325	.endm
326
327	.macro get_bad_stack_swi
328	sub r13, r13, #4 @ space on current stack for
329	@ scratch reg.
330	str r0, [r13] @ save R0's value.
331	ldr r0, _armboot_start @ get data regions start
332	sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
333	sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move past gbl and a couple
334	@ spots for abort stack
335	str lr, [r0] @ save caller lr in position 0
336	@ of saved stack
337	mrs r0, spsr @ get the spsr
338	str lr, [r0, #4] @ save spsr in position 1 of
339	@ saved stack
340	ldr r0, [r13] @ restore r0
341	add r13, r13, #4 @ pop stack entry
342	.endm
343
344	.macro get_irq_stack @ setup IRQ stack
345	ldr sp, IRQ_STACK_START
346	.endm
347
348	.macro get_fiq_stack @ setup FIQ stack
349	ldr sp, FIQ_STACK_START
350	.endm
351
352	/*
353	* exception handlers
354	*/
355	.align 5
356	undefined_instruction:
357	get_bad_stack
358	bad_save_user_regs
359	bl do_undefined_instruction
360
361	.align 5
362	software_interrupt:
363	get_bad_stack_swi
364	bad_save_user_regs
365	bl do_software_interrupt
366
367	.align 5
368	prefetch_abort:
369	get_bad_stack
370	bad_save_user_regs
371	bl do_prefetch_abort
372
373	.align 5
374	data_abort:
375	get_bad_stack
376	bad_save_user_regs
377	bl do_data_abort
378
379	.align 5
380	not_used:
381	get_bad_stack
382	bad_save_user_regs
383	bl do_not_used
384
385	#ifdef CONFIG_USE_IRQ
386
387	.align 5
388	irq:
389	get_irq_stack
390	irq_save_user_regs
391	bl do_irq
392	irq_restore_user_regs
393
394	.align 5
395	fiq:
396	get_fiq_stack
397	/* someone ought to write a more effective fiq_save_user_regs */
398	irq_save_user_regs
399	bl do_fiq
400	irq_restore_user_regs
401
402	#else
403
404	.align 5
405	irq:
406	get_bad_stack
407	bad_save_user_regs
408	bl do_irq
409
410	.align 5
411	fiq:
412	get_bad_stack
413	bad_save_user_regs
414	bl do_fiq
415
416	#endif
417
418	/*
419	* v7_flush_dcache_all()
420	*
421	* Flush the whole D-cache.
422	*
423	* Corrupted registers: r0-r5, r7, r9-r11
424	*
425	* - mm - mm_struct describing address space
426	*/
427	.align 5
428	.global v7_flush_dcache_all
429	v7_flush_dcache_all:
430	stmfd r13!, {r0 - r5, r7, r9 - r12, r14}
431
432	mov r7, r0 @ take a backup of device type
433	cmp r0, #0x3 @ check if the device type is
434	@ GP
435	moveq r12, #0x1 @ set up to invalide L2
436	smi: .word 0x01600070 @ Call SMI monitor (smieq)
437	cmp r7, #0x3 @ compare again in case its
438	@ lost
439	beq finished_inval @ if GP device, inval done
440	@ above
441
442	mrc p15, 1, r0, c0, c0, 1 @ read clidr
443	ands r3, r0, #0x7000000 @ extract loc from clidr
444	mov r3, r3, lsr #23 @ left align loc bit field
445	beq finished_inval @ if loc is 0, then no need to
446	@ clean
447	mov r10, #0 @ start clean at cache level 0
448	inval_loop1:
449	add r2, r10, r10, lsr #1 @ work out 3x current cache
450	@ level
451	mov r1, r0, lsr r2 @ extract cache type bits from
452	@ clidr
453	and r1, r1, #7 @ mask of the bits for current
454	@ cache only
455	cmp r1, #2 @ see what cache we have at
456	@ this level
457	blt skip_inval @ skip if no cache, or just
458	@ i-cache
459	mcr p15, 2, r10, c0, c0, 0 @ select current cache level
460	@ in cssr
461	mov r2, #0 @ operand for mcr SBZ
462	mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to
463	@ sych the new cssr&csidr,
464	@ with armv7 this is 'isb',
465	@ but we compile with armv5
466	mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
467	and r2, r1, #7 @ extract the length of the
468	@ cache lines
469	add r2, r2, #4 @ add 4 (line length offset)
470	ldr r4, =0x3ff
471	ands r4, r4, r1, lsr #3 @ find maximum number on the
472	@ way size
473	clz r5, r4 @ find bit position of way
474	@ size increment
475	ldr r7, =0x7fff
476	ands r7, r7, r1, lsr #13 @ extract max number of the
477	@ index size
478	inval_loop2:
479	mov r9, r4 @ create working copy of max
480	@ way size
481	inval_loop3:
482	orr r11, r10, r9, lsl r5 @ factor way and cache number
483	@ into r11
484	orr r11, r11, r7, lsl r2 @ factor index number into r11
485	mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
486	subs r9, r9, #1 @ decrement the way
487	bge inval_loop3
488	subs r7, r7, #1 @ decrement the index
489	bge inval_loop2
490	skip_inval:
491	add r10, r10, #2 @ increment cache number
492	cmp r3, r10
493	bgt inval_loop1
494	finished_inval:
495	mov r10, #0 @ swith back to cache level 0
496	mcr p15, 2, r10, c0, c0, 0 @ select current cache level
497	@ in cssr
498	mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer,
499	@ with armv7 this is 'isb',
500	@ but we compile with armv5
501
502	ldmfd r13!, {r0 - r5, r7, r9 - r12, pc}
503
504
505	.align 5
506	.global reset_cpu
507	reset_cpu:
508	ldr r1, rstctl @ get addr for global reset
509	@ reg
510	mov r3, #0x2 @ full reset pll + mpu
511	str r3, [r1] @ force reset
512	mov r0, r0
513	_loop_forever:
514	b _loop_forever
515	rstctl:
516	.word PRM_RSTCTRL