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6cb142fa | 1 | /* |
3f0606ad | 2 | * U-boot - start.S Startup file of u-boot for BF533/BF561 |
6cb142fa | 3 | * |
155fd766 | 4 | * Copyright (c) 2005-2007 Analog Devices Inc. |
6cb142fa WD |
5 | * |
6 | * This file is based on head.S | |
7 | * Copyright (c) 2003 Metrowerks/Motorola | |
8 | * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>, | |
9 | * Kenneth Albanowski <kjahds@kjahds.com>, | |
10 | * The Silver Hammer Group, Ltd. | |
11 | * (c) 1995, Dionne & Associates | |
12 | * (c) 1995, DKG Display Tech. | |
13 | * | |
14 | * See file CREDITS for list of people who contributed to this | |
15 | * project. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or | |
18 | * modify it under the terms of the GNU General Public License as | |
19 | * published by the Free Software Foundation; either version 2 of | |
20 | * the License, or (at your option) any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software | |
155fd766 AL |
29 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
30 | * MA 02110-1301 USA | |
6cb142fa WD |
31 | */ |
32 | ||
33 | /* | |
34 | * Note: A change in this file subsequently requires a change in | |
8db13d63 | 35 | * board/$(board_name)/config.mk for a valid u-boot.bin |
6cb142fa WD |
36 | */ |
37 | ||
38 | #define ASSEMBLY | |
39 | ||
40 | #include <linux/config.h> | |
6cb142fa | 41 | #include <config.h> |
3f0606ad AL |
42 | #include <asm/blackfin.h> |
43 | ||
44 | .global _stext; | |
45 | .global __bss_start; | |
46 | .global start; | |
47 | .global _start; | |
48 | .global _rambase; | |
49 | .global _ramstart; | |
50 | .global _ramend; | |
51 | .global _bf533_data_dest; | |
52 | .global _bf533_data_size; | |
53 | .global edata; | |
54 | .global _initialize; | |
55 | .global _exit; | |
56 | .global flashdataend; | |
57 | .global init_sdram; | |
6cb142fa WD |
58 | |
59 | #if (CONFIG_CCLK_DIV == 1) | |
60 | #define CONFIG_CCLK_ACT_DIV CCLK_DIV1 | |
61 | #endif | |
62 | #if (CONFIG_CCLK_DIV == 2) | |
63 | #define CONFIG_CCLK_ACT_DIV CCLK_DIV2 | |
64 | #endif | |
65 | #if (CONFIG_CCLK_DIV == 4) | |
66 | #define CONFIG_CCLK_ACT_DIV CCLK_DIV4 | |
67 | #endif | |
68 | #if (CONFIG_CCLK_DIV == 8) | |
69 | #define CONFIG_CCLK_ACT_DIV CCLK_DIV8 | |
70 | #endif | |
71 | #ifndef CONFIG_CCLK_ACT_DIV | |
72 | #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly | |
73 | #endif | |
74 | ||
6cb142fa WD |
75 | .text |
76 | _start: | |
77 | start: | |
78 | _stext: | |
79 | ||
3f0606ad | 80 | R0 = 0x32; |
6cb142fa WD |
81 | SYSCFG = R0; |
82 | SSYNC; | |
83 | ||
84 | /* As per HW reference manual DAG registers, | |
0d93de11 | 85 | * DATA and Address resgister shall be zero'd |
6cb142fa WD |
86 | * in initialization, after a reset state |
87 | */ | |
88 | r1 = 0; /* Data registers zero'd */ | |
89 | r2 = 0; | |
90 | r3 = 0; | |
91 | r4 = 0; | |
92 | r5 = 0; | |
93 | r6 = 0; | |
94 | r7 = 0; | |
95 | ||
96 | p0 = 0; /* Address registers zero'd */ | |
97 | p1 = 0; | |
98 | p2 = 0; | |
99 | p3 = 0; | |
100 | p4 = 0; | |
101 | p5 = 0; | |
0d93de11 | 102 | |
6cb142fa WD |
103 | i0 = 0; /* DAG Registers zero'd */ |
104 | i1 = 0; | |
105 | i2 = 0; | |
106 | i3 = 0; | |
107 | m0 = 0; | |
108 | m1 = 0; | |
109 | m3 = 0; | |
110 | m3 = 0; | |
111 | l0 = 0; | |
112 | l1 = 0; | |
113 | l2 = 0; | |
114 | l3 = 0; | |
115 | b0 = 0; | |
116 | b1 = 0; | |
117 | b2 = 0; | |
118 | b3 = 0; | |
119 | ||
120 | /* Set loop counters to zero, to make sure that | |
121 | * hw loops are disabled. | |
122 | */ | |
3f0606ad AL |
123 | r0 = 0; |
124 | lc0 = r0; | |
125 | lc1 = r0; | |
6cb142fa WD |
126 | |
127 | SSYNC; | |
128 | ||
129 | /* Check soft reset status */ | |
130 | p0.h = SWRST >> 16; | |
131 | p0.l = SWRST & 0xFFFF; | |
132 | r0.l = w[p0]; | |
133 | ||
134 | cc = bittst(r0, 15); | |
135 | if !cc jump no_soft_reset; | |
136 | ||
137 | /* Clear Soft reset */ | |
138 | r0 = 0x0000; | |
139 | w[p0] = r0; | |
140 | ssync; | |
141 | ||
142 | no_soft_reset: | |
143 | nop; | |
144 | ||
145 | /* Clear EVT registers */ | |
146 | p0.h = (EVT_EMULATION_ADDR >> 16); | |
147 | p0.l = (EVT_EMULATION_ADDR & 0xFFFF); | |
148 | p0 += 8; | |
149 | p1 = 14; | |
150 | r1 = 0; | |
151 | LSETUP(4,4) lc0 = p1; | |
152 | [ p0 ++ ] = r1; | |
0d93de11 | 153 | |
3f0606ad | 154 | p0.h = hi(SIC_IWR); |
8db13d63 AL |
155 | p0.l = lo(SIC_IWR); |
156 | r0.l = 0x1; | |
157 | w[p0] = r0.l; | |
158 | SSYNC; | |
6cb142fa | 159 | |
3f0606ad AL |
160 | sp.l = (0xffb01000 & 0xFFFF); |
161 | sp.h = (0xffb01000 >> 16); | |
6cb142fa | 162 | |
3f0606ad | 163 | call init_sdram; |
6cb142fa | 164 | |
3f0606ad AL |
165 | /* relocate into to RAM */ |
166 | call get_pc; | |
167 | offset: | |
168 | r2.l = offset; | |
169 | r2.h = offset; | |
170 | r3.l = start; | |
171 | r3.h = start; | |
172 | r1 = r2 - r3; | |
6cb142fa | 173 | |
3f0606ad AL |
174 | r0 = r0 - r1; |
175 | p1 = r0; | |
6cb142fa | 176 | |
6cb142fa WD |
177 | p2.l = (CFG_MONITOR_BASE & 0xffff); |
178 | p2.h = (CFG_MONITOR_BASE >> 16); | |
3f0606ad AL |
179 | |
180 | p3 = 0x04; | |
181 | p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff); | |
182 | p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16); | |
6cb142fa | 183 | loop1: |
3f0606ad AL |
184 | r1 = [p1 ++ p3]; |
185 | [p2 ++ p3] = r1; | |
186 | cc=p2==p4; | |
6cb142fa | 187 | if !cc jump loop1; |
6cb142fa WD |
188 | /* |
189 | * configure STACK | |
190 | */ | |
191 | r0.h = (CONFIG_STACKBASE >> 16); | |
192 | r0.l = (CONFIG_STACKBASE & 0xFFFF); | |
193 | sp = r0; | |
194 | fp = sp; | |
195 | ||
196 | /* | |
197 | * This next section keeps the processor in supervisor mode | |
198 | * during kernel boot. Switches to user mode at end of boot. | |
199 | * See page 3-9 of Hardware Reference manual for documentation. | |
200 | */ | |
201 | ||
202 | /* To keep ourselves in the supervisor mode */ | |
203 | p0.l = (EVT_IVG15_ADDR & 0xFFFF); | |
204 | p0.h = (EVT_IVG15_ADDR >> 16); | |
205 | ||
206 | p1.l = _real_start; | |
207 | p1.h = _real_start; | |
208 | [p0] = p1; | |
209 | ||
210 | p0.l = (IMASK & 0xFFFF); | |
211 | p0.h = (IMASK >> 16); | |
3f0606ad AL |
212 | r0.l = LO(IVG15_POS); |
213 | r0.h = HI(IVG15_POS); | |
6cb142fa WD |
214 | [p0] = r0; |
215 | raise 15; | |
216 | p0.l = WAIT_HERE; | |
217 | p0.h = WAIT_HERE; | |
218 | reti = p0; | |
219 | rti; | |
220 | ||
221 | WAIT_HERE: | |
222 | jump WAIT_HERE; | |
223 | ||
224 | .global _real_start; | |
225 | _real_start: | |
226 | [ -- sp ] = reti; | |
227 | ||
6cb142fa WD |
228 | /* DMA reset code to Hi of L1 SRAM */ |
229 | copy: | |
3f0606ad AL |
230 | /* P1 Points to the beginning of SYSTEM MMR Space */ |
231 | P1.H = hi(SYSMMR_BASE); | |
6cb142fa WD |
232 | P1.L = lo(SYSMMR_BASE); |
233 | ||
234 | R0.H = reset_start; /* Source Address (high) */ | |
235 | R0.L = reset_start; /* Source Address (low) */ | |
236 | R1.H = reset_end; | |
237 | R1.L = reset_end; | |
238 | R2 = R1 - R0; /* Count */ | |
239 | R1.H = hi(L1_ISRAM); /* Destination Address (high) */ | |
240 | R1.L = lo(L1_ISRAM); /* Destination Address (low) */ | |
241 | R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ | |
3f0606ad AL |
242 | /* Destination DMAConfig Value (8-bit words) */ |
243 | R4.L = (DI_EN | WNR | DMAEN); | |
6cb142fa WD |
244 | |
245 | DMA: | |
246 | R6 = 0x1 (Z); | |
247 | W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ | |
248 | W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ | |
249 | ||
250 | [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ | |
251 | W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */ | |
252 | /* Set Source DMAConfig = DMA Enable, | |
253 | Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */ | |
254 | W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3; | |
255 | ||
3f0606ad AL |
256 | /* Set Destination Base Address */ |
257 | [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; | |
6cb142fa WD |
258 | W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ |
259 | /* Set Destination DMAConfig = DMA Enable, | |
260 | Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ | |
261 | W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4; | |
0d93de11 AL |
262 | |
263 | WAIT_DMA_DONE: | |
3f0606ad AL |
264 | p0.h = hi(MDMA_D0_IRQ_STATUS); |
265 | p0.l = lo(MDMA_D0_IRQ_STATUS); | |
266 | R0 = W[P0](Z); | |
267 | CC = BITTST(R0, 0); | |
268 | if ! CC jump WAIT_DMA_DONE | |
6cb142fa WD |
269 | |
270 | R0 = 0x1; | |
6cb142fa | 271 | |
3f0606ad AL |
272 | /* Write 1 to clear DMA interrupt */ |
273 | W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; | |
6cb142fa WD |
274 | |
275 | /* Initialize BSS Section with 0 s */ | |
276 | p1.l = __bss_start; | |
277 | p1.h = __bss_start; | |
278 | p2.l = _end; | |
279 | p2.h = _end; | |
280 | r1 = p1; | |
281 | r2 = p2; | |
282 | r3 = r2 - r1; | |
283 | r3 = r3 >> 2; | |
284 | p3 = r3; | |
285 | lsetup (_clear_bss, _clear_bss_end ) lc1 = p3; | |
286 | CC = p2<=p1; | |
287 | if CC jump _clear_bss_skip; | |
288 | r0 = 0; | |
289 | _clear_bss: | |
290 | _clear_bss_end: | |
291 | [p1++] = r0; | |
292 | _clear_bss_skip: | |
293 | ||
294 | p0.l = _start1; | |
295 | p0.h = _start1; | |
296 | jump (p0); | |
297 | ||
298 | reset_start: | |
299 | p0.h = WDOG_CNT >> 16; | |
300 | p0.l = WDOG_CNT & 0xffff; | |
301 | r0 = 0x0010; | |
302 | w[p0] = r0; | |
303 | p0.h = WDOG_CTL >> 16; | |
304 | p0.l = WDOG_CTL & 0xffff; | |
305 | r0 = 0x0000; | |
306 | w[p0] = r0; | |
307 | reset_wait: | |
308 | jump reset_wait; | |
309 | ||
310 | reset_end: nop; | |
311 | ||
312 | _exit: | |
313 | jump.s _exit; | |
3f0606ad AL |
314 | get_pc: |
315 | r0 = rets; | |
316 | rts; |