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2d5b561e WD |
1 | /* vi: set ts=8 sw=8 noet: */ |
2 | /* | |
3 | * u-boot - Startup Code for XScale IXP | |
4 | * | |
5 | * Copyright (C) 2003 Kyle Harris <kharris@nexus-tech.net> | |
6 | * | |
7 | * Based on startup code example contained in the | |
8 | * Intel IXP4xx Programmer's Guide and past u-boot Start.S | |
9 | * samples. | |
10 | * | |
11 | * See file CREDITS for list of people who contributed to this | |
12 | * project. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of | |
17 | * the License, or (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | * MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | #include <config.h> | |
31 | #include <version.h> | |
32 | #include <asm/arch/ixp425.h> | |
33 | ||
42d1f039 WD |
34 | #define MMU_Control_M 0x001 /* Enable MMU */ |
35 | #define MMU_Control_A 0x002 /* Enable address alignment faults */ | |
36 | #define MMU_Control_C 0x004 /* Enable cache */ | |
37 | #define MMU_Control_W 0x008 /* Enable write-buffer */ | |
38 | #define MMU_Control_P 0x010 /* Compatability: 32 bit code */ | |
39 | #define MMU_Control_D 0x020 /* Compatability: 32 bit data */ | |
40 | #define MMU_Control_L 0x040 /* Compatability: */ | |
41 | #define MMU_Control_B 0x080 /* Enable Big-Endian */ | |
42 | #define MMU_Control_S 0x100 /* Enable system protection */ | |
43 | #define MMU_Control_R 0x200 /* Enable ROM protection */ | |
44 | #define MMU_Control_I 0x1000 /* Enable Instruction cache */ | |
45 | #define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */ | |
2d5b561e WD |
46 | #define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L) |
47 | ||
48 | ||
49 | /* | |
50 | * Macro definitions | |
51 | */ | |
42d1f039 WD |
52 | /* Delay a bit */ |
53 | .macro DELAY_FOR cycles, reg0 | |
54 | ldr \reg0, =\cycles | |
55 | subs \reg0, \reg0, #1 | |
56 | subne pc, pc, #0xc | |
57 | .endm | |
58 | ||
59 | /* wait for coprocessor write complete */ | |
60 | .macro CPWAIT reg | |
61 | mrc p15,0,\reg,c2,c0,0 | |
62 | mov \reg,\reg | |
63 | sub pc,pc,#4 | |
64 | .endm | |
2d5b561e WD |
65 | |
66 | .globl _start | |
67 | _start: b reset | |
68 | ldr pc, _undefined_instruction | |
69 | ldr pc, _software_interrupt | |
70 | ldr pc, _prefetch_abort | |
71 | ldr pc, _data_abort | |
72 | ldr pc, _not_used | |
73 | ldr pc, _irq | |
74 | ldr pc, _fiq | |
75 | ||
76 | _undefined_instruction: .word undefined_instruction | |
77 | _software_interrupt: .word software_interrupt | |
78 | _prefetch_abort: .word prefetch_abort | |
79 | _data_abort: .word data_abort | |
80 | _not_used: .word not_used | |
81 | _irq: .word irq | |
82 | _fiq: .word fiq | |
83 | ||
84 | .balignl 16,0xdeadbeef | |
85 | ||
86 | ||
87 | /* | |
88 | * Startup Code (reset vector) | |
89 | * | |
90 | * do important init only if we don't start from memory! | |
91 | * - relocate armboot to ram | |
92 | * - setup stack | |
93 | * - jump to second stage | |
94 | */ | |
95 | ||
96 | _TEXT_BASE: | |
97 | .word TEXT_BASE | |
98 | ||
99 | .globl _armboot_start | |
100 | _armboot_start: | |
101 | .word _start | |
102 | ||
103 | /* | |
f6e20fc6 | 104 | * These are defined in the board-specific linker script. |
2d5b561e WD |
105 | */ |
106 | .globl _bss_start | |
107 | _bss_start: | |
f6e20fc6 | 108 | .word __bss_start |
2d5b561e WD |
109 | |
110 | .globl _bss_end | |
111 | _bss_end: | |
f6e20fc6 | 112 | .word _end |
2d5b561e WD |
113 | |
114 | #ifdef CONFIG_USE_IRQ | |
115 | /* IRQ stack memory (calculated at run-time) */ | |
116 | .globl IRQ_STACK_START | |
117 | IRQ_STACK_START: | |
118 | .word 0x0badc0de | |
119 | ||
120 | /* IRQ stack memory (calculated at run-time) */ | |
121 | .globl FIQ_STACK_START | |
122 | FIQ_STACK_START: | |
123 | .word 0x0badc0de | |
124 | #endif | |
125 | ||
126 | /****************************************************************************/ | |
127 | /* */ | |
128 | /* the actual reset code */ | |
129 | /* */ | |
130 | /****************************************************************************/ | |
131 | ||
132 | reset: | |
133 | /* disable mmu, set big-endian */ | |
134 | mov r0, #0xf8 | |
135 | mcr p15, 0, r0, c1, c0, 0 | |
42d1f039 | 136 | CPWAIT r0 |
2d5b561e WD |
137 | |
138 | /* invalidate I & D caches & BTB */ | |
139 | mcr p15, 0, r0, c7, c7, 0 | |
140 | CPWAIT r0 | |
141 | ||
142 | /* invalidate I & Data TLB */ | |
53677ef1 | 143 | mcr p15, 0, r0, c8, c7, 0 |
42d1f039 | 144 | CPWAIT r0 |
2d5b561e WD |
145 | |
146 | /* drain write and fill buffers */ | |
147 | mcr p15, 0, r0, c7, c10, 4 | |
148 | CPWAIT r0 | |
149 | ||
150 | /* disable write buffer coalescing */ | |
151 | mrc p15, 0, r0, c1, c0, 1 | |
152 | orr r0, r0, #1 | |
153 | mcr p15, 0, r0, c1, c0, 1 | |
154 | CPWAIT r0 | |
155 | ||
156 | /* set EXP CS0 to the optimum timing */ | |
6d0f6bcf | 157 | ldr r1, =CONFIG_SYS_EXP_CS0 |
2d5b561e WD |
158 | ldr r2, =IXP425_EXP_CS0 |
159 | str r1, [r2] | |
160 | ||
42d1f039 | 161 | /* make sure flash is visible at 0 */ |
a1191902 | 162 | #if 0 |
53677ef1 | 163 | ldr r2, =IXP425_EXP_CFG0 |
2d5b561e WD |
164 | ldr r1, [r2] |
165 | orr r1, r1, #0x80000000 | |
166 | str r1, [r2] | |
a1191902 | 167 | #endif |
6d0f6bcf | 168 | mov r1, #CONFIG_SYS_SDR_CONFIG |
2d5b561e WD |
169 | ldr r2, =IXP425_SDR_CONFIG |
170 | str r1, [r2] | |
171 | ||
172 | /* disable refresh cycles */ | |
53677ef1 | 173 | mov r1, #0 |
2d5b561e WD |
174 | ldr r3, =IXP425_SDR_REFRESH |
175 | str r1, [r3] | |
176 | ||
177 | /* send nop command */ | |
53677ef1 | 178 | mov r1, #3 |
2d5b561e WD |
179 | ldr r4, =IXP425_SDR_IR |
180 | str r1, [r4] | |
42d1f039 | 181 | DELAY_FOR 0x4000, r0 |
2d5b561e WD |
182 | |
183 | /* set SDRAM internal refresh val */ | |
6d0f6bcf | 184 | ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT |
2d5b561e WD |
185 | str r1, [r3] |
186 | DELAY_FOR 0x4000, r0 | |
187 | ||
188 | /* send precharge-all command to close all open banks */ | |
189 | mov r1, #2 | |
190 | str r1, [r4] | |
191 | DELAY_FOR 0x4000, r0 | |
192 | ||
193 | /* provide 8 auto-refresh cycles */ | |
194 | mov r1, #4 | |
195 | mov r5, #8 | |
196 | 111: str r1, [r4] | |
197 | DELAY_FOR 0x100, r0 | |
198 | subs r5, r5, #1 | |
199 | bne 111b | |
200 | ||
201 | /* set mode register in sdram */ | |
6d0f6bcf | 202 | mov r1, #CONFIG_SYS_SDR_MODE_CONFIG |
2d5b561e WD |
203 | str r1, [r4] |
204 | DELAY_FOR 0x4000, r0 | |
205 | ||
206 | /* send normal operation command */ | |
207 | mov r1, #6 | |
208 | str r1, [r4] | |
209 | DELAY_FOR 0x4000, r0 | |
210 | ||
211 | /* copy */ | |
42d1f039 WD |
212 | mov r0, #0 |
213 | mov r4, r0 | |
6d0f6bcf | 214 | add r2, r0, #CONFIG_SYS_MONITOR_LEN |
2d5b561e | 215 | mov r1, #0x10000000 |
42d1f039 | 216 | mov r5, r1 |
2d5b561e WD |
217 | |
218 | 30: | |
42d1f039 WD |
219 | ldr r3, [r0], #4 |
220 | str r3, [r1], #4 | |
221 | cmp r0, r2 | |
222 | bne 30b | |
2d5b561e WD |
223 | |
224 | /* invalidate I & D caches & BTB */ | |
225 | mcr p15, 0, r0, c7, c7, 0 | |
226 | CPWAIT r0 | |
227 | ||
228 | /* invalidate I & Data TLB */ | |
53677ef1 | 229 | mcr p15, 0, r0, c8, c7, 0 |
42d1f039 | 230 | CPWAIT r0 |
2d5b561e WD |
231 | |
232 | /* drain write and fill buffers */ | |
233 | mcr p15, 0, r0, c7, c10, 4 | |
234 | CPWAIT r0 | |
235 | ||
42d1f039 | 236 | /* move flash to 0x50000000 */ |
53677ef1 | 237 | ldr r2, =IXP425_EXP_CFG0 |
2d5b561e WD |
238 | ldr r1, [r2] |
239 | bic r1, r1, #0x80000000 | |
240 | str r1, [r2] | |
241 | ||
242 | nop | |
243 | nop | |
244 | nop | |
245 | nop | |
246 | nop | |
247 | nop | |
248 | ||
249 | /* invalidate I & Data TLB */ | |
53677ef1 | 250 | mcr p15, 0, r0, c8, c7, 0 |
42d1f039 | 251 | CPWAIT r0 |
2d5b561e | 252 | |
42d1f039 WD |
253 | /* enable I cache */ |
254 | mrc p15, 0, r0, c1, c0, 0 | |
255 | orr r0, r0, #MMU_Control_I | |
256 | mcr p15, 0, r0, c1, c0, 0 | |
257 | CPWAIT r0 | |
2d5b561e WD |
258 | |
259 | mrs r0,cpsr /* set the cpu to SVC32 mode */ | |
260 | bic r0,r0,#0x1f /* (superviser mode, M=10011) */ | |
261 | orr r0,r0,#0x13 | |
262 | msr cpsr,r0 | |
263 | ||
8aa1a2d1 | 264 | #ifndef CONFIG_SKIP_RELOCATE_UBOOT |
2d5b561e WD |
265 | relocate: /* relocate U-Boot to RAM */ |
266 | adr r0, _start /* r0 <- current position of code */ | |
267 | ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ | |
268 | cmp r0, r1 /* don't reloc during debug */ | |
269 | beq stack_setup | |
270 | ||
271 | ldr r2, _armboot_start | |
f6e20fc6 | 272 | ldr r3, _bss_start |
2d5b561e WD |
273 | sub r2, r3, r2 /* r2 <- size of armboot */ |
274 | add r2, r0, r2 /* r2 <- source end address */ | |
275 | ||
276 | copy_loop: | |
277 | ldmia r0!, {r3-r10} /* copy from source address [r0] */ | |
278 | stmia r1!, {r3-r10} /* copy to target address [r1] */ | |
279 | cmp r0, r2 /* until source end addreee [r2] */ | |
280 | ble copy_loop | |
8aa1a2d1 | 281 | #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ |
2d5b561e WD |
282 | |
283 | /* Set up the stack */ | |
2d5b561e | 284 | stack_setup: |
f6e20fc6 | 285 | ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ |
6d0f6bcf JCPV |
286 | sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ |
287 | sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ | |
f6e20fc6 WD |
288 | #ifdef CONFIG_USE_IRQ |
289 | sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) | |
290 | #endif | |
2d5b561e WD |
291 | sub sp, r0, #12 /* leave 3 words for abort-stack */ |
292 | ||
293 | clear_bss: | |
2d5b561e | 294 | ldr r0, _bss_start /* find start of bss segment */ |
2d5b561e | 295 | ldr r1, _bss_end /* stop here */ |
53677ef1 | 296 | mov r2, #0x00000000 /* clear */ |
2d5b561e WD |
297 | |
298 | clbss_l:str r2, [r0] /* clear loop... */ | |
299 | add r0, r0, #4 | |
300 | cmp r0, r1 | |
a1191902 | 301 | ble clbss_l |
2d5b561e | 302 | |
2d5b561e WD |
303 | ldr pc, _start_armboot |
304 | ||
305 | _start_armboot: .word start_armboot | |
306 | ||
307 | ||
2d5b561e WD |
308 | /****************************************************************************/ |
309 | /* */ | |
310 | /* Interrupt handling */ | |
311 | /* */ | |
312 | /****************************************************************************/ | |
313 | ||
314 | /* IRQ stack frame */ | |
315 | ||
316 | #define S_FRAME_SIZE 72 | |
317 | ||
318 | #define S_OLD_R0 68 | |
319 | #define S_PSR 64 | |
320 | #define S_PC 60 | |
321 | #define S_LR 56 | |
322 | #define S_SP 52 | |
323 | ||
324 | #define S_IP 48 | |
325 | #define S_FP 44 | |
326 | #define S_R10 40 | |
327 | #define S_R9 36 | |
328 | #define S_R8 32 | |
329 | #define S_R7 28 | |
330 | #define S_R6 24 | |
331 | #define S_R5 20 | |
332 | #define S_R4 16 | |
333 | #define S_R3 12 | |
334 | #define S_R2 8 | |
335 | #define S_R1 4 | |
336 | #define S_R0 0 | |
337 | ||
338 | #define MODE_SVC 0x13 | |
339 | ||
340 | /* use bad_save_user_regs for abort/prefetch/undef/swi ... */ | |
341 | ||
342 | .macro bad_save_user_regs | |
343 | sub sp, sp, #S_FRAME_SIZE | |
344 | stmia sp, {r0 - r12} /* Calling r0-r12 */ | |
345 | add r8, sp, #S_PC | |
346 | ||
f6e20fc6 | 347 | ldr r2, _armboot_start |
6d0f6bcf JCPV |
348 | sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) |
349 | sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack | |
2d5b561e WD |
350 | ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ |
351 | add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ | |
352 | ||
353 | add r5, sp, #S_SP | |
354 | mov r1, lr | |
355 | stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ | |
356 | mov r0, sp | |
357 | .endm | |
358 | ||
359 | ||
360 | /* use irq_save_user_regs / irq_restore_user_regs for */ | |
361 | /* IRQ/FIQ handling */ | |
362 | ||
363 | .macro irq_save_user_regs | |
364 | sub sp, sp, #S_FRAME_SIZE | |
365 | stmia sp, {r0 - r12} /* Calling r0-r12 */ | |
366 | add r8, sp, #S_PC | |
367 | stmdb r8, {sp, lr}^ /* Calling SP, LR */ | |
368 | str lr, [r8, #0] /* Save calling PC */ | |
369 | mrs r6, spsr | |
370 | str r6, [r8, #4] /* Save CPSR */ | |
371 | str r0, [r8, #8] /* Save OLD_R0 */ | |
372 | mov r0, sp | |
373 | .endm | |
374 | ||
375 | .macro irq_restore_user_regs | |
376 | ldmia sp, {r0 - lr}^ @ Calling r0 - lr | |
377 | mov r0, r0 | |
378 | ldr lr, [sp, #S_PC] @ Get PC | |
379 | add sp, sp, #S_FRAME_SIZE | |
380 | subs pc, lr, #4 @ return & move spsr_svc into cpsr | |
381 | .endm | |
382 | ||
383 | .macro get_bad_stack | |
f6e20fc6 | 384 | ldr r13, _armboot_start @ setup our mode stack |
6d0f6bcf JCPV |
385 | sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) |
386 | sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack | |
2d5b561e WD |
387 | |
388 | str lr, [r13] @ save caller lr / spsr | |
389 | mrs lr, spsr | |
390 | str lr, [r13, #4] | |
391 | ||
392 | mov r13, #MODE_SVC @ prepare SVC-Mode | |
393 | msr spsr_c, r13 | |
394 | mov lr, pc | |
395 | movs pc, lr | |
396 | .endm | |
397 | ||
398 | .macro get_irq_stack @ setup IRQ stack | |
399 | ldr sp, IRQ_STACK_START | |
400 | .endm | |
401 | ||
402 | .macro get_fiq_stack @ setup FIQ stack | |
403 | ldr sp, FIQ_STACK_START | |
404 | .endm | |
405 | ||
406 | ||
407 | /****************************************************************************/ | |
408 | /* */ | |
409 | /* exception handlers */ | |
410 | /* */ | |
411 | /****************************************************************************/ | |
412 | ||
413 | .align 5 | |
414 | undefined_instruction: | |
415 | get_bad_stack | |
416 | bad_save_user_regs | |
417 | bl do_undefined_instruction | |
418 | ||
419 | .align 5 | |
420 | software_interrupt: | |
421 | get_bad_stack | |
422 | bad_save_user_regs | |
423 | bl do_software_interrupt | |
424 | ||
425 | .align 5 | |
426 | prefetch_abort: | |
427 | get_bad_stack | |
428 | bad_save_user_regs | |
429 | bl do_prefetch_abort | |
430 | ||
431 | .align 5 | |
432 | data_abort: | |
433 | get_bad_stack | |
434 | bad_save_user_regs | |
435 | bl do_data_abort | |
436 | ||
437 | .align 5 | |
438 | not_used: | |
439 | get_bad_stack | |
440 | bad_save_user_regs | |
441 | bl do_not_used | |
442 | ||
443 | #ifdef CONFIG_USE_IRQ | |
444 | ||
445 | .align 5 | |
446 | irq: | |
447 | get_irq_stack | |
448 | irq_save_user_regs | |
449 | bl do_irq | |
450 | irq_restore_user_regs | |
451 | ||
452 | .align 5 | |
453 | fiq: | |
454 | get_fiq_stack | |
455 | irq_save_user_regs /* someone ought to write a more */ | |
456 | bl do_fiq /* effiction fiq_save_user_regs */ | |
457 | irq_restore_user_regs | |
458 | ||
459 | #else | |
460 | ||
461 | .align 5 | |
462 | irq: | |
463 | get_bad_stack | |
464 | bad_save_user_regs | |
465 | bl do_irq | |
466 | ||
467 | .align 5 | |
468 | fiq: | |
469 | get_bad_stack | |
470 | bad_save_user_regs | |
471 | bl do_fiq | |
472 | ||
473 | #endif | |
474 | ||
475 | /****************************************************************************/ | |
476 | /* */ | |
477 | /* Reset function: Use Watchdog to reset */ | |
478 | /* */ | |
479 | /****************************************************************************/ | |
480 | ||
481 | .align 5 | |
482 | .globl reset_cpu | |
483 | ||
484 | reset_cpu: | |
53677ef1 | 485 | ldr r1, =0x482e |
2d5b561e WD |
486 | ldr r2, =IXP425_OSWK |
487 | str r1, [r2] | |
53677ef1 | 488 | ldr r1, =0x0fff |
2d5b561e WD |
489 | ldr r2, =IXP425_OSWT |
490 | str r1, [r2] | |
53677ef1 | 491 | ldr r1, =0x5 |
2d5b561e WD |
492 | ldr r2, =IXP425_OSWE |
493 | str r1, [r2] | |
494 | b reset_endless | |
495 | ||
496 | ||
497 | reset_endless: | |
498 | ||
499 | b reset_endless | |
ba94a1bb WD |
500 | |
501 | #ifdef CONFIG_USE_IRQ | |
502 | ||
503 | .LC0: .word loops_per_jiffy | |
504 | ||
505 | /* | |
506 | * 0 <= r0 <= 2000 | |
507 | */ | |
508 | .globl udelay | |
509 | udelay: | |
510 | mov r2, #0x6800 | |
511 | orr r2, r2, #0x00db | |
512 | mul r0, r2, r0 | |
513 | ldr r2, .LC0 | |
514 | ldr r2, [r2] @ max = 0x0fffffff | |
515 | mov r0, r0, lsr #11 @ max = 0x00003fff | |
516 | mov r2, r2, lsr #11 @ max = 0x0003ffff | |
517 | mul r0, r2, r0 @ max = 2^32-1 | |
518 | movs r0, r0, lsr #6 | |
519 | ||
520 | delay_loop: | |
521 | subs r0, r0, #1 | |
522 | bne delay_loop | |
523 | mov pc, lr | |
524 | ||
525 | #endif /* CONFIG_USE_IRQ */ |