[people/ms/u-boot.git] / cpu / mcf52x2 / cpu.c

/*
 * (C) Copyright 2003
 * Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * MCF5282 additionals
 * (C) Copyright 2005
 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
 *
 * MCF5275 additions
 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/immap.h>
#include <netdev.h>

#ifdef  CONFIG_M5271
/*
 * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
 * determine which one we are running on, based on the Chip Identification
 * Register (CIR).
 */
int checkcpu(void)
{
	char buf[32];
	unsigned short cir;	/* Chip Identification Register */
	unsigned short pin;	/* Part identification number */
	unsigned char prn;	/* Part revision number */
	char *cpu_model;

	cir = mbar_readShort(MCF_CCM_CIR);
	pin = cir >> MCF_CCM_CIR_PIN_LEN;
	prn = cir & MCF_CCM_CIR_PRN_MASK;

	switch (pin) {
	case MCF_CCM_CIR_PIN_MCF5270:
		cpu_model = "5270";
		break;
	case MCF_CCM_CIR_PIN_MCF5271:
		cpu_model = "5271";
		break;
	default:
		cpu_model = NULL;
		break;
	}

	if (cpu_model)
		printf("CPU:   Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
		       cpu_model, prn, strmhz(buf, CFG_CLK));
	else
		printf("CPU:   Unknown - Freescale ColdFire MCF5271 family"
		       " (PIN: 0x%x) rev. %hu, at %s MHz\n",
		       pin, prn, strmhz(buf, CFG_CLK));

	return 0;
}

int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
	mbar_writeByte(MCF_RCM_RCR,
		       MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
	return 0;
};

#if defined(CONFIG_WATCHDOG)
void watchdog_reset(void)
{
	mbar_writeShort(MCF_WTM_WSR, 0x5555);
	mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
}

int watchdog_disable(void)
{
	mbar_writeShort(MCF_WTM_WCR, 0);
	return (0);
}

int watchdog_init(void)
{
	mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
	return (0);
}
#endif				/* #ifdef CONFIG_WATCHDOG */

#endif

#ifdef	CONFIG_M5272
int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);

	wdp->wdog_wrrr = 0;
	udelay(1000);

	/* enable watchdog, set timeout to 0 and wait */
	wdp->wdog_wrrr = 1;
	while (1) ;

	/* we don't return! */
	return 0;
};

int checkcpu(void)
{
	volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
	uchar msk;
	char *suf;

	puts("CPU:   ");
	msk = (sysctrl->sc_dir > 28) & 0xf;
	switch (msk) {
	case 0x2:
		suf = "1K75N";
		break;
	case 0x4:
		suf = "3K75N";
		break;
	default:
		suf = NULL;
		printf("Freescale MCF5272 (Mask:%01x)\n", msk);
		break;
	}

	if (suf)
		printf("Freescale MCF5272 %s\n", suf);
	return 0;
};

#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
	wdt->wdog_wcr = 0;
}

int watchdog_disable(void)
{
	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);

	wdt->wdog_wcr = 0;	/* reset watchdog counter */
	wdt->wdog_wirr = 0;	/* disable watchdog interrupt */
	wdt->wdog_wrrr = 0;	/* disable watchdog timer */

	puts("WATCHDOG:disabled\n");
	return (0);
}

int watchdog_init(void)
{
	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);

	wdt->wdog_wirr = 0;	/* disable watchdog interrupt */

	/* set timeout and enable watchdog */
	wdt->wdog_wrrr =
	    ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
	wdt->wdog_wcr = 0;	/* reset watchdog counter */

	puts("WATCHDOG:enabled\n");
	return (0);
}
#endif				/* #ifdef CONFIG_WATCHDOG */

#endif				/* #ifdef CONFIG_M5272 */

#ifdef	CONFIG_M5275
int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
	volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);

	udelay(1000);

	rcm->rcr = RCM_RCR_SOFTRST;

	/* we don't return! */
	return 0;
};

int checkcpu(void)
{
	char buf[32];

	printf("CPU:   Freescale Coldfire MCF5275 at %s MHz\n",
			strmhz(buf, CFG_CLK));
	return 0;
};


#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
	wdt->wsr = 0x5555;
	wdt->wsr = 0xAAAA;
}

int watchdog_disable(void)
{
	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);

	wdt->wsr = 0x5555; /* reset watchdog counter */
	wdt->wsr = 0xAAAA;
	wdt->wcr = 0;	/* disable watchdog timer */

	puts("WATCHDOG:disabled\n");
	return (0);
}

int watchdog_init(void)
{
	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);

	wdt->wcr = 0;	/* disable watchdog */

	/* set timeout and enable watchdog */
	wdt->wmr =
		((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
	wdt->wsr = 0x5555; /* reset watchdog counter */
	wdt->wsr = 0xAAAA;

	puts("WATCHDOG:enabled\n");
	return (0);
}
#endif				/* #ifdef CONFIG_WATCHDOG */

#endif				/* #ifdef CONFIG_M5275 */

#ifdef	CONFIG_M5282
int checkcpu(void)
{
	unsigned char resetsource = MCFRESET_RSR;

	printf("CPU:   Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
	       MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
	printf("Reset:%s%s%s%s%s%s%s\n",
	       (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
	       (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
	       (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
	       (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
	       (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
	       (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
	       (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
	return 0;
}

int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
	MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
	return 0;
};
#endif

#ifdef CONFIG_M5249
int checkcpu(void)
{
	char buf[32];

	printf("CPU:   Freescale Coldfire MCF5249 at %s MHz\n",
	       strmhz(buf, CFG_CLK));
	return 0;
}

int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
	/* enable watchdog, set timeout to 0 and wait */
	mbar_writeByte(MCFSIM_SYPCR, 0xc0);
	while (1) ;

	/* we don't return! */
	return 0;
};
#endif

#ifdef CONFIG_M5253
int checkcpu(void)
{
	char buf[32];

	unsigned char resetsource = mbar_readLong(SIM_RSR);
	printf("CPU:   Freescale Coldfire MCF5253 at %s MHz\n",
	       strmhz(buf, CFG_CLK));

	if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
		printf("Reset:%s%s\n",
		       (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
		       : "",
		       (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
		       "");
	}
	return 0;
}

int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
{
	/* enable watchdog, set timeout to 0 and wait */
	mbar_writeByte(SIM_SYPCR, 0xc0);
	while (1) ;

	/* we don't return! */
	return 0;
};
#endif

#if defined(CONFIG_MCFFEC)
/* Default initializations for MCFFEC controllers.  To override,
 * create a board-specific function called:
 * 	int board_eth_init(bd_t *bis)
 */

int cpu_eth_init(bd_t *bis)
{
	return mcffec_initialize(bis);
}
#endif
Commit	Line	Data
bf9e3b38 WD	1	/*
	2	* (C) Copyright 2003
	3	* Josef Baumgartner <josef.baumgartner@telex.de>
	4	*
9acb626f HS	5	* MCF5282 additionals
	6	* (C) Copyright 2005
	7	* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
	8	*
f71d9d91 MF	9	* MCF5275 additions
	10	* Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
	11	*
bf9e3b38 WD	12	* See file CREDITS for list of people who contributed to this
	13	* project.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of
	18	* the License, or (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; if not, write to the Free Software
	27	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	28	* MA 02111-1307 USA
	29	*/
	30
	31	#include <common.h>
	32	#include <watchdog.h>
	33	#include <command.h>
83ec20bc	34	#include <asm/immap.h>
89973f8a	35	#include <netdev.h>
bf9e3b38	36
eacbd317	37	#ifdef CONFIG_M5271
363d1d8f BS	38	/*
	39	* Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
	40	* determine which one we are running on, based on the Chip Identification
	41	* Register (CIR).
	42	*/
83ec20bc	43	int checkcpu(void)
eacbd317	44	{
b75ef85f	45	char buf[32];
363d1d8f BS	46	unsigned short cir; /* Chip Identification Register */
	47	unsigned short pin; /* Part identification number */
	48	unsigned char prn; /* Part revision number */
	49	char *cpu_model;
	50
	51	cir = mbar_readShort(MCF_CCM_CIR);
	52	pin = cir >> MCF_CCM_CIR_PIN_LEN;
	53	prn = cir & MCF_CCM_CIR_PRN_MASK;
	54
	55	switch (pin) {
	56	case MCF_CCM_CIR_PIN_MCF5270:
	57	cpu_model = "5270";
	58	break;
	59	case MCF_CCM_CIR_PIN_MCF5271:
	60	cpu_model = "5271";
	61	break;
	62	default:
	63	cpu_model = NULL;
	64	break;
	65	}
	66
	67	if (cpu_model)
	68	printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
83ec20bc	69	cpu_model, prn, strmhz(buf, CFG_CLK));
363d1d8f BS	70	else
363d1d8f BS	71	printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
83ec20bc TL	72	" (PIN: 0x%x) rev. %hu, at %s MHz\n",
83ec20bc TL	73	pin, prn, strmhz(buf, CFG_CLK));
b75ef85f	74
eacbd317 ZL	75	return 0;
	76	}
	77
83ec20bc TL	78	int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
83ec20bc TL	79	{
eacbd317	80	mbar_writeByte(MCF_RCM_RCR,
83ec20bc	81	MCF_RCM_RCR_SOFTRST \| MCF_RCM_RCR_FRCRSTOUT);
eacbd317 ZL	82	return 0;
	83	};
	84
	85	#if defined(CONFIG_WATCHDOG)
83ec20bc	86	void watchdog_reset(void)
eacbd317 ZL	87	{
	88	mbar_writeShort(MCF_WTM_WSR, 0x5555);
	89	mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
	90	}
	91
83ec20bc	92	int watchdog_disable(void)
eacbd317 ZL	93	{
	94	mbar_writeShort(MCF_WTM_WCR, 0);
	95	return (0);
	96	}
	97
83ec20bc	98	int watchdog_init(void)
eacbd317	99	{
eacbd317 ZL	100	mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
	101	return (0);
	102	}
83ec20bc	103	#endif /* #ifdef CONFIG_WATCHDOG */
eacbd317 ZL	104
eacbd317 ZL	105	#endif
bf9e3b38 WD	106
bf9e3b38 WD	107	#ifdef CONFIG_M5272
83ec20bc TL	108	int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
	109	{
	110	volatile wdog_t wdp = (wdog_t ) (MMAP_WDOG);
bf9e3b38 WD	111
bf9e3b38 WD	112	wdp->wdog_wrrr = 0;
83ec20bc	113	udelay(1000);
bf9e3b38 WD	114
	115	/* enable watchdog, set timeout to 0 and wait */
	116	wdp->wdog_wrrr = 1;
83ec20bc	117	while (1) ;
bf9e3b38 WD	118
	119	/* we don't return! */
	120	return 0;
	121	};
	122
83ec20bc TL	123	int checkcpu(void)
	124	{
	125	volatile sysctrl_t sysctrl = (sysctrl_t ) (MMAP_CFG);
bf9e3b38	126	uchar msk;
83ec20bc	127	char *suf;
bf9e3b38	128
83ec20bc TL	129	puts("CPU: ");
83ec20bc TL	130	msk = (sysctrl->sc_dir > 28) & 0xf;
bf9e3b38	131	switch (msk) {
83ec20bc TL	132	case 0x2:
	133	suf = "1K75N";
	134	break;
	135	case 0x4:
	136	suf = "3K75N";
	137	break;
	138	default:
	139	suf = NULL;
	140	printf("Freescale MCF5272 (Mask:%01x)\n", msk);
	141	break;
	142	}
bf9e3b38 WD	143
bf9e3b38 WD	144	if (suf)
83ec20bc	145	printf("Freescale MCF5272 %s\n", suf);
bf9e3b38 WD	146	return 0;
	147	};
	148
bf9e3b38 WD	149	#if defined(CONFIG_WATCHDOG)
bf9e3b38 WD	150	/* Called by macro WATCHDOG_RESET */
83ec20bc	151	void watchdog_reset(void)
bf9e3b38	152	{
83ec20bc TL	153	volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);
83ec20bc TL	154	wdt->wdog_wcr = 0;
bf9e3b38 WD	155	}
bf9e3b38 WD	156
83ec20bc	157	int watchdog_disable(void)
bf9e3b38	158	{
83ec20bc	159	volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);
bf9e3b38	160
83ec20bc TL	161	wdt->wdog_wcr = 0; /* reset watchdog counter */
	162	wdt->wdog_wirr = 0; /* disable watchdog interrupt */
	163	wdt->wdog_wrrr = 0; /* disable watchdog timer */
bf9e3b38	164
83ec20bc	165	puts("WATCHDOG:disabled\n");
bf9e3b38 WD	166	return (0);
	167	}
	168
83ec20bc	169	int watchdog_init(void)
bf9e3b38	170	{
83ec20bc	171	volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);
bf9e3b38	172
83ec20bc	173	wdt->wdog_wirr = 0; /* disable watchdog interrupt */
bf9e3b38 WD	174
bf9e3b38 WD	175	/* set timeout and enable watchdog */
83ec20bc TL	176	wdt->wdog_wrrr =
	177	((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
	178	wdt->wdog_wcr = 0; /* reset watchdog counter */
bf9e3b38	179
83ec20bc	180	puts("WATCHDOG:enabled\n");
bf9e3b38 WD	181	return (0);
bf9e3b38 WD	182	}
83ec20bc	183	#endif /* #ifdef CONFIG_WATCHDOG */
bf9e3b38	184
83ec20bc	185	#endif /* #ifdef CONFIG_M5272 */
bf9e3b38	186
f71d9d91 MF	187	#ifdef CONFIG_M5275
	188	int do_reset(cmd_tbl_t cmdtp, bd_t bd, int flag, int argc, char *argv[])
	189	{
	190	volatile rcm_t rcm = (rcm_t )(MMAP_RCM);
	191
	192	udelay(1000);
	193
	194	rcm->rcr = RCM_RCR_SOFTRST;
	195
	196	/* we don't return! */
	197	return 0;
	198	};
	199
	200	int checkcpu(void)
	201	{
	202	char buf[32];
	203
	204	printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
	205	strmhz(buf, CFG_CLK));
	206	return 0;
	207	};
	208
	209
	210	#if defined(CONFIG_WATCHDOG)
	211	/* Called by macro WATCHDOG_RESET */
	212	void watchdog_reset(void)
	213	{
	214	volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);
	215	wdt->wsr = 0x5555;
	216	wdt->wsr = 0xAAAA;
	217	}
	218
	219	int watchdog_disable(void)
	220	{
	221	volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);
	222
	223	wdt->wsr = 0x5555; /* reset watchdog counter */
	224	wdt->wsr = 0xAAAA;
	225	wdt->wcr = 0; /* disable watchdog timer */
	226
	227	puts("WATCHDOG:disabled\n");
	228	return (0);
	229	}
	230
	231	int watchdog_init(void)
	232	{
	233	volatile wdog_t wdt = (volatile wdog_t )(MMAP_WDOG);
	234
	235	wdt->wcr = 0; /* disable watchdog */
	236
	237	/* set timeout and enable watchdog */
	238	wdt->wmr =
	239	((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
	240	wdt->wsr = 0x5555; /* reset watchdog counter */
	241	wdt->wsr = 0xAAAA;
	242
	243	puts("WATCHDOG:enabled\n");
	244	return (0);
	245	}
	246	#endif /* #ifdef CONFIG_WATCHDOG */
	247
	248	#endif /* #ifdef CONFIG_M5275 */
	249
bf9e3b38	250	#ifdef CONFIG_M5282
83ec20bc	251	int checkcpu(void)
bf9e3b38	252	{
4176c799	253	unsigned char resetsource = MCFRESET_RSR;
9acb626f	254
83ec20bc TL	255	printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
	256	MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
	257	printf("Reset:%s%s%s%s%s%s%s\n",
	258	(resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
	259	(resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
	260	(resetsource & MCFRESET_RSR_EXT) ? " External" : "",
	261	(resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
	262	(resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
	263	(resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
	264	(resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
bf9e3b38 WD	265	return 0;
	266	}
	267
83ec20bc	268	int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
9acb626f HS	269	{
9acb626f HS	270	MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
bf9e3b38 WD	271	return 0;
	272	};
	273	#endif
8c725b93	274
a1436a84	275	#ifdef CONFIG_M5249
83ec20bc	276	int checkcpu(void)
8c725b93 SR	277	{
	278	char buf[32];
	279
83ec20bc TL	280	printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
83ec20bc TL	281	strmhz(buf, CFG_CLK));
8c725b93 SR	282	return 0;
	283	}
	284
83ec20bc TL	285	int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
83ec20bc TL	286	{
8c725b93 SR	287	/* enable watchdog, set timeout to 0 and wait */
8c725b93 SR	288	mbar_writeByte(MCFSIM_SYPCR, 0xc0);
83ec20bc	289	while (1) ;
8c725b93 SR	290
	291	/* we don't return! */
	292	return 0;
	293	};
	294	#endif
a1436a84 TL	295
	296	#ifdef CONFIG_M5253
	297	int checkcpu(void)
	298	{
	299	char buf[32];
	300
	301	unsigned char resetsource = mbar_readLong(SIM_RSR);
	302	printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
	303	strmhz(buf, CFG_CLK));
	304
	305	if ((resetsource & SIM_RSR_HRST) \|\| (resetsource & SIM_RSR_SWTR)) {
	306	printf("Reset:%s%s\n",
	307	(resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
	308	: "",
	309	(resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
	310	"");
	311	}
	312	return 0;
	313	}
	314
	315	int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
	316	{
	317	/* enable watchdog, set timeout to 0 and wait */
	318	mbar_writeByte(SIM_SYPCR, 0xc0);
	319	while (1) ;
	320
	321	/* we don't return! */
	322	return 0;
	323	};
	324	#endif
86882b80 BW	325
	326	#if defined(CONFIG_MCFFEC)
	327	/* Default initializations for MCFFEC controllers. To override,
	328	* create a board-specific function called:
	329	* int board_eth_init(bd_t *bis)
	330	*/
	331
86882b80 BW	332	int cpu_eth_init(bd_t *bis)
	333	{
	334	return mcffec_initialize(bis);
	335	}
	336	#endif
	337