[people/ms/u-boot.git] / cpu / mcf52x2 / cpu_init.c

/*
 * (C) Copyright 2003
 * Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * MCF5282 additionals
 * (C) Copyright 2005
 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 * Hayden Fraser (Hayden.Fraser@freescale.com)
 *
 * MCF5275 additions
 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>

#if defined(CONFIG_M5253)
/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f(void)
{
	mbar_writeByte(MCFSIM_MPARK, 0x40);	/* 5249 Internal Core takes priority over DMA */
	mbar_writeByte(MCFSIM_SYPCR, 0x00);
	mbar_writeByte(MCFSIM_SWIVR, 0x0f);
	mbar_writeByte(MCFSIM_SWSR, 0x00);
	mbar_writeByte(MCFSIM_SWDICR, 0x00);
	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
	mbar_writeByte(MCFSIM_I2CICR, 0x00);
	mbar_writeByte(MCFSIM_UART1ICR, 0x00);
	mbar_writeByte(MCFSIM_UART2ICR, 0x00);
	mbar_writeByte(MCFSIM_ICR6, 0x00);
	mbar_writeByte(MCFSIM_ICR7, 0x00);
	mbar_writeByte(MCFSIM_ICR8, 0x00);
	mbar_writeByte(MCFSIM_ICR9, 0x00);
	mbar_writeByte(MCFSIM_QSPIICR, 0x00);

	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
	mbar2_writeByte(MCFSIM_INTBASE, 0x40);	/* Base interrupts at 64 */
	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);

	/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */

	/*
	 *  Setup chip selects...
	 */

	mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
	mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
	mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);

	mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
	mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
	mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);

	/* enable instruction cache now */
	icache_enable();
}

/*initialize higher level parts of CPU like timers */
int cpu_init_r(void)
{
	return (0);
}

void uart_port_conf(void)
{
	/* Setup Ports: */
	switch (CFG_UART_PORT) {
	case 0:
		break;
	case 1:
		break;
	case 2:
		break;
	}
}
#endif				/* #if defined(CONFIG_M5253) */

#if defined(CONFIG_M5271)
void cpu_init_f(void)
{
#ifndef CONFIG_WATCHDOG
	/* Disable the watchdog if we aren't using it */
	mbar_writeShort(MCF_WTM_WCR, 0);
#endif

	/* Set clockspeed to 100MHz */
	mbar_writeShort(MCF_FMPLL_SYNCR,
			MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
	while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r(void)
{
	return (0);
}

void uart_port_conf(void)
{
	/* Setup Ports: */
	switch (CFG_UART_PORT) {
	case 0:
		mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
				MCF_GPIO_PAR_UART_U0RXD);
		break;
	case 1:
		mbar_writeShort(MCF_GPIO_PAR_UART,
				MCF_GPIO_PAR_UART_U1RXD_UART1 |
				MCF_GPIO_PAR_UART_U1TXD_UART1);
		break;
	case 2:
		mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
		break;
	}
}
#endif

#if defined(CONFIG_M5272)
/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f(void)
{
	/* if we come from RAM we assume the CPU is
	 * already initialized.
	 */
#ifndef CONFIG_MONITOR_IS_IN_RAM
	volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR);
	volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
	volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);

	sysctrl->sc_scr = CFG_SCR;
	sysctrl->sc_spr = CFG_SPR;

	/* Setup Ports: */
	gpio->gpio_pacnt = CFG_PACNT;
	gpio->gpio_paddr = CFG_PADDR;
	gpio->gpio_padat = CFG_PADAT;
	gpio->gpio_pbcnt = CFG_PBCNT;
	gpio->gpio_pbddr = CFG_PBDDR;
	gpio->gpio_pbdat = CFG_PBDAT;
	gpio->gpio_pdcnt = CFG_PDCNT;

	/* Memory Controller: */
	csctrl->cs_br0 = CFG_BR0_PRELIM;
	csctrl->cs_or0 = CFG_OR0_PRELIM;

#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
	csctrl->cs_br1 = CFG_BR1_PRELIM;
	csctrl->cs_or1 = CFG_OR1_PRELIM;
#endif

#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
	csctrl->cs_br2 = CFG_BR2_PRELIM;
	csctrl->cs_or2 = CFG_OR2_PRELIM;
#endif

#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
	csctrl->cs_br3 = CFG_BR3_PRELIM;
	csctrl->cs_or3 = CFG_OR3_PRELIM;
#endif

#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
	csctrl->cs_br4 = CFG_BR4_PRELIM;
	csctrl->cs_or4 = CFG_OR4_PRELIM;
#endif

#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
	csctrl->cs_br5 = CFG_BR5_PRELIM;
	csctrl->cs_or5 = CFG_OR5_PRELIM;
#endif

#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
	csctrl->cs_br6 = CFG_BR6_PRELIM;
	csctrl->cs_or6 = CFG_OR6_PRELIM;
#endif

#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
	csctrl->cs_br7 = CFG_BR7_PRELIM;
	csctrl->cs_or7 = CFG_OR7_PRELIM;
#endif

#endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */

	/* enable instruction cache now */
	icache_enable();

}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r(void)
{
	return (0);
}

void uart_port_conf(void)
{
	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Setup Ports: */
	switch (CFG_UART_PORT) {
	case 0:
		gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
		gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
		break;
	case 1:
		gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
		gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
		break;
	}
}
#endif				/* #if defined(CONFIG_M5272) */

#if defined(CONFIG_M5275)

/*
 * Breathe some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f(void)
{
	/* if we come from RAM we assume the CPU is
	 * already initialized.
	 */

#ifndef CONFIG_MONITOR_IS_IN_RAM
	volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
	volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
	volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);

	/* Kill watchdog so we can initialize the PLL */
	wdog_reg->wcr = 0;

	/* Memory Controller: */
	/* Flash */
	csctrl_reg->ar0 = CFG_AR0_PRELIM;
	csctrl_reg->cr0 = CFG_CR0_PRELIM;
	csctrl_reg->mr0 = CFG_MR0_PRELIM;

#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
	csctrl_reg->ar1 = CFG_AR1_PRELIM;
	csctrl_reg->cr1 = CFG_CR1_PRELIM;
	csctrl_reg->mr1 = CFG_MR1_PRELIM;
#endif

#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
	csctrl_reg->ar2 = CFG_AR2_PRELIM;
	csctrl_reg->cr2 = CFG_CR2_PRELIM;
	csctrl_reg->mr2 = CFG_MR2_PRELIM;
#endif

#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
	csctrl_reg->ar3 = CFG_AR3_PRELIM;
	csctrl_reg->cr3 = CFG_CR3_PRELIM;
	csctrl_reg->mr3 = CFG_MR3_PRELIM;
#endif

#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
	csctrl_reg->ar4 = CFG_AR4_PRELIM;
	csctrl_reg->cr4 = CFG_CR4_PRELIM;
	csctrl_reg->mr4 = CFG_MR4_PRELIM;
#endif

#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
	csctrl_reg->ar5 = CFG_AR5_PRELIM;
	csctrl_reg->cr5 = CFG_CR5_PRELIM;
	csctrl_reg->mr5 = CFG_MR5_PRELIM;
#endif

#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
	csctrl_reg->ar6 = CFG_AR6_PRELIM;
	csctrl_reg->cr6 = CFG_CR6_PRELIM;
	csctrl_reg->mr6 = CFG_MR6_PRELIM;
#endif

#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
	csctrl_reg->ar7 = CFG_AR7_PRELIM;
	csctrl_reg->cr7 = CFG_CR7_PRELIM;
	csctrl_reg->mr7 = CFG_MR7_PRELIM;
#endif

#endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */

#ifdef CONFIG_FSL_I2C
	gpio_reg->par_feci2c = 0x000F;
#endif

	/* enable instruction cache now */
	icache_enable();
}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r(void)
{
	return (0);
}

void uart_port_conf(void)
{
	volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;

	/* Setup Ports: */
	switch (CFG_UART_PORT) {
	case 0:
		gpio->par_uart |= UART0_ENABLE_MASK;
		break;
	case 1:
		gpio->par_uart |= UART1_ENABLE_MASK;
		break;
	case 2:
		gpio->par_uart |= UART2_ENABLE_MASK;
		break;
	}
}
#endif				/* #if defined(CONFIG_M5275) */

#if defined(CONFIG_M5282)
/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f(void)
{
#ifndef CONFIG_WATCHDOG
	/* disable watchdog if we aren't using it */
	MCFWTM_WCR = 0;
#endif

#ifndef CONFIG_MONITOR_IS_IN_RAM
	/* Set speed /PLL */
	MCFCLOCK_SYNCR =
	    MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
	while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;

	MCFGPIO_PBCDPAR = 0xc0;

	/* Set up the GPIO ports */
#ifdef CFG_PEPAR
	MCFGPIO_PEPAR = CFG_PEPAR;
#endif
#ifdef	CFG_PFPAR
	MCFGPIO_PFPAR = CFG_PFPAR;
#endif
#ifdef CFG_PJPAR
	MCFGPIO_PJPAR = CFG_PJPAR;
#endif
#ifdef CFG_PSDPAR
	MCFGPIO_PSDPAR = CFG_PSDPAR;
#endif
#ifdef CFG_PASPAR
	MCFGPIO_PASPAR = CFG_PASPAR;
#endif
#ifdef CFG_PEHLPAR
	MCFGPIO_PEHLPAR = CFG_PEHLPAR;
#endif
#ifdef CFG_PQSPAR
	MCFGPIO_PQSPAR = CFG_PQSPAR;
#endif
#ifdef CFG_PTCPAR
	MCFGPIO_PTCPAR = CFG_PTCPAR;
#endif
#ifdef CFG_PTDPAR
	MCFGPIO_PTDPAR = CFG_PTDPAR;
#endif
#ifdef CFG_PUAPAR
	MCFGPIO_PUAPAR = CFG_PUAPAR;
#endif

#ifdef CFG_DDRUA
	MCFGPIO_DDRUA = CFG_DDRUA;
#endif

	/* This is probably a bad place to setup chip selects, but everyone
	   else is doing it! */

#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
    defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS)

	MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;

#if (CFG_CS0_WIDTH == 8)
#define	 CFG_CS0_PS  MCFCSM_CSCR_PS_8
#elif (CFG_CS0_WIDTH == 16)
#define	 CFG_CS0_PS  MCFCSM_CSCR_PS_16
#elif (CFG_CS0_WIDTH == 32)
#define	 CFG_CS0_PS  MCFCSM_CSCR_PS_32
#else
#error	"CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
#endif
	MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
	    | CFG_CS0_PS | MCFCSM_CSCR_AA;

#if (CFG_CS0_RO != 0)
	MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1)
	    | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
	MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V;
#endif
#else
#waring "Chip Select 0 are not initialized/used"
#endif

#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
    defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS)

	MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;

#if (CFG_CS1_WIDTH == 8)
#define	 CFG_CS1_PS  MCFCSM_CSCR_PS_8
#elif (CFG_CS1_WIDTH == 16)
#define	 CFG_CS1_PS  MCFCSM_CSCR_PS_16
#elif (CFG_CS1_WIDTH == 32)
#define	 CFG_CS1_PS  MCFCSM_CSCR_PS_32
#else
#error	"CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
#endif
	MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
	    | CFG_CS1_PS | MCFCSM_CSCR_AA;

#if (CFG_CS1_RO != 0)
	MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
	    | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
	MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
	    | MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 1 are not initialized/used"
#endif

#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
    defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS)

	MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;

#if (CFG_CS2_WIDTH == 8)
#define	 CFG_CS2_PS  MCFCSM_CSCR_PS_8
#elif (CFG_CS2_WIDTH == 16)
#define	 CFG_CS2_PS  MCFCSM_CSCR_PS_16
#elif (CFG_CS2_WIDTH == 32)
#define	 CFG_CS2_PS  MCFCSM_CSCR_PS_32
#else
#error	"CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
#endif
	MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
	    | CFG_CS2_PS | MCFCSM_CSCR_AA;

#if (CFG_CS2_RO != 0)
	MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
	    | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
	MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
	    | MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 2 are not initialized/used"
#endif

#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
    defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS)

	MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;

#if (CFG_CS3_WIDTH == 8)
#define	 CFG_CS3_PS  MCFCSM_CSCR_PS_8
#elif (CFG_CS3_WIDTH == 16)
#define	 CFG_CS3_PS  MCFCSM_CSCR_PS_16
#elif (CFG_CS3_WIDTH == 32)
#define	 CFG_CS3_PS  MCFCSM_CSCR_PS_32
#else
#error	"CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
#endif
	MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
	    | CFG_CS3_PS | MCFCSM_CSCR_AA;

#if (CFG_CS3_RO != 0)
	MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
	    | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
#else
	MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
	    | MCFCSM_CSMR_V;
#endif
#else
#warning "Chip Select 3 are not initialized/used"
#endif

#endif				/* CONFIG_MONITOR_IS_IN_RAM */

	/* defer enabling cache until boot (see do_go) */
	/* icache_enable(); */
}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r(void)
{
	return (0);
}

void uart_port_conf(void)
{
	/* Setup Ports: */
	switch (CFG_UART_PORT) {
	case 0:
		MCFGPIO_PUAPAR &= 0xFc;
		MCFGPIO_PUAPAR |= 0x03;
		break;
	case 1:
		MCFGPIO_PUAPAR &= 0xF3;
		MCFGPIO_PUAPAR |= 0x0C;
		break;
	case 2:
		MCFGPIO_PASPAR &= 0xFF0F;
		MCFGPIO_PASPAR |= 0x00A0;
		break;
	}
}
#endif

#if defined(CONFIG_M5249)
/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f(void)
{
	/*
	 *  NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
	 *        (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
	 *        which is their primary function.
	 *        ~Jeremy
	 */
	mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
	mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
	mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN);
	mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN);
	mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT);
	mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT);

	/*
	 *  dBug Compliance:
	 *    You can verify these values by using dBug's 'ird'
	 *    (Internal Register Display) command
	 *    ~Jeremy
	 *
	 */
	mbar_writeByte(MCFSIM_MPARK, 0x30);	/* 5249 Internal Core takes priority over DMA */
	mbar_writeByte(MCFSIM_SYPCR, 0x00);
	mbar_writeByte(MCFSIM_SWIVR, 0x0f);
	mbar_writeByte(MCFSIM_SWSR, 0x00);
	mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
	mbar_writeByte(MCFSIM_SWDICR, 0x00);
	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
	mbar_writeByte(MCFSIM_I2CICR, 0x00);
	mbar_writeByte(MCFSIM_UART1ICR, 0x00);
	mbar_writeByte(MCFSIM_UART2ICR, 0x00);
	mbar_writeByte(MCFSIM_ICR6, 0x00);
	mbar_writeByte(MCFSIM_ICR7, 0x00);
	mbar_writeByte(MCFSIM_ICR8, 0x00);
	mbar_writeByte(MCFSIM_ICR9, 0x00);
	mbar_writeByte(MCFSIM_QSPIICR, 0x00);

	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
	mbar2_writeByte(MCFSIM_INTBASE, 0x40);	/* Base interrupts at 64 */
	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);	/* Enable a 1 cycle pre-drive cycle on CS1 */

	/* Setup interrupt priorities for gpio7 */
	/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */

	/* IDE Config registers */
	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
	mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);

	/*
	 *  Setup chip selects...
	 */

	mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
	mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
	mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);

	mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
	mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
	mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);

	/* enable instruction cache now */
	icache_enable();
}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r(void)
{
	return (0);
}

void uart_port_conf(void)
{
	/* Setup Ports: */
	switch (CFG_UART_PORT) {
	case 0:
		break;
	case 1:
		break;
	}
}
#endif				/* #if defined(CONFIG_M5249) */
Commit	Line	Data
bf9e3b38 WD	1	/*
	2	* (C) Copyright 2003
	3	* Josef Baumgartner <josef.baumgartner@telex.de>
	4	*
9acb626f HS	5	* MCF5282 additionals
	6	* (C) Copyright 2005
	7	* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
	8	*
a1436a84 TL	9	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	10	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	11	* Hayden Fraser (Hayden.Fraser@freescale.com)
	12	*
f71d9d91 MF	13	* MCF5275 additions
	14	* Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
	15	*
bf9e3b38 WD	16	* See file CREDITS for list of people who contributed to this
	17	* project.
	18	*
	19	* This program is free software; you can redistribute it and/or
	20	* modify it under the terms of the GNU General Public License as
	21	* published by the Free Software Foundation; either version 2 of
	22	* the License, or (at your option) any later version.
	23	*
	24	* This program is distributed in the hope that it will be useful,
	25	* but WITHOUT ANY WARRANTY; without even the implied warranty of
977b50f8	26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
bf9e3b38 WD	27	* GNU General Public License for more details.
	28	*
	29	* You should have received a copy of the GNU General Public License
	30	* along with this program; if not, write to the Free Software
	31	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	32	* MA 02111-1307 USA
	33	*/
	34
	35	#include <common.h>
	36	#include <watchdog.h>
83ec20bc	37	#include <asm/immap.h>
8c725b93	38
a1436a84 TL	39	#if defined(CONFIG_M5253)
	40	/*
	41	* Breath some life into the CPU...
	42	*
	43	* Set up the memory map,
	44	* initialize a bunch of registers,
	45	* initialize the UPM's
	46	*/
	47	void cpu_init_f(void)
	48	{
	49	mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
	50	mbar_writeByte(MCFSIM_SYPCR, 0x00);
	51	mbar_writeByte(MCFSIM_SWIVR, 0x0f);
	52	mbar_writeByte(MCFSIM_SWSR, 0x00);
	53	mbar_writeByte(MCFSIM_SWDICR, 0x00);
	54	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
	55	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
	56	mbar_writeByte(MCFSIM_I2CICR, 0x00);
	57	mbar_writeByte(MCFSIM_UART1ICR, 0x00);
	58	mbar_writeByte(MCFSIM_UART2ICR, 0x00);
	59	mbar_writeByte(MCFSIM_ICR6, 0x00);
	60	mbar_writeByte(MCFSIM_ICR7, 0x00);
	61	mbar_writeByte(MCFSIM_ICR8, 0x00);
	62	mbar_writeByte(MCFSIM_ICR9, 0x00);
	63	mbar_writeByte(MCFSIM_QSPIICR, 0x00);
	64
	65	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
	66	mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
	67	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
	68
8280f6a1	69	/mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); / /* Enable a 1 cycle pre-drive cycle on CS1 */
a1436a84 TL	70
	71	/*
	72	* Setup chip selects...
	73	*/
	74
	75	mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
	76	mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
	77	mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
	78
	79	mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
	80	mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
	81	mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
	82
	83	/* enable instruction cache now */
	84	icache_enable();
	85	}
	86
	87	/initialize higher level parts of CPU like timers /
	88	int cpu_init_r(void)
	89	{
	90	return (0);
	91	}
	92
	93	void uart_port_conf(void)
	94	{
	95	/* Setup Ports: */
	96	switch (CFG_UART_PORT) {
	97	case 0:
	98	break;
	99	case 1:
	100	break;
	101	case 2:
	102	break;
	103	}
	104	}
	105	#endif /* #if defined(CONFIG_M5253) */
	106
eacbd317	107	#if defined(CONFIG_M5271)
83ec20bc	108	void cpu_init_f(void)
eacbd317 ZL	109	{
	110	#ifndef CONFIG_WATCHDOG
	111	/* Disable the watchdog if we aren't using it */
	112	mbar_writeShort(MCF_WTM_WCR, 0);
	113	#endif
	114
	115	/* Set clockspeed to 100MHz */
	116	mbar_writeShort(MCF_FMPLL_SYNCR,
	117	MCF_FMPLL_SYNCR_MFD(0) \| MCF_FMPLL_SYNCR_RFD(0));
83ec20bc	118	while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
eacbd317 ZL	119	}
	120
	121	/*
	122	* initialize higher level parts of CPU like timers
	123	*/
83ec20bc	124	int cpu_init_r(void)
eacbd317 ZL	125	{
	126	return (0);
	127	}
83ec20bc TL	128
	129	void uart_port_conf(void)
	130	{
	131	/* Setup Ports: */
	132	switch (CFG_UART_PORT) {
	133	case 0:
	134	mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD \|
	135	MCF_GPIO_PAR_UART_U0RXD);
	136	break;
	137	case 1:
	138	mbar_writeShort(MCF_GPIO_PAR_UART,
	139	MCF_GPIO_PAR_UART_U1RXD_UART1 \|
	140	MCF_GPIO_PAR_UART_U1TXD_UART1);
	141	break;
	142	case 2:
	143	mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
	144	break;
	145	}
	146	}
eacbd317 ZL	147	#endif
eacbd317 ZL	148
8c725b93	149	#if defined(CONFIG_M5272)
bf9e3b38 WD	150	/*
	151	* Breath some life into the CPU...
	152	*
	153	* Set up the memory map,
	154	* initialize a bunch of registers,
	155	* initialize the UPM's
	156	*/
83ec20bc	157	void cpu_init_f(void)
bf9e3b38 WD	158	{
	159	/* if we come from RAM we assume the CPU is
	160	* already initialized.
	161	*/
	162	#ifndef CONFIG_MONITOR_IS_IN_RAM
83ec20bc TL	163	volatile sysctrl_t sysctrl = (sysctrl_t ) (CFG_MBAR);
	164	volatile gpio_t gpio = (gpio_t ) (MMAP_GPIO);
	165	volatile csctrl_t csctrl = (csctrl_t ) (MMAP_FBCS);
bf9e3b38	166
83ec20bc TL	167	sysctrl->sc_scr = CFG_SCR;
83ec20bc TL	168	sysctrl->sc_spr = CFG_SPR;
bf9e3b38	169
977b50f8	170	/* Setup Ports: */
83ec20bc TL	171	gpio->gpio_pacnt = CFG_PACNT;
	172	gpio->gpio_paddr = CFG_PADDR;
	173	gpio->gpio_padat = CFG_PADAT;
	174	gpio->gpio_pbcnt = CFG_PBCNT;
	175	gpio->gpio_pbddr = CFG_PBDDR;
	176	gpio->gpio_pbdat = CFG_PBDAT;
	177	gpio->gpio_pdcnt = CFG_PDCNT;
bf9e3b38 WD	178
bf9e3b38 WD	179	/* Memory Controller: */
83ec20bc TL	180	csctrl->cs_br0 = CFG_BR0_PRELIM;
83ec20bc TL	181	csctrl->cs_or0 = CFG_OR0_PRELIM;
bf9e3b38 WD	182
bf9e3b38 WD	183	#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
83ec20bc TL	184	csctrl->cs_br1 = CFG_BR1_PRELIM;
83ec20bc TL	185	csctrl->cs_or1 = CFG_OR1_PRELIM;
bf9e3b38 WD	186	#endif
	187
	188	#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
83ec20bc TL	189	csctrl->cs_br2 = CFG_BR2_PRELIM;
83ec20bc TL	190	csctrl->cs_or2 = CFG_OR2_PRELIM;
bf9e3b38 WD	191	#endif
	192
	193	#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
83ec20bc TL	194	csctrl->cs_br3 = CFG_BR3_PRELIM;
83ec20bc TL	195	csctrl->cs_or3 = CFG_OR3_PRELIM;
bf9e3b38 WD	196	#endif
	197
	198	#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
83ec20bc TL	199	csctrl->cs_br4 = CFG_BR4_PRELIM;
83ec20bc TL	200	csctrl->cs_or4 = CFG_OR4_PRELIM;
bf9e3b38 WD	201	#endif
	202
	203	#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
83ec20bc TL	204	csctrl->cs_br5 = CFG_BR5_PRELIM;
83ec20bc TL	205	csctrl->cs_or5 = CFG_OR5_PRELIM;
bf9e3b38 WD	206	#endif
	207
	208	#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
83ec20bc TL	209	csctrl->cs_br6 = CFG_BR6_PRELIM;
83ec20bc TL	210	csctrl->cs_or6 = CFG_OR6_PRELIM;
bf9e3b38 WD	211	#endif
	212
	213	#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
83ec20bc TL	214	csctrl->cs_br7 = CFG_BR7_PRELIM;
83ec20bc TL	215	csctrl->cs_or7 = CFG_OR7_PRELIM;
bf9e3b38 WD	216	#endif
bf9e3b38 WD	217
83ec20bc	218	#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
bf9e3b38	219
977b50f8 WD	220	/* enable instruction cache now */
977b50f8 WD	221	icache_enable();
bf9e3b38 WD	222
	223	}
	224
	225	/*
	226	* initialize higher level parts of CPU like timers
	227	*/
83ec20bc	228	int cpu_init_r(void)
bf9e3b38 WD	229	{
	230	return (0);
	231	}
bf9e3b38	232
83ec20bc TL	233	void uart_port_conf(void)
	234	{
	235	volatile gpio_t gpio = (gpio_t ) MMAP_GPIO;
	236
	237	/* Setup Ports: */
	238	switch (CFG_UART_PORT) {
	239	case 0:
	240	gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK \| GPIO_PBCNT_PB1MSK);
	241	gpio->gpio_pbcnt \|= (GPIO_PBCNT_URT0_TXD \| GPIO_PBCNT_URT0_RXD);
	242	break;
	243	case 1:
	244	gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK \| GPIO_PDCNT_PD4MSK);
	245	gpio->gpio_pdcnt \|= (GPIO_PDCNT_URT1_RXD \| GPIO_PDCNT_URT1_TXD);
	246	break;
	247	}
	248	}
	249	#endif /* #if defined(CONFIG_M5272) */
bf9e3b38	250
f71d9d91 MF	251	#if defined(CONFIG_M5275)
	252
	253	/*
	254	* Breathe some life into the CPU...
	255	*
	256	* Set up the memory map,
	257	* initialize a bunch of registers,
	258	* initialize the UPM's
	259	*/
	260	void cpu_init_f(void)
	261	{
	262	/* if we come from RAM we assume the CPU is
	263	* already initialized.
	264	*/
	265
	266	#ifndef CONFIG_MONITOR_IS_IN_RAM
	267	volatile wdog_t wdog_reg = (wdog_t )(MMAP_WDOG);
	268	volatile gpio_t gpio_reg = (gpio_t )(MMAP_GPIO);
	269	volatile csctrl_t csctrl_reg = (csctrl_t )(MMAP_FBCS);
	270
	271	/* Kill watchdog so we can initialize the PLL */
	272	wdog_reg->wcr = 0;
	273
	274	/* Memory Controller: */
	275	/* Flash */
	276	csctrl_reg->ar0 = CFG_AR0_PRELIM;
	277	csctrl_reg->cr0 = CFG_CR0_PRELIM;
	278	csctrl_reg->mr0 = CFG_MR0_PRELIM;
	279
	280	#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
	281	csctrl_reg->ar1 = CFG_AR1_PRELIM;
	282	csctrl_reg->cr1 = CFG_CR1_PRELIM;
	283	csctrl_reg->mr1 = CFG_MR1_PRELIM;
	284	#endif
	285
	286	#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
	287	csctrl_reg->ar2 = CFG_AR2_PRELIM;
	288	csctrl_reg->cr2 = CFG_CR2_PRELIM;
	289	csctrl_reg->mr2 = CFG_MR2_PRELIM;
	290	#endif
	291
	292	#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
	293	csctrl_reg->ar3 = CFG_AR3_PRELIM;
	294	csctrl_reg->cr3 = CFG_CR3_PRELIM;
	295	csctrl_reg->mr3 = CFG_MR3_PRELIM;
	296	#endif
	297
	298	#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
	299	csctrl_reg->ar4 = CFG_AR4_PRELIM;
	300	csctrl_reg->cr4 = CFG_CR4_PRELIM;
	301	csctrl_reg->mr4 = CFG_MR4_PRELIM;
	302	#endif
	303
	304	#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
	305	csctrl_reg->ar5 = CFG_AR5_PRELIM;
	306	csctrl_reg->cr5 = CFG_CR5_PRELIM;
	307	csctrl_reg->mr5 = CFG_MR5_PRELIM;
	308	#endif
	309
	310	#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
	311	csctrl_reg->ar6 = CFG_AR6_PRELIM;
	312	csctrl_reg->cr6 = CFG_CR6_PRELIM;
	313	csctrl_reg->mr6 = CFG_MR6_PRELIM;
	314	#endif
315
316	#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
317	csctrl_reg->ar7 = CFG_AR7_PRELIM;
318	csctrl_reg->cr7 = CFG_CR7_PRELIM;
319	csctrl_reg->mr7 = CFG_MR7_PRELIM;
320	#endif
321
322	#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
323
324	#ifdef CONFIG_FSL_I2C
325	gpio_reg->par_feci2c = 0x000F;
326	#endif
327
328	/* enable instruction cache now */
329	icache_enable();
330	}
331
332	/*
333	* initialize higher level parts of CPU like timers
334	*/
335	int cpu_init_r(void)
336	{
337	return (0);
338	}
339
340	void uart_port_conf(void)
341	{
342	volatile gpio_t gpio = (gpio_t )MMAP_GPIO;
343
344	/* Setup Ports: */
345	switch (CFG_UART_PORT) {
346	case 0:
347	gpio->par_uart \|= UART0_ENABLE_MASK;
348	break;
349	case 1:
350	gpio->par_uart \|= UART1_ENABLE_MASK;
351	break;
352	case 2:
353	gpio->par_uart \|= UART2_ENABLE_MASK;
354	break;
355	}
356	}
357	#endif /* #if defined(CONFIG_M5275) */
358
83ec20bc	359	#if defined(CONFIG_M5282)
bf9e3b38 WD	360	/*
	361	* Breath some life into the CPU...
	362	*
	363	* Set up the memory map,
	364	* initialize a bunch of registers,
	365	* initialize the UPM's
	366	*/
83ec20bc	367	void cpu_init_f(void)
bf9e3b38	368	{
9acb626f HS	369	#ifndef CONFIG_WATCHDOG
	370	/* disable watchdog if we aren't using it */
	371	MCFWTM_WCR = 0;
	372	#endif
	373
	374	#ifndef CONFIG_MONITOR_IS_IN_RAM
	375	/* Set speed /PLL */
83ec20bc TL	376	MCFCLOCK_SYNCR =
	377	MCFCLOCK_SYNCR_MFD(CFG_MFD) \| MCFCLOCK_SYNCR_RFD(CFG_RFD);
	378	while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
	379
	380	MCFGPIO_PBCDPAR = 0xc0;
9acb626f HS	381
	382	/* Set up the GPIO ports */
	383	#ifdef CFG_PEPAR
	384	MCFGPIO_PEPAR = CFG_PEPAR;
	385	#endif
	386	#ifdef CFG_PFPAR
	387	MCFGPIO_PFPAR = CFG_PFPAR;
	388	#endif
	389	#ifdef CFG_PJPAR
	390	MCFGPIO_PJPAR = CFG_PJPAR;
	391	#endif
	392	#ifdef CFG_PSDPAR
	393	MCFGPIO_PSDPAR = CFG_PSDPAR;
	394	#endif
	395	#ifdef CFG_PASPAR
	396	MCFGPIO_PASPAR = CFG_PASPAR;
	397	#endif
	398	#ifdef CFG_PEHLPAR
	399	MCFGPIO_PEHLPAR = CFG_PEHLPAR;
	400	#endif
	401	#ifdef CFG_PQSPAR
	402	MCFGPIO_PQSPAR = CFG_PQSPAR;
	403	#endif
	404	#ifdef CFG_PTCPAR
	405	MCFGPIO_PTCPAR = CFG_PTCPAR;
	406	#endif
	407	#ifdef CFG_PTDPAR
	408	MCFGPIO_PTDPAR = CFG_PTDPAR;
	409	#endif
	410	#ifdef CFG_PUAPAR
	411	MCFGPIO_PUAPAR = CFG_PUAPAR;
	412	#endif
	413
	414	#ifdef CFG_DDRUA
	415	MCFGPIO_DDRUA = CFG_DDRUA;
	416	#endif
	417
	418	/* This is probably a bad place to setup chip selects, but everyone
	419	else is doing it! */
	420
	421	#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
47bf9c71	422	defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS)
9acb626f	423
83ec20bc TL	424	MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
	425
	426	#if (CFG_CS0_WIDTH == 8)
	427	#define CFG_CS0_PS MCFCSM_CSCR_PS_8
	428	#elif (CFG_CS0_WIDTH == 16)
	429	#define CFG_CS0_PS MCFCSM_CSCR_PS_16
	430	#elif (CFG_CS0_WIDTH == 32)
	431	#define CFG_CS0_PS MCFCSM_CSCR_PS_32
9acb626f	432	#else
83ec20bc TL	433	#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
	434	#endif
	435	MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
	436	\| CFG_CS0_PS \| MCFCSM_CSCR_AA;
	437
	438	#if (CFG_CS0_RO != 0)
	439	MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1)
	440	\| MCFCSM_CSMR_WP \| MCFCSM_CSMR_V;
	441	#else
	442	MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) \| MCFCSM_CSMR_V;
	443	#endif
	444	#else
	445	#waring "Chip Select 0 are not initialized/used"
9acb626f HS	446	#endif
	447
	448	#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
47bf9c71	449	defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS)
9acb626f HS	450
	451	MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
	452
83ec20bc TL	453	#if (CFG_CS1_WIDTH == 8)
	454	#define CFG_CS1_PS MCFCSM_CSCR_PS_8
	455	#elif (CFG_CS1_WIDTH == 16)
	456	#define CFG_CS1_PS MCFCSM_CSCR_PS_16
	457	#elif (CFG_CS1_WIDTH == 32)
	458	#define CFG_CS1_PS MCFCSM_CSCR_PS_32
	459	#else
	460	#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
	461	#endif
	462	MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
	463	\| CFG_CS1_PS \| MCFCSM_CSCR_AA;
	464
	465	#if (CFG_CS1_RO != 0)
	466	MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
	467	\| MCFCSM_CSMR_WP \| MCFCSM_CSMR_V;
	468	#else
	469	MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
	470	\| MCFCSM_CSMR_V;
	471	#endif
9acb626f	472	#else
83ec20bc	473	#warning "Chip Select 1 are not initialized/used"
9acb626f HS	474	#endif
	475
	476	#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
47bf9c71	477	defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS)
9acb626f HS	478
	479	MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
	480
83ec20bc TL	481	#if (CFG_CS2_WIDTH == 8)
	482	#define CFG_CS2_PS MCFCSM_CSCR_PS_8
	483	#elif (CFG_CS2_WIDTH == 16)
	484	#define CFG_CS2_PS MCFCSM_CSCR_PS_16
	485	#elif (CFG_CS2_WIDTH == 32)
	486	#define CFG_CS2_PS MCFCSM_CSCR_PS_32
9acb626f	487	#else
83ec20bc TL	488	#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
	489	#endif
	490	MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
	491	\| CFG_CS2_PS \| MCFCSM_CSCR_AA;
	492
	493	#if (CFG_CS2_RO != 0)
	494	MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
	495	\| MCFCSM_CSMR_WP \| MCFCSM_CSMR_V;
	496	#else
	497	MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
	498	\| MCFCSM_CSMR_V;
	499	#endif
	500	#else
	501	#warning "Chip Select 2 are not initialized/used"
9acb626f HS	502	#endif
	503
	504	#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
47bf9c71	505	defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS)
9acb626f HS	506
	507	MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
	508
83ec20bc TL	509	#if (CFG_CS3_WIDTH == 8)
	510	#define CFG_CS3_PS MCFCSM_CSCR_PS_8
	511	#elif (CFG_CS3_WIDTH == 16)
	512	#define CFG_CS3_PS MCFCSM_CSCR_PS_16
	513	#elif (CFG_CS3_WIDTH == 32)
	514	#define CFG_CS3_PS MCFCSM_CSCR_PS_32
	515	#else
	516	#error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
	517	#endif
	518	MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
	519	\| CFG_CS3_PS \| MCFCSM_CSCR_AA;
	520
	521	#if (CFG_CS3_RO != 0)
	522	MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
	523	\| MCFCSM_CSMR_WP \| MCFCSM_CSMR_V;
	524	#else
	525	MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
	526	\| MCFCSM_CSMR_V;
	527	#endif
9acb626f	528	#else
83ec20bc	529	#warning "Chip Select 3 are not initialized/used"
9acb626f HS	530	#endif
9acb626f HS	531
83ec20bc	532	#endif /* CONFIG_MONITOR_IS_IN_RAM */
bf9e3b38	533
9acb626f HS	534	/* defer enabling cache until boot (see do_go) */
9acb626f HS	535	/* icache_enable(); */
bf9e3b38 WD	536	}
	537
	538	/*
	539	* initialize higher level parts of CPU like timers
	540	*/
83ec20bc	541	int cpu_init_r(void)
bf9e3b38 WD	542	{
	543	return (0);
	544	}
83ec20bc TL	545
	546	void uart_port_conf(void)
	547	{
	548	/* Setup Ports: */
	549	switch (CFG_UART_PORT) {
	550	case 0:
	551	MCFGPIO_PUAPAR &= 0xFc;
	552	MCFGPIO_PUAPAR \|= 0x03;
	553	break;
	554	case 1:
	555	MCFGPIO_PUAPAR &= 0xF3;
	556	MCFGPIO_PUAPAR \|= 0x0C;
	557	break;
	558	case 2:
	559	MCFGPIO_PASPAR &= 0xFF0F;
	560	MCFGPIO_PASPAR \|= 0x00A0;
	561	break;
	562	}
	563	}
bf9e3b38	564	#endif
8c725b93 SR	565
	566	#if defined(CONFIG_M5249)
	567	/*
	568	* Breath some life into the CPU...
	569	*
	570	* Set up the memory map,
	571	* initialize a bunch of registers,
	572	* initialize the UPM's
	573	*/
83ec20bc	574	void cpu_init_f(void)
8c725b93	575	{
8c725b93 SR	576	/*
8c725b93 SR	577	* NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
83ec20bc TL	578	* (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
	579	* which is their primary function.
	580	* ~Jeremy
8c725b93 SR	581	*/
	582	mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
	583	mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
	584	mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN);
	585	mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN);
	586	mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT);
	587	mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT);
	588
	589	/*
	590	* dBug Compliance:
	591	* You can verify these values by using dBug's 'ird'
	592	* (Internal Register Display) command
	593	* ~Jeremy
	594	*
977b50f8	595	*/
83ec20bc	596	mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
8c725b93 SR	597	mbar_writeByte(MCFSIM_SYPCR, 0x00);
	598	mbar_writeByte(MCFSIM_SWIVR, 0x0f);
	599	mbar_writeByte(MCFSIM_SWSR, 0x00);
	600	mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
	601	mbar_writeByte(MCFSIM_SWDICR, 0x00);
	602	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
	603	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
	604	mbar_writeByte(MCFSIM_I2CICR, 0x00);
	605	mbar_writeByte(MCFSIM_UART1ICR, 0x00);
	606	mbar_writeByte(MCFSIM_UART2ICR, 0x00);
	607	mbar_writeByte(MCFSIM_ICR6, 0x00);
	608	mbar_writeByte(MCFSIM_ICR7, 0x00);
	609	mbar_writeByte(MCFSIM_ICR8, 0x00);
	610	mbar_writeByte(MCFSIM_ICR9, 0x00);
	611	mbar_writeByte(MCFSIM_QSPIICR, 0x00);
	612
	613	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
977b50f8	614	mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
8c725b93	615	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
83ec20bc	616	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
8c725b93 SR	617
	618	/* Setup interrupt priorities for gpio7 */
	619	/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
	620
	621	/* IDE Config registers */
	622	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
	623	mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
	624
	625	/*
	626	* Setup chip selects...
	627	*/
	628
	629	mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
	630	mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
	631	mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
	632
	633	mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
	634	mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
	635	mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
	636
	637	/* enable instruction cache now */
	638	icache_enable();
	639	}
	640
	641	/*
	642	* initialize higher level parts of CPU like timers
	643	*/
83ec20bc	644	int cpu_init_r(void)
8c725b93 SR	645	{
	646	return (0);
	647	}
83ec20bc TL	648
	649	void uart_port_conf(void)
	650	{
	651	/* Setup Ports: */
	652	switch (CFG_UART_PORT) {
	653	case 0:
	654	break;
	655	case 1:
	656	break;
	657	}
	658	}
	659	#endif /* #if defined(CONFIG_M5249) */