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Add MCF5282 support (without preloader)
[people/ms/u-boot.git] / cpu / mcf52x2 / cpu_init.c
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bf9e3b38
WD		 1/*
2 * (C) Copyright 2003
3 * Josef Baumgartner <josef.baumgartner@telex.de>
4 *
9acb626f
HS		 5 * MCF5282 additionals
6 * (C) Copyright 2005
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
8 *
bf9e3b38
WD		 9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <watchdog.h>
30
31#ifdef CONFIG_M5272
32#include <asm/m5272.h>
33#include <asm/immap_5272.h>
34#endif
35
36#ifdef CONFIG_M5282
37#include <asm/m5282.h>
38#include <asm/immap_5282.h>
39#endif
40
8c725b93
SR		 41#ifdef CONFIG_M5249
42#include <asm/m5249.h>
43#endif
44
45#if defined(CONFIG_M5272)
bf9e3b38
WD		 46/*
47 * Breath some life into the CPU...
48 *
49 * Set up the memory map,
50 * initialize a bunch of registers,
51 * initialize the UPM's
52 */
53void cpu_init_f (void)
54{
55 /* if we come from RAM we assume the CPU is
56 * already initialized.
57 */
58#ifndef CONFIG_MONITOR_IS_IN_RAM
59 volatile immap_t *regp = (immap_t *)CFG_MBAR;
60
61 volatile unsigned char *mbar;
62 mbar = (volatile unsigned char *) CFG_MBAR;
63
64 regp->sysctrl_reg.sc_scr = CFG_SCR;
65 regp->sysctrl_reg.sc_spr = CFG_SPR;
66
67 /* Setup Ports: */
68 regp->gpio_reg.gpio_pacnt = CFG_PACNT;
69 regp->gpio_reg.gpio_paddr = CFG_PADDR;
70 regp->gpio_reg.gpio_padat = CFG_PADAT;
71 regp->gpio_reg.gpio_pbcnt = CFG_PBCNT;
72 regp->gpio_reg.gpio_pbddr = CFG_PBDDR;
73 regp->gpio_reg.gpio_pbdat = CFG_PBDAT;
74 regp->gpio_reg.gpio_pdcnt = CFG_PDCNT;
75
76 /* Memory Controller: */
77 regp->csctrl_reg.cs_br0 = CFG_BR0_PRELIM;
78 regp->csctrl_reg.cs_or0 = CFG_OR0_PRELIM;
79
80#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
81 regp->csctrl_reg.cs_br1 = CFG_BR1_PRELIM;
82 regp->csctrl_reg.cs_or1 = CFG_OR1_PRELIM;
83#endif
84
85#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
86 regp->csctrl_reg.cs_br2 = CFG_BR2_PRELIM;
87 regp->csctrl_reg.cs_or2 = CFG_OR2_PRELIM;
88#endif
89
90#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
91 regp->csctrl_reg.cs_br3 = CFG_BR3_PRELIM;
92 regp->csctrl_reg.cs_or3 = CFG_OR3_PRELIM;
93#endif
94
95#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
96 regp->csctrl_reg.cs_br4 = CFG_BR4_PRELIM;
97 regp->csctrl_reg.cs_or4 = CFG_OR4_PRELIM;
98#endif
99
100#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
101 regp->csctrl_reg.cs_br5 = CFG_BR5_PRELIM;
102 regp->csctrl_reg.cs_or5 = CFG_OR5_PRELIM;
103#endif
104
105#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
106 regp->csctrl_reg.cs_br6 = CFG_BR6_PRELIM;
107 regp->csctrl_reg.cs_or6 = CFG_OR6_PRELIM;
108#endif
109
110#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
111 regp->csctrl_reg.cs_br7 = CFG_BR7_PRELIM;
112 regp->csctrl_reg.cs_or7 = CFG_OR7_PRELIM;
113#endif
114
115#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
116
117 /* enable instruction cache now */
118 icache_enable();
119
120}
121
122/*
123 * initialize higher level parts of CPU like timers
124 */
125int cpu_init_r (void)
126{
127 return (0);
128}
8c725b93 129#endif /* #if defined(CONFIG_M5272) */
bf9e3b38
WD		 130
131
132#ifdef CONFIG_M5282
133/*
134 * Breath some life into the CPU...
135 *
136 * Set up the memory map,
137 * initialize a bunch of registers,
138 * initialize the UPM's
139 */
140void cpu_init_f (void)
141{
9acb626f
HS		 142#ifndef CONFIG_WATCHDOG
143 /* disable watchdog if we aren't using it */
144 MCFWTM_WCR = 0;
145#endif
146
147#ifndef CONFIG_MONITOR_IS_IN_RAM
148 /* Set speed /PLL */
149 MCFCLOCK_SYNCR = MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
150
151 /* Set up the GPIO ports */
152#ifdef CFG_PEPAR
153 MCFGPIO_PEPAR = CFG_PEPAR;
154#endif
155#ifdef CFG_PFPAR
156 MCFGPIO_PFPAR = CFG_PFPAR;
157#endif
158#ifdef CFG_PJPAR
159 MCFGPIO_PJPAR = CFG_PJPAR;
160#endif
161#ifdef CFG_PSDPAR
162 MCFGPIO_PSDPAR = CFG_PSDPAR;
163#endif
164#ifdef CFG_PASPAR
165 MCFGPIO_PASPAR = CFG_PASPAR;
166#endif
167#ifdef CFG_PEHLPAR
168 MCFGPIO_PEHLPAR = CFG_PEHLPAR;
169#endif
170#ifdef CFG_PQSPAR
171 MCFGPIO_PQSPAR = CFG_PQSPAR;
172#endif
173#ifdef CFG_PTCPAR
174 MCFGPIO_PTCPAR = CFG_PTCPAR;
175#endif
176#ifdef CFG_PTDPAR
177 MCFGPIO_PTDPAR = CFG_PTDPAR;
178#endif
179#ifdef CFG_PUAPAR
180 MCFGPIO_PUAPAR = CFG_PUAPAR;
181#endif
182
183#ifdef CFG_DDRUA
184 MCFGPIO_DDRUA = CFG_DDRUA;
185#endif
186
187 /* This is probably a bad place to setup chip selects, but everyone
188 else is doing it! */
189
190#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
191 defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
192 defined(CFG_CS0_WS)
193
194 MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
195
196 #if (CFG_CS0_WIDTH == 8)
197 #define CFG_CS0_PS MCFCSM_CSCR_PS_8
198 #elif (CFG_CS0_WIDTH == 16)
199 #define CFG_CS0_PS MCFCSM_CSCR_PS_16
200 #elif (CFG_CS0_WIDTH == 32)
201 #define CFG_CS0_PS MCFCSM_CSCR_PS_32
202 #else
203 #error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
204 #endif
205 MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
206 |CFG_CS0_PS
207 |MCFCSM_CSCR_AA;
208
209 #if (CFG_CS0_RO != 0)
210 MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)
211 |MCFCSM_CSMR_WP|MCFCSM_CSMR_V;
212 #else
213 MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)|MCFCSM_CSMR_V;
214 #endif
215#else
216 #waring "Chip Select 0 are not initialized/used"
217#endif
218
219#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
220 defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \
221 defined(CFG_CS1_WS)
222
223 MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
224
225 #if (CFG_CS1_WIDTH == 8)
226 #define CFG_CS1_PS MCFCSM_CSCR_PS_8
227 #elif (CFG_CS1_WIDTH == 16)
228 #define CFG_CS1_PS MCFCSM_CSCR_PS_16
229 #elif (CFG_CS1_WIDTH == 32)
230 #define CFG_CS1_PS MCFCSM_CSCR_PS_32
231 #else
232 #error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
233 #endif
234 MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
235 |CFG_CS1_PS
236 |MCFCSM_CSCR_AA;
237
238 #if (CFG_CS1_RO != 0)
239 MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
240 |MCFCSM_CSMR_WP
241 |MCFCSM_CSMR_V;
242 #else
243 MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
244 |MCFCSM_CSMR_V;
245 #endif
246#else
247 #warning "Chip Select 1 are not initialized/used"
248#endif
249
250#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
251 defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \
252 defined(CFG_CS2_WS)
253
254 MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
255
256 #if (CFG_CS2_WIDTH == 8)
257 #define CFG_CS2_PS MCFCSM_CSCR_PS_8
258 #elif (CFG_CS2_WIDTH == 16)
259 #define CFG_CS2_PS MCFCSM_CSCR_PS_16
260 #elif (CFG_CS2_WIDTH == 32)
261 #define CFG_CS2_PS MCFCSM_CSCR_PS_32
262 #else
263 #error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
264 #endif
265 MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
266 |CFG_CS2_PS
267 |MCFCSM_CSCR_AA;
268
269 #if (CFG_CS2_RO != 0)
270 MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
271 |MCFCSM_CSMR_WP
272 |MCFCSM_CSMR_V;
273 #else
274 MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
275 |MCFCSM_CSMR_V;
276 #endif
277#else
278 #warning "Chip Select 2 are not initialized/used"
279#endif
280
281#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
282 defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \
283 defined(CFG_CS3_WS)
284
285 MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
286
287 #if (CFG_CS3_WIDTH == 8)
288 #define CFG_CS3_PS MCFCSM_CSCR_PS_8
289 #elif (CFG_CS3_WIDTH == 16)
290 #define CFG_CS3_PS MCFCSM_CSCR_PS_16
291 #elif (CFG_CS3_WIDTH == 32)
292 #define CFG_CS3_PS MCFCSM_CSCR_PS_32
293 #else
294 #error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
295 #endif
296 MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
297 |CFG_CS3_PS
298 |MCFCSM_CSCR_AA;
299
300 #if (CFG_CS3_RO != 0)
301 MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
302 |MCFCSM_CSMR_WP
303 |MCFCSM_CSMR_V;
304 #else
305 MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
306 |MCFCSM_CSMR_V;
307 #endif
308#else
309 #warning "Chip Select 3 are not initialized/used"
310#endif
311
312#endif /* CONFIG_MONITOR_IS_IN_RAM */
bf9e3b38 313
9acb626f
HS		 314 /* defer enabling cache until boot (see do_go) */
315 /* icache_enable(); */
bf9e3b38
WD		 316}
317
318/*
319 * initialize higher level parts of CPU like timers
320 */
321int cpu_init_r (void)
322{
323 return (0);
324}
325#endif
8c725b93
SR		 326
327#if defined(CONFIG_M5249)
328/*
329 * Breath some life into the CPU...
330 *
331 * Set up the memory map,
332 * initialize a bunch of registers,
333 * initialize the UPM's
334 */
335void cpu_init_f (void)
336{
337#ifndef CFG_PLL_BYPASS
338 /*
339 * Setup the PLL to run at the specified speed
340 *
341 */
342 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
343 unsigned long pllcr;
344#ifdef CFG_FAST_CLK
345 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
346#else
347 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
348#endif
349 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
350 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
351 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
352 pllcr ^= 0x00000001; /* Set pll bypass to 1 */
353 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
354 udelay(0x20); /* Wait for a lock ... */
355#endif /* #ifndef CFG_PLL_BYPASS */
356
357 /*
358 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
359 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
360 * which is their primary function.
361 * ~Jeremy
362 */
363 mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
364 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
365 mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN);
366 mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN);
367 mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT);
368 mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT);
369
370 /*
371 * dBug Compliance:
372 * You can verify these values by using dBug's 'ird'
373 * (Internal Register Display) command
374 * ~Jeremy
375 *
376 */
377 mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
378 mbar_writeByte(MCFSIM_SYPCR, 0x00);
379 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
380 mbar_writeByte(MCFSIM_SWSR, 0x00);
381 mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
382 mbar_writeByte(MCFSIM_SWDICR, 0x00);
383 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
384 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
385 mbar_writeByte(MCFSIM_I2CICR, 0x00);
386 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
387 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
388 mbar_writeByte(MCFSIM_ICR6, 0x00);
389 mbar_writeByte(MCFSIM_ICR7, 0x00);
390 mbar_writeByte(MCFSIM_ICR8, 0x00);
391 mbar_writeByte(MCFSIM_ICR9, 0x00);
392 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
393
394 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
395 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
396 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
397 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
398
399 /* Setup interrupt priorities for gpio7 */
400 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
401
402 /* IDE Config registers */
403 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
404 mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
405
406 /*
407 * Setup chip selects...
408 */
409
410 mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
411 mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
412 mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
413
414 mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
415 mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
416 mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
417
418 /* enable instruction cache now */
419 icache_enable();
420}
421
422/*
423 * initialize higher level parts of CPU like timers
424 */
425int cpu_init_r (void)
426{
427 return (0);
428}
429#endif /* #if defined(CONFIG_M5249) */
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