[people/ms/u-boot.git] / cpu / mcf52x2 / cpu_init.c

/*
 * (C) Copyright 2003
 * Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * MCF5282 additionals
 * (C) Copyright 2005
 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>

#ifdef	CONFIG_M5271
#include <asm/m5271.h>
#include <asm/immap_5271.h>
#endif

#ifdef	CONFIG_M5272
#include <asm/m5272.h>
#include <asm/immap_5272.h>
#endif

#ifdef	CONFIG_M5282
#include <asm/m5282.h>
#include <asm/immap_5282.h>
#endif

#ifdef	CONFIG_M5249
#include <asm/m5249.h>
#endif

#if defined(CONFIG_M5271)
void cpu_init_f (void)
{
#ifndef CONFIG_WATCHDOG
	/* Disable the watchdog if we aren't using it */
	mbar_writeShort(MCF_WTM_WCR, 0);
#endif

	/* Set clockspeed to 100MHz */
	mbar_writeShort(MCF_FMPLL_SYNCR,
			MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
	while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK);

	/* Enable UART pins */
	mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
			MCF_GPIO_PAR_UART_U0RXD |
			MCF_GPIO_PAR_UART_U1RXD_UART1 |
			MCF_GPIO_PAR_UART_U1TXD_UART1);

	/* Enable Ethernet pins */
	mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r	(void)
{
	return (0);
}
#endif

#if defined(CONFIG_M5272)
/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f (void)
{
	/* if we come from RAM we assume the CPU is
	 * already initialized.
	 */
#ifndef CONFIG_MONITOR_IS_IN_RAM
	volatile immap_t *regp = (immap_t *)CFG_MBAR;

	volatile unsigned char	*mbar;
	mbar = (volatile unsigned char *) CFG_MBAR;

	regp->sysctrl_reg.sc_scr = CFG_SCR;
	regp->sysctrl_reg.sc_spr = CFG_SPR;

	/* Setup Ports: */
	regp->gpio_reg.gpio_pacnt = CFG_PACNT;
	regp->gpio_reg.gpio_paddr = CFG_PADDR;
	regp->gpio_reg.gpio_padat = CFG_PADAT;
	regp->gpio_reg.gpio_pbcnt = CFG_PBCNT;
	regp->gpio_reg.gpio_pbddr = CFG_PBDDR;
	regp->gpio_reg.gpio_pbdat = CFG_PBDAT;
	regp->gpio_reg.gpio_pdcnt = CFG_PDCNT;

	/* Memory Controller: */
	regp->csctrl_reg.cs_br0 = CFG_BR0_PRELIM;
	regp->csctrl_reg.cs_or0 = CFG_OR0_PRELIM;

#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
	regp->csctrl_reg.cs_br1 = CFG_BR1_PRELIM;
	regp->csctrl_reg.cs_or1 = CFG_OR1_PRELIM;
#endif

#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
	regp->csctrl_reg.cs_br2 = CFG_BR2_PRELIM;
	regp->csctrl_reg.cs_or2 = CFG_OR2_PRELIM;
#endif

#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
	regp->csctrl_reg.cs_br3 = CFG_BR3_PRELIM;
	regp->csctrl_reg.cs_or3 = CFG_OR3_PRELIM;
#endif

#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
	regp->csctrl_reg.cs_br4 = CFG_BR4_PRELIM;
	regp->csctrl_reg.cs_or4 = CFG_OR4_PRELIM;
#endif

#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
	regp->csctrl_reg.cs_br5 = CFG_BR5_PRELIM;
	regp->csctrl_reg.cs_or5 = CFG_OR5_PRELIM;
#endif

#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
	regp->csctrl_reg.cs_br6 = CFG_BR6_PRELIM;
	regp->csctrl_reg.cs_or6 = CFG_OR6_PRELIM;
#endif

#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
	regp->csctrl_reg.cs_br7 = CFG_BR7_PRELIM;
	regp->csctrl_reg.cs_or7 = CFG_OR7_PRELIM;
#endif

#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */

	/* enable instruction cache now */
	icache_enable();

}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r	(void)
{
	return (0);
}
#endif /* #if defined(CONFIG_M5272) */


#ifdef	CONFIG_M5282
/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f (void)
{
#ifndef CONFIG_WATCHDOG
	/* disable watchdog if we aren't using it */
	MCFWTM_WCR = 0;
#endif

#ifndef CONFIG_MONITOR_IS_IN_RAM
	/* Set speed /PLL */
	MCFCLOCK_SYNCR =  MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);

	/* Set up the GPIO ports */
#ifdef CFG_PEPAR
	MCFGPIO_PEPAR = CFG_PEPAR;
#endif
#ifdef	CFG_PFPAR
	MCFGPIO_PFPAR = CFG_PFPAR;
#endif
#ifdef CFG_PJPAR
	MCFGPIO_PJPAR = CFG_PJPAR;
#endif
#ifdef CFG_PSDPAR
	MCFGPIO_PSDPAR = CFG_PSDPAR;
#endif
#ifdef CFG_PASPAR
	MCFGPIO_PASPAR = CFG_PASPAR;
#endif
#ifdef CFG_PEHLPAR
	MCFGPIO_PEHLPAR = CFG_PEHLPAR;
#endif
#ifdef CFG_PQSPAR
	MCFGPIO_PQSPAR = CFG_PQSPAR;
#endif
#ifdef CFG_PTCPAR
	MCFGPIO_PTCPAR = CFG_PTCPAR;
#endif
#ifdef CFG_PTDPAR
	MCFGPIO_PTDPAR = CFG_PTDPAR;
#endif
#ifdef CFG_PUAPAR
	MCFGPIO_PUAPAR = CFG_PUAPAR;
#endif

#ifdef CFG_DDRUA
	MCFGPIO_DDRUA = CFG_DDRUA;
#endif

	/* This is probably a bad place to setup chip selects, but everyone
	   else is doing it! */

#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
    defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
	defined(CFG_CS0_WS)

	MCFCSM_CSAR0 =	(CFG_CS0_BASE >> 16) & 0xFFFF;

	#if (CFG_CS0_WIDTH == 8)
		#define	 CFG_CS0_PS  MCFCSM_CSCR_PS_8
	#elif (CFG_CS0_WIDTH == 16)
		#define	 CFG_CS0_PS  MCFCSM_CSCR_PS_16
	#elif (CFG_CS0_WIDTH == 32)
		#define	 CFG_CS0_PS  MCFCSM_CSCR_PS_32
	#else
		#error	"CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
	#endif
	MCFCSM_CSCR0 =	MCFCSM_CSCR_WS(CFG_CS0_WS)
			|CFG_CS0_PS
			|MCFCSM_CSCR_AA;

	#if (CFG_CS0_RO != 0)
		MCFCSM_CSMR0 =	MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)
				|MCFCSM_CSMR_WP|MCFCSM_CSMR_V;
 	#else
		MCFCSM_CSMR0 =	MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)|MCFCSM_CSMR_V;
	#endif
#else
	#waring "Chip Select 0 are not initialized/used"
#endif

#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
    defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \
	defined(CFG_CS1_WS)

	MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;

	#if (CFG_CS1_WIDTH == 8)
		#define	 CFG_CS1_PS  MCFCSM_CSCR_PS_8
	#elif (CFG_CS1_WIDTH == 16)
		#define	 CFG_CS1_PS  MCFCSM_CSCR_PS_16
	#elif (CFG_CS1_WIDTH == 32)
		#define	 CFG_CS1_PS  MCFCSM_CSCR_PS_32
	#else
		#error	"CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
	#endif
	MCFCSM_CSCR1 =	MCFCSM_CSCR_WS(CFG_CS1_WS)
			|CFG_CS1_PS
			|MCFCSM_CSCR_AA;

	#if (CFG_CS1_RO != 0)
		MCFCSM_CSMR1 =	MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
				|MCFCSM_CSMR_WP
				|MCFCSM_CSMR_V;
 	#else
		MCFCSM_CSMR1 =	MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
				|MCFCSM_CSMR_V;
	#endif
#else
	#warning "Chip Select 1 are not initialized/used"
#endif

#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
    defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \
	defined(CFG_CS2_WS)

	MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;

	#if (CFG_CS2_WIDTH == 8)
		#define	 CFG_CS2_PS  MCFCSM_CSCR_PS_8
	#elif (CFG_CS2_WIDTH == 16)
		#define	 CFG_CS2_PS  MCFCSM_CSCR_PS_16
	#elif (CFG_CS2_WIDTH == 32)
		#define	 CFG_CS2_PS  MCFCSM_CSCR_PS_32
	#else
		#error	"CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
	#endif
	MCFCSM_CSCR2 =	MCFCSM_CSCR_WS(CFG_CS2_WS)
			|CFG_CS2_PS
			|MCFCSM_CSCR_AA;

	#if (CFG_CS2_RO != 0)
		MCFCSM_CSMR2 =	MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
				|MCFCSM_CSMR_WP
				|MCFCSM_CSMR_V;
 	#else
		MCFCSM_CSMR2 =	MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
				|MCFCSM_CSMR_V;
	#endif
#else
	#warning "Chip Select 2 are not initialized/used"
#endif

#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
    defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \
	defined(CFG_CS3_WS)

	MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;

	#if (CFG_CS3_WIDTH == 8)
		#define	 CFG_CS3_PS  MCFCSM_CSCR_PS_8
	#elif (CFG_CS3_WIDTH == 16)
		#define	 CFG_CS3_PS  MCFCSM_CSCR_PS_16
	#elif (CFG_CS3_WIDTH == 32)
		#define	 CFG_CS3_PS  MCFCSM_CSCR_PS_32
	#else
		#error	"CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
	#endif
	MCFCSM_CSCR3 =	MCFCSM_CSCR_WS(CFG_CS3_WS)
			|CFG_CS3_PS
			|MCFCSM_CSCR_AA;

	#if (CFG_CS3_RO != 0)
		MCFCSM_CSMR3 =	MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
				|MCFCSM_CSMR_WP
				|MCFCSM_CSMR_V;
 	#else
		MCFCSM_CSMR3 =	MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
				|MCFCSM_CSMR_V;
	#endif
#else
	#warning "Chip Select 3 are not initialized/used"
#endif

#endif /* CONFIG_MONITOR_IS_IN_RAM */

	/* defer enabling cache until boot (see do_go) */
	/* icache_enable(); */
}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r	(void)
{
	return (0);
}
#endif

#if defined(CONFIG_M5249)
/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f (void)
{
#ifndef CFG_PLL_BYPASS
	/*
	 *  Setup the PLL to run at the specified speed
	 *
	 */
	volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
	unsigned long pllcr;
#ifdef CFG_FAST_CLK
	pllcr = 0x925a3100;			  /* ~140MHz clock (PLL bypass = 0) */
#else
	pllcr = 0x135a4140;			  /* ~72MHz clock (PLL bypass = 0) */
#endif
	cpll = cpll & 0xfffffffe;		  /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
	mbar2_writeLong(MCFSIM_PLLCR, cpll);	  /* Set the PLL to bypass mode (PSTCLK = crystal) */
	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	  /* set the clock speed */
	pllcr ^= 0x00000001;			  /* Set pll bypass to 1 */
	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	  /* Start locking (pll bypass = 1) */
	udelay(0x20);				  /* Wait for a lock ... */
#endif /* #ifndef CFG_PLL_BYPASS */

	/*
	 *  NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
	 *	  (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
	 *	  which is their primary function.
	 *	  ~Jeremy
	 */
	mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
	mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
	mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN);
	mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN);
	mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT);
	mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT);

	/*
	 *  dBug Compliance:
	 *    You can verify these values by using dBug's 'ird'
	 *    (Internal Register Display) command
	 *    ~Jeremy
	 *
	 */
	mbar_writeByte(MCFSIM_MPARK, 0x30);    /* 5249 Internal Core takes priority over DMA */
	mbar_writeByte(MCFSIM_SYPCR, 0x00);
	mbar_writeByte(MCFSIM_SWIVR, 0x0f);
	mbar_writeByte(MCFSIM_SWSR, 0x00);
	mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
	mbar_writeByte(MCFSIM_SWDICR, 0x00);
	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
	mbar_writeByte(MCFSIM_I2CICR, 0x00);
	mbar_writeByte(MCFSIM_UART1ICR, 0x00);
	mbar_writeByte(MCFSIM_UART2ICR, 0x00);
	mbar_writeByte(MCFSIM_ICR6, 0x00);
	mbar_writeByte(MCFSIM_ICR7, 0x00);
	mbar_writeByte(MCFSIM_ICR8, 0x00);
	mbar_writeByte(MCFSIM_ICR9, 0x00);
	mbar_writeByte(MCFSIM_QSPIICR, 0x00);

	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
	mbar2_writeByte(MCFSIM_INTBASE, 0x40);	/* Base interrupts at 64 */
	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);	 /* Enable a 1 cycle pre-drive cycle on CS1 */

	/* Setup interrupt priorities for gpio7 */
	/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */

	/* IDE Config registers */
	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
	mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);

	/*
	 *  Setup chip selects...
	 */

	mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
	mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
	mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);

	mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
	mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
	mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);

	/* enable instruction cache now */
	icache_enable();
}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r	(void)
{
	return (0);
}
#endif /* #if defined(CONFIG_M5249) */
Commit	Line	Data
bf9e3b38 WD	1	/*
	2	* (C) Copyright 2003
	3	* Josef Baumgartner <josef.baumgartner@telex.de>
	4	*
9acb626f HS	5	* MCF5282 additionals
	6	* (C) Copyright 2005
	7	* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
	8	*
bf9e3b38 WD	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
977b50f8	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
bf9e3b38 WD	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <common.h>
	29	#include <watchdog.h>
	30
eacbd317 ZL	31	#ifdef CONFIG_M5271
	32	#include <asm/m5271.h>
	33	#include <asm/immap_5271.h>
	34	#endif
	35
bf9e3b38 WD	36	#ifdef CONFIG_M5272
	37	#include <asm/m5272.h>
	38	#include <asm/immap_5272.h>
	39	#endif
	40
	41	#ifdef CONFIG_M5282
	42	#include <asm/m5282.h>
	43	#include <asm/immap_5282.h>
	44	#endif
	45
8c725b93 SR	46	#ifdef CONFIG_M5249
	47	#include <asm/m5249.h>
	48	#endif
	49
eacbd317 ZL	50	#if defined(CONFIG_M5271)
	51	void cpu_init_f (void)
	52	{
	53	#ifndef CONFIG_WATCHDOG
	54	/* Disable the watchdog if we aren't using it */
	55	mbar_writeShort(MCF_WTM_WCR, 0);
	56	#endif
	57
	58	/* Set clockspeed to 100MHz */
	59	mbar_writeShort(MCF_FMPLL_SYNCR,
	60	MCF_FMPLL_SYNCR_MFD(0) \| MCF_FMPLL_SYNCR_RFD(0));
	61	while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK);
	62
	63	/* Enable UART pins */
	64	mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD \|
977b50f8 WD	65	MCF_GPIO_PAR_UART_U0RXD \|
	66	MCF_GPIO_PAR_UART_U1RXD_UART1 \|
	67	MCF_GPIO_PAR_UART_U1TXD_UART1);
eacbd317 ZL	68
	69	/* Enable Ethernet pins */
	70	mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
	71	}
	72
	73	/*
	74	* initialize higher level parts of CPU like timers
	75	*/
977b50f8	76	int cpu_init_r (void)
eacbd317 ZL	77	{
	78	return (0);
	79	}
	80	#endif
	81
8c725b93	82	#if defined(CONFIG_M5272)
bf9e3b38 WD	83	/*
	84	* Breath some life into the CPU...
	85	*
	86	* Set up the memory map,
	87	* initialize a bunch of registers,
	88	* initialize the UPM's
	89	*/
	90	void cpu_init_f (void)
	91	{
	92	/* if we come from RAM we assume the CPU is
	93	* already initialized.
	94	*/
	95	#ifndef CONFIG_MONITOR_IS_IN_RAM
	96	volatile immap_t regp = (immap_t )CFG_MBAR;
	97
	98	volatile unsigned char *mbar;
	99	mbar = (volatile unsigned char *) CFG_MBAR;
	100
	101	regp->sysctrl_reg.sc_scr = CFG_SCR;
	102	regp->sysctrl_reg.sc_spr = CFG_SPR;
	103
977b50f8	104	/* Setup Ports: */
bf9e3b38 WD	105	regp->gpio_reg.gpio_pacnt = CFG_PACNT;
	106	regp->gpio_reg.gpio_paddr = CFG_PADDR;
	107	regp->gpio_reg.gpio_padat = CFG_PADAT;
	108	regp->gpio_reg.gpio_pbcnt = CFG_PBCNT;
	109	regp->gpio_reg.gpio_pbddr = CFG_PBDDR;
	110	regp->gpio_reg.gpio_pbdat = CFG_PBDAT;
	111	regp->gpio_reg.gpio_pdcnt = CFG_PDCNT;
	112
	113	/* Memory Controller: */
	114	regp->csctrl_reg.cs_br0 = CFG_BR0_PRELIM;
	115	regp->csctrl_reg.cs_or0 = CFG_OR0_PRELIM;
	116
	117	#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
	118	regp->csctrl_reg.cs_br1 = CFG_BR1_PRELIM;
	119	regp->csctrl_reg.cs_or1 = CFG_OR1_PRELIM;
	120	#endif
	121
	122	#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
	123	regp->csctrl_reg.cs_br2 = CFG_BR2_PRELIM;
	124	regp->csctrl_reg.cs_or2 = CFG_OR2_PRELIM;
	125	#endif
	126
	127	#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
	128	regp->csctrl_reg.cs_br3 = CFG_BR3_PRELIM;
	129	regp->csctrl_reg.cs_or3 = CFG_OR3_PRELIM;
	130	#endif
	131
	132	#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
	133	regp->csctrl_reg.cs_br4 = CFG_BR4_PRELIM;
	134	regp->csctrl_reg.cs_or4 = CFG_OR4_PRELIM;
	135	#endif
	136
	137	#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
	138	regp->csctrl_reg.cs_br5 = CFG_BR5_PRELIM;
	139	regp->csctrl_reg.cs_or5 = CFG_OR5_PRELIM;
	140	#endif
	141
	142	#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
	143	regp->csctrl_reg.cs_br6 = CFG_BR6_PRELIM;
	144	regp->csctrl_reg.cs_or6 = CFG_OR6_PRELIM;
	145	#endif
	146
	147	#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
	148	regp->csctrl_reg.cs_br7 = CFG_BR7_PRELIM;
	149	regp->csctrl_reg.cs_or7 = CFG_OR7_PRELIM;
	150	#endif
	151
	152	#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
	153
977b50f8 WD	154	/* enable instruction cache now */
977b50f8 WD	155	icache_enable();
bf9e3b38 WD	156
	157	}
	158
	159	/*
	160	* initialize higher level parts of CPU like timers
	161	*/
977b50f8	162	int cpu_init_r (void)
bf9e3b38 WD	163	{
	164	return (0);
	165	}
8c725b93	166	#endif /* #if defined(CONFIG_M5272) */
bf9e3b38 WD	167
	168
	169	#ifdef CONFIG_M5282
	170	/*
	171	* Breath some life into the CPU...
	172	*
	173	* Set up the memory map,
	174	* initialize a bunch of registers,
	175	* initialize the UPM's
	176	*/
	177	void cpu_init_f (void)
	178	{
9acb626f HS	179	#ifndef CONFIG_WATCHDOG
	180	/* disable watchdog if we aren't using it */
	181	MCFWTM_WCR = 0;
	182	#endif
	183
	184	#ifndef CONFIG_MONITOR_IS_IN_RAM
	185	/* Set speed /PLL */
	186	MCFCLOCK_SYNCR = MCFCLOCK_SYNCR_MFD(CFG_MFD) \| MCFCLOCK_SYNCR_RFD(CFG_RFD);
	187
	188	/* Set up the GPIO ports */
	189	#ifdef CFG_PEPAR
	190	MCFGPIO_PEPAR = CFG_PEPAR;
	191	#endif
	192	#ifdef CFG_PFPAR
	193	MCFGPIO_PFPAR = CFG_PFPAR;
	194	#endif
	195	#ifdef CFG_PJPAR
	196	MCFGPIO_PJPAR = CFG_PJPAR;
	197	#endif
	198	#ifdef CFG_PSDPAR
	199	MCFGPIO_PSDPAR = CFG_PSDPAR;
	200	#endif
	201	#ifdef CFG_PASPAR
	202	MCFGPIO_PASPAR = CFG_PASPAR;
	203	#endif
	204	#ifdef CFG_PEHLPAR
	205	MCFGPIO_PEHLPAR = CFG_PEHLPAR;
	206	#endif
	207	#ifdef CFG_PQSPAR
	208	MCFGPIO_PQSPAR = CFG_PQSPAR;
	209	#endif
	210	#ifdef CFG_PTCPAR
	211	MCFGPIO_PTCPAR = CFG_PTCPAR;
	212	#endif
	213	#ifdef CFG_PTDPAR
	214	MCFGPIO_PTDPAR = CFG_PTDPAR;
	215	#endif
	216	#ifdef CFG_PUAPAR
	217	MCFGPIO_PUAPAR = CFG_PUAPAR;
	218	#endif
	219
	220	#ifdef CFG_DDRUA
	221	MCFGPIO_DDRUA = CFG_DDRUA;
	222	#endif
	223
	224	/* This is probably a bad place to setup chip selects, but everyone
	225	else is doing it! */
	226
	227	#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
	228	defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
	229	defined(CFG_CS0_WS)
	230
	231	MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
	232
	233	#if (CFG_CS0_WIDTH == 8)
	234	#define CFG_CS0_PS MCFCSM_CSCR_PS_8
	235	#elif (CFG_CS0_WIDTH == 16)
	236	#define CFG_CS0_PS MCFCSM_CSCR_PS_16
	237	#elif (CFG_CS0_WIDTH == 32)
	238	#define CFG_CS0_PS MCFCSM_CSCR_PS_32
	239	#else
	240	#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
	241	#endif
	242	MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
243	\|CFG_CS0_PS
244	\|MCFCSM_CSCR_AA;
245
246	#if (CFG_CS0_RO != 0)
247	MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)
248	\|MCFCSM_CSMR_WP\|MCFCSM_CSMR_V;
249	#else
250	MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)\|MCFCSM_CSMR_V;
251	#endif
252	#else
253	#waring "Chip Select 0 are not initialized/used"
254	#endif
255
256	#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
257	defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \
258	defined(CFG_CS1_WS)
259
260	MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
261
262	#if (CFG_CS1_WIDTH == 8)
263	#define CFG_CS1_PS MCFCSM_CSCR_PS_8
264	#elif (CFG_CS1_WIDTH == 16)
265	#define CFG_CS1_PS MCFCSM_CSCR_PS_16
266	#elif (CFG_CS1_WIDTH == 32)
267	#define CFG_CS1_PS MCFCSM_CSCR_PS_32
268	#else
269	#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
270	#endif
271	MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
272	\|CFG_CS1_PS
273	\|MCFCSM_CSCR_AA;
274
275	#if (CFG_CS1_RO != 0)
276	MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
277	\|MCFCSM_CSMR_WP
278	\|MCFCSM_CSMR_V;
279	#else
280	MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
281	\|MCFCSM_CSMR_V;
282	#endif
283	#else
284	#warning "Chip Select 1 are not initialized/used"
285	#endif
286
287	#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
288	defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \
289	defined(CFG_CS2_WS)
290
291	MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
292
293	#if (CFG_CS2_WIDTH == 8)
294	#define CFG_CS2_PS MCFCSM_CSCR_PS_8
295	#elif (CFG_CS2_WIDTH == 16)
296	#define CFG_CS2_PS MCFCSM_CSCR_PS_16
297	#elif (CFG_CS2_WIDTH == 32)
298	#define CFG_CS2_PS MCFCSM_CSCR_PS_32
299	#else
300	#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
301	#endif
302	MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
303	\|CFG_CS2_PS
304	\|MCFCSM_CSCR_AA;
305
306	#if (CFG_CS2_RO != 0)
307	MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
308	\|MCFCSM_CSMR_WP
309	\|MCFCSM_CSMR_V;
310	#else
311	MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
312	\|MCFCSM_CSMR_V;
313	#endif
314	#else
315	#warning "Chip Select 2 are not initialized/used"
316	#endif
317
318	#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
319	defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \
320	defined(CFG_CS3_WS)
321
322	MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
323
324	#if (CFG_CS3_WIDTH == 8)
325	#define CFG_CS3_PS MCFCSM_CSCR_PS_8
326	#elif (CFG_CS3_WIDTH == 16)
327	#define CFG_CS3_PS MCFCSM_CSCR_PS_16
328	#elif (CFG_CS3_WIDTH == 32)
329	#define CFG_CS3_PS MCFCSM_CSCR_PS_32
330	#else
331	#error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
332	#endif
333	MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
334	\|CFG_CS3_PS
335	\|MCFCSM_CSCR_AA;
336
337	#if (CFG_CS3_RO != 0)
338	MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
339	\|MCFCSM_CSMR_WP
340	\|MCFCSM_CSMR_V;
341	#else
342	MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
343	\|MCFCSM_CSMR_V;
344	#endif
345	#else
346	#warning "Chip Select 3 are not initialized/used"
347	#endif
348
349	#endif /* CONFIG_MONITOR_IS_IN_RAM */
bf9e3b38	350
9acb626f HS	351	/* defer enabling cache until boot (see do_go) */
9acb626f HS	352	/* icache_enable(); */
bf9e3b38 WD	353	}
	354
	355	/*
	356	* initialize higher level parts of CPU like timers
	357	*/
977b50f8	358	int cpu_init_r (void)
bf9e3b38 WD	359	{
	360	return (0);
	361	}
	362	#endif
8c725b93 SR	363
	364	#if defined(CONFIG_M5249)
	365	/*
	366	* Breath some life into the CPU...
	367	*
	368	* Set up the memory map,
	369	* initialize a bunch of registers,
	370	* initialize the UPM's
	371	*/
	372	void cpu_init_f (void)
	373	{
	374	#ifndef CFG_PLL_BYPASS
	375	/*
	376	* Setup the PLL to run at the specified speed
	377	*
	378	*/
	379	volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
	380	unsigned long pllcr;
	381	#ifdef CFG_FAST_CLK
977b50f8	382	pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
8c725b93	383	#else
977b50f8	384	pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
8c725b93	385	#endif
977b50f8 WD	386	cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
	387	mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
	388	mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
	389	pllcr ^= 0x00000001; /* Set pll bypass to 1 */
	390	mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
	391	udelay(0x20); /* Wait for a lock ... */
8c725b93 SR	392	#endif /* #ifndef CFG_PLL_BYPASS */
	393
	394	/*
	395	* NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
977b50f8 WD	396	* (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
	397	* which is their primary function.
	398	* ~Jeremy
8c725b93 SR	399	*/
	400	mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
	401	mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
	402	mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN);
	403	mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN);
	404	mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT);
	405	mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT);
	406
	407	/*
	408	* dBug Compliance:
	409	* You can verify these values by using dBug's 'ird'
	410	* (Internal Register Display) command
	411	* ~Jeremy
	412	*
977b50f8	413	*/
8c725b93 SR	414	mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
	415	mbar_writeByte(MCFSIM_SYPCR, 0x00);
	416	mbar_writeByte(MCFSIM_SWIVR, 0x0f);
	417	mbar_writeByte(MCFSIM_SWSR, 0x00);
	418	mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
	419	mbar_writeByte(MCFSIM_SWDICR, 0x00);
	420	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
	421	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
	422	mbar_writeByte(MCFSIM_I2CICR, 0x00);
	423	mbar_writeByte(MCFSIM_UART1ICR, 0x00);
	424	mbar_writeByte(MCFSIM_UART2ICR, 0x00);
	425	mbar_writeByte(MCFSIM_ICR6, 0x00);
	426	mbar_writeByte(MCFSIM_ICR7, 0x00);
	427	mbar_writeByte(MCFSIM_ICR8, 0x00);
	428	mbar_writeByte(MCFSIM_ICR9, 0x00);
	429	mbar_writeByte(MCFSIM_QSPIICR, 0x00);
	430
	431	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
977b50f8	432	mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
8c725b93	433	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
977b50f8	434	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
8c725b93 SR	435
	436	/* Setup interrupt priorities for gpio7 */
	437	/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
	438
	439	/* IDE Config registers */
	440	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
	441	mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
	442
	443	/*
	444	* Setup chip selects...
	445	*/
	446
	447	mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
	448	mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
	449	mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
	450
	451	mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
	452	mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
	453	mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
	454
	455	/* enable instruction cache now */
	456	icache_enable();
	457	}
	458
	459	/*
	460	* initialize higher level parts of CPU like timers
	461	*/
977b50f8	462	int cpu_init_r (void)
8c725b93 SR	463	{
	464	return (0);
	465	}
	466	#endif /* #if defined(CONFIG_M5249) */