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4e5ca3eb | 1 | /* |
bf9e3b38 WD |
2 | * (C) Copyright 2003 |
3 | * Josef Baumgartner <josef.baumgartner@telex.de> | |
4e5ca3eb | 4 | * |
a1436a84 TL |
5 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
6 | * Hayden Fraser (Hayden.Fraser@freescale.com) | |
7 | * | |
4e5ca3eb WD |
8 | * See file CREDITS for list of people who contributed to this |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
28 | #include <asm/processor.h> | |
a1436a84 | 29 | #include <asm/immap.h> |
4e5ca3eb | 30 | |
d87080b7 WD |
31 | DECLARE_GLOBAL_DATA_PTR; |
32 | ||
bf9e3b38 WD |
33 | /* |
34 | * get_clocks() fills in gd->cpu_clock and gd->bus_clk | |
35 | */ | |
36 | int get_clocks (void) | |
4e5ca3eb | 37 | { |
a1436a84 TL |
38 | #if defined(CONFIG_M5249) || defined(CONFIG_M5253) |
39 | volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); | |
40 | unsigned long pllcr; | |
41 | ||
6d0f6bcf | 42 | #ifndef CONFIG_SYS_PLL_BYPASS |
a1436a84 | 43 | |
8c725b93 | 44 | #ifdef CONFIG_M5249 |
a1436a84 | 45 | /* Setup the PLL to run at the specified speed */ |
6d0f6bcf | 46 | #ifdef CONFIG_SYS_FAST_CLK |
a1436a84 TL |
47 | pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ |
48 | #else | |
49 | pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ | |
50 | #endif | |
51 | #endif /* CONFIG_M5249 */ | |
52 | ||
53 | #ifdef CONFIG_M5253 | |
6d0f6bcf | 54 | pllcr = CONFIG_SYS_PLLCR; |
a1436a84 TL |
55 | #endif /* CONFIG_M5253 */ |
56 | ||
57 | cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ | |
58 | mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ | |
59 | mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ | |
60 | pllcr ^= 0x00000001; /* Set pll bypass to 1 */ | |
61 | mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ | |
62 | udelay(0x20); /* Wait for a lock ... */ | |
6d0f6bcf | 63 | #endif /* #ifndef CONFIG_SYS_PLL_BYPASS */ |
a1436a84 TL |
64 | |
65 | #endif /* CONFIG_M5249 || CONFIG_M5253 */ | |
66 | ||
f71d9d91 MF |
67 | #if defined(CONFIG_M5275) |
68 | volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); | |
69 | ||
1aeed8d7 WD |
70 | /* Setup PLL */ |
71 | pll->syncr = 0x01080000; | |
dd08e973 | 72 | while (!(pll->synsr & FMPLL_SYNSR_LOCK)) |
1aeed8d7 WD |
73 | ; |
74 | pll->syncr = 0x01000000; | |
75 | while (!(pll->synsr & FMPLL_SYNSR_LOCK)) | |
76 | ; | |
f71d9d91 MF |
77 | #endif |
78 | ||
6d0f6bcf | 79 | gd->cpu_clk = CONFIG_SYS_CLK; |
f71d9d91 | 80 | #if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275) |
8c725b93 SR |
81 | gd->bus_clk = gd->cpu_clk / 2; |
82 | #else | |
bf9e3b38 | 83 | gd->bus_clk = gd->cpu_clk; |
8c725b93 | 84 | #endif |
eec567a6 TL |
85 | |
86 | #ifdef CONFIG_FSL_I2C | |
87 | gd->i2c1_clk = gd->bus_clk; | |
6d0f6bcf | 88 | #ifdef CONFIG_SYS_I2C2_OFFSET |
eec567a6 TL |
89 | gd->i2c2_clk = gd->bus_clk; |
90 | #endif | |
91 | #endif | |
92 | ||
bf9e3b38 | 93 | return (0); |
4e5ca3eb | 94 | } |