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8993e54b | 1 | /* |
843efb11 | 2 | * (C) Copyright 2003 - 2009 |
8993e54b RJ |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | * | |
23 | * Based on the MPC5xxx code. | |
24 | */ | |
25 | ||
26 | #include <common.h> | |
843efb11 | 27 | #include <asm/io.h> |
8993e54b RJ |
28 | |
29 | DECLARE_GLOBAL_DATA_PTR; | |
30 | ||
31 | #ifdef CONFIG_HARD_I2C | |
32 | ||
8993e54b RJ |
33 | #include <i2c.h> |
34 | ||
8993e54b | 35 | /* by default set I2C bus 0 active */ |
c60dc852 | 36 | static unsigned int bus_num __attribute__ ((section (".data"))) = 0; |
8993e54b RJ |
37 | |
38 | #define I2C_TIMEOUT 100 | |
39 | #define I2C_RETRIES 3 | |
40 | ||
41 | struct mpc512x_i2c_tap { | |
42 | int scl2tap; | |
43 | int tap2tap; | |
44 | }; | |
45 | ||
46 | static int mpc_reg_in(volatile u32 *reg); | |
47 | static void mpc_reg_out(volatile u32 *reg, int val, int mask); | |
48 | static int wait_for_bb(void); | |
49 | static int wait_for_pin(int *status); | |
50 | static int do_address(uchar chip, char rdwr_flag); | |
51 | static int send_bytes(uchar chip, char *buf, int len); | |
52 | static int receive_bytes(uchar chip, char *buf, int len); | |
53 | static int mpc_get_fdr(int); | |
54 | ||
55 | static int mpc_reg_in (volatile u32 *reg) | |
56 | { | |
843efb11 WD |
57 | int ret = in_be32(reg) >> 24; |
58 | ||
8993e54b RJ |
59 | return ret; |
60 | } | |
61 | ||
62 | static void mpc_reg_out (volatile u32 *reg, int val, int mask) | |
63 | { | |
8993e54b | 64 | if (!mask) { |
843efb11 | 65 | out_be32(reg, val << 24); |
8993e54b | 66 | } else { |
843efb11 | 67 | clrsetbits_be32(reg, mask << 24, (val & mask) << 24); |
8993e54b | 68 | } |
8993e54b RJ |
69 | } |
70 | ||
71 | static int wait_for_bb (void) | |
72 | { | |
843efb11 WD |
73 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
74 | volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; | |
8993e54b RJ |
75 | int timeout = I2C_TIMEOUT; |
76 | int status; | |
77 | ||
78 | status = mpc_reg_in (®s->msr); | |
79 | ||
80 | while (timeout-- && (status & I2C_BB)) { | |
81 | volatile int temp; | |
82 | mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); | |
83 | temp = mpc_reg_in (®s->mdr); | |
84 | mpc_reg_out (®s->mcr, 0, I2C_STA); | |
85 | mpc_reg_out (®s->mcr, 0, 0); | |
86 | mpc_reg_out (®s->mcr, I2C_EN, 0); | |
87 | ||
88 | udelay (1000); | |
89 | status = mpc_reg_in (®s->msr); | |
90 | } | |
91 | ||
92 | return (status & I2C_BB); | |
93 | } | |
94 | ||
95 | static int wait_for_pin (int *status) | |
96 | { | |
843efb11 WD |
97 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
98 | volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; | |
8993e54b RJ |
99 | int timeout = I2C_TIMEOUT; |
100 | ||
101 | *status = mpc_reg_in (®s->msr); | |
102 | ||
103 | while (timeout-- && !(*status & I2C_IF)) { | |
104 | udelay (1000); | |
105 | *status = mpc_reg_in (®s->msr); | |
106 | } | |
107 | ||
108 | if (!(*status & I2C_IF)) { | |
109 | return -1; | |
110 | } | |
111 | ||
112 | mpc_reg_out (®s->msr, 0, I2C_IF); | |
113 | ||
114 | return 0; | |
115 | } | |
116 | ||
117 | static int do_address (uchar chip, char rdwr_flag) | |
118 | { | |
843efb11 WD |
119 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
120 | volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; | |
8993e54b RJ |
121 | int status; |
122 | ||
123 | chip <<= 1; | |
124 | ||
125 | if (rdwr_flag) { | |
126 | chip |= 1; | |
127 | } | |
128 | ||
129 | mpc_reg_out (®s->mcr, I2C_TX, I2C_TX); | |
130 | mpc_reg_out (®s->mdr, chip, 0); | |
131 | ||
132 | if (wait_for_pin (&status)) { | |
133 | return -2; | |
134 | } | |
135 | ||
136 | if (status & I2C_RXAK) { | |
137 | return -3; | |
138 | } | |
139 | ||
140 | return 0; | |
141 | } | |
142 | ||
143 | static int send_bytes (uchar chip, char *buf, int len) | |
144 | { | |
843efb11 WD |
145 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
146 | volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; | |
8993e54b RJ |
147 | int wrcount; |
148 | int status; | |
149 | ||
150 | for (wrcount = 0; wrcount < len; ++wrcount) { | |
151 | ||
152 | mpc_reg_out (®s->mdr, buf[wrcount], 0); | |
153 | ||
154 | if (wait_for_pin (&status)) { | |
155 | break; | |
156 | } | |
157 | ||
158 | if (status & I2C_RXAK) { | |
159 | break; | |
160 | } | |
161 | ||
162 | } | |
163 | ||
164 | return !(wrcount == len); | |
165 | } | |
166 | ||
167 | static int receive_bytes (uchar chip, char *buf, int len) | |
168 | { | |
843efb11 WD |
169 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
170 | volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; | |
8993e54b RJ |
171 | int dummy = 1; |
172 | int rdcount = 0; | |
173 | int status; | |
174 | int i; | |
175 | ||
176 | mpc_reg_out (®s->mcr, 0, I2C_TX); | |
177 | ||
178 | for (i = 0; i < len; ++i) { | |
179 | buf[rdcount] = mpc_reg_in (®s->mdr); | |
180 | ||
181 | if (dummy) { | |
182 | dummy = 0; | |
183 | } else { | |
184 | rdcount++; | |
185 | } | |
186 | ||
187 | if (wait_for_pin (&status)) { | |
188 | return -4; | |
189 | } | |
190 | } | |
191 | ||
192 | mpc_reg_out (®s->mcr, I2C_TXAK, I2C_TXAK); | |
193 | buf[rdcount++] = mpc_reg_in (®s->mdr); | |
194 | ||
195 | if (wait_for_pin (&status)) { | |
196 | return -5; | |
197 | } | |
198 | ||
199 | mpc_reg_out (®s->mcr, 0, I2C_TXAK); | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | /**************** I2C API ****************/ | |
205 | ||
206 | void i2c_init (int speed, int saddr) | |
207 | { | |
843efb11 | 208 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
8993e54b | 209 | int i; |
843efb11 WD |
210 | |
211 | for (i = 0; i < I2C_BUS_CNT; i++){ | |
212 | volatile i2c512x_dev_t *regs = &im->i2c.dev[i]; | |
213 | ||
8993e54b RJ |
214 | mpc_reg_out (®s->mcr, 0, 0); |
215 | ||
216 | /* Set clock */ | |
217 | mpc_reg_out (®s->mfdr, mpc_get_fdr (speed), 0); | |
218 | mpc_reg_out (®s->madr, saddr << 1, 0); | |
219 | ||
220 | /* Enable module */ | |
221 | mpc_reg_out (®s->mcr, I2C_EN, I2C_INIT_MASK); | |
222 | mpc_reg_out (®s->msr, 0, I2C_IF); | |
223 | } | |
224 | ||
225 | /* Disable interrupts */ | |
843efb11 WD |
226 | out_be32(&im->i2c.icr, 0); |
227 | ||
8993e54b | 228 | /* Turn off filters */ |
843efb11 | 229 | out_be32(&im->i2c.mifr, 0); |
8993e54b RJ |
230 | } |
231 | ||
232 | static int mpc_get_fdr (int speed) | |
233 | { | |
234 | static int fdr = -1; | |
235 | ||
236 | if (fdr == -1) { | |
237 | ulong best_speed = 0; | |
238 | ulong divider; | |
5d49e0e1 | 239 | ulong ips, scl; |
8993e54b RJ |
240 | ulong bestmatch = 0xffffffffUL; |
241 | int best_i = 0, best_j = 0, i, j; | |
242 | int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8}; | |
243 | struct mpc512x_i2c_tap scltap[] = { | |
244 | {4, 1}, | |
245 | {4, 2}, | |
246 | {6, 4}, | |
247 | {6, 8}, | |
248 | {14, 16}, | |
249 | {30, 32}, | |
250 | {62, 64}, | |
251 | {126, 128} | |
252 | }; | |
253 | ||
5d49e0e1 | 254 | ips = gd->ips_clk; |
8993e54b RJ |
255 | for (i = 7; i >= 0; i--) { |
256 | for (j = 7; j >= 0; j--) { | |
257 | scl = 2 * (scltap[j].scl2tap + | |
258 | (SCL_Tap[i] - 1) * scltap[j].tap2tap | |
259 | + 2); | |
5d49e0e1 GB |
260 | if (ips <= speed*scl) { |
261 | if ((speed*scl - ips) < bestmatch) { | |
262 | bestmatch = speed*scl - ips; | |
8993e54b RJ |
263 | best_i = i; |
264 | best_j = j; | |
5d49e0e1 | 265 | best_speed = ips/scl; |
8993e54b RJ |
266 | } |
267 | } | |
268 | } | |
269 | } | |
270 | divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2); | |
271 | if (gd->flags & GD_FLG_RELOC) { | |
272 | fdr = divider; | |
273 | } else { | |
274 | debug("%ld kHz, \n", best_speed / 1000); | |
275 | return divider; | |
276 | } | |
277 | } | |
278 | ||
279 | return fdr; | |
280 | } | |
281 | ||
282 | int i2c_probe (uchar chip) | |
283 | { | |
843efb11 WD |
284 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
285 | volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; | |
8993e54b RJ |
286 | int i; |
287 | ||
288 | for (i = 0; i < I2C_RETRIES; i++) { | |
289 | mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); | |
290 | ||
291 | if (! do_address (chip, 0)) { | |
292 | mpc_reg_out (®s->mcr, 0, I2C_STA); | |
293 | udelay (500); | |
294 | break; | |
295 | } | |
296 | ||
297 | mpc_reg_out (®s->mcr, 0, I2C_STA); | |
298 | udelay (500); | |
299 | } | |
300 | ||
301 | return (i == I2C_RETRIES); | |
302 | } | |
303 | ||
304 | int i2c_read (uchar chip, uint addr, int alen, uchar *buf, int len) | |
305 | { | |
843efb11 WD |
306 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
307 | volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; | |
8993e54b | 308 | char xaddr[4]; |
8993e54b RJ |
309 | int ret = -1; |
310 | ||
311 | xaddr[0] = (addr >> 24) & 0xFF; | |
312 | xaddr[1] = (addr >> 16) & 0xFF; | |
313 | xaddr[2] = (addr >> 8) & 0xFF; | |
314 | xaddr[3] = addr & 0xFF; | |
315 | ||
316 | if (wait_for_bb ()) { | |
317 | printf ("i2c_read: bus is busy\n"); | |
318 | goto Done; | |
319 | } | |
320 | ||
321 | mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); | |
322 | if (do_address (chip, 0)) { | |
323 | printf ("i2c_read: failed to address chip\n"); | |
324 | goto Done; | |
325 | } | |
326 | ||
327 | if (send_bytes (chip, &xaddr[4-alen], alen)) { | |
328 | printf ("i2c_read: send_bytes failed\n"); | |
329 | goto Done; | |
330 | } | |
331 | ||
332 | mpc_reg_out (®s->mcr, I2C_RSTA, I2C_RSTA); | |
333 | if (do_address (chip, 1)) { | |
334 | printf ("i2c_read: failed to address chip\n"); | |
335 | goto Done; | |
336 | } | |
337 | ||
338 | if (receive_bytes (chip, (char *)buf, len)) { | |
339 | printf ("i2c_read: receive_bytes failed\n"); | |
340 | goto Done; | |
341 | } | |
342 | ||
343 | ret = 0; | |
344 | Done: | |
345 | mpc_reg_out (®s->mcr, 0, I2C_STA); | |
346 | return ret; | |
347 | } | |
348 | ||
349 | int i2c_write (uchar chip, uint addr, int alen, uchar *buf, int len) | |
350 | { | |
843efb11 WD |
351 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
352 | volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num]; | |
8993e54b | 353 | char xaddr[4]; |
8993e54b RJ |
354 | int ret = -1; |
355 | ||
356 | xaddr[0] = (addr >> 24) & 0xFF; | |
357 | xaddr[1] = (addr >> 16) & 0xFF; | |
358 | xaddr[2] = (addr >> 8) & 0xFF; | |
359 | xaddr[3] = addr & 0xFF; | |
360 | ||
361 | if (wait_for_bb ()) { | |
362 | printf ("i2c_write: bus is busy\n"); | |
363 | goto Done; | |
364 | } | |
365 | ||
366 | mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); | |
367 | if (do_address (chip, 0)) { | |
368 | printf ("i2c_write: failed to address chip\n"); | |
369 | goto Done; | |
370 | } | |
371 | ||
372 | if (send_bytes (chip, &xaddr[4-alen], alen)) { | |
373 | printf ("i2c_write: send_bytes failed\n"); | |
374 | goto Done; | |
375 | } | |
376 | ||
377 | if (send_bytes (chip, (char *)buf, len)) { | |
378 | printf ("i2c_write: send_bytes failed\n"); | |
379 | goto Done; | |
380 | } | |
381 | ||
382 | ret = 0; | |
383 | Done: | |
384 | mpc_reg_out (®s->mcr, 0, I2C_STA); | |
385 | return ret; | |
386 | } | |
387 | ||
8993e54b RJ |
388 | int i2c_set_bus_num (unsigned int bus) |
389 | { | |
390 | if (bus >= I2C_BUS_CNT) { | |
391 | return -1; | |
392 | } | |
393 | bus_num = bus; | |
394 | ||
395 | return 0; | |
396 | } | |
397 | ||
398 | unsigned int i2c_get_bus_num (void) | |
399 | { | |
400 | return bus_num; | |
401 | } | |
402 | ||
8993e54b | 403 | #endif /* CONFIG_HARD_I2C */ |