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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / cpu / mpc512x / start.S
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8993e54b
RJ		 1/*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001, 2002, 2007 Wolfgang Denk <wd@denx.de>
5 * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 *
25 * Based on the MPC83xx code.
26 */
27
28/*
29 * U-Boot - Startup Code for MPC512x based Embedded Boards
30 */
31
32#include <config.h>
33#include <mpc512x.h>
34#include <version.h>
35
36#define CONFIG_521X 1 /* needed for Linux kernel header files*/
37
38#include <ppc_asm.tmpl>
39#include <ppc_defs.h>
40
41#include <asm/cache.h>
42#include <asm/mmu.h>
43
44#ifndef CONFIG_IDENT_STRING
45#define CONFIG_IDENT_STRING "MPC512X"
46#endif
47
48/*
49 * Floating Point enable, Machine Check and Recoverable Interr.
50 */
51#undef MSR_KERNEL
52#ifdef DEBUG
53#define MSR_KERNEL (MSR_FP|MSR_RI)
54#else
55#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
56#endif
57
58/* Macros for manipulating CSx_START/STOP */
59#define START_REG(start) ((start) >> 16)
60#define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
61
62/*
63 * Set up GOT: Global Offset Table
64 *
65 * Use r14 to access the GOT
66 */
67 START_GOT
68 GOT_ENTRY(_GOT2_TABLE_)
69 GOT_ENTRY(_FIXUP_TABLE_)
70
71 GOT_ENTRY(_start)
72 GOT_ENTRY(_start_of_vectors)
73 GOT_ENTRY(_end_of_vectors)
74 GOT_ENTRY(transfer_to_handler)
75
76 GOT_ENTRY(__init_end)
77 GOT_ENTRY(_end)
78 GOT_ENTRY(__bss_start)
79 END_GOT
80
81/*
82 * Magic number and version string
83 */
84 .long 0x27051956 /* U-Boot Magic Number */
85 .globl version_string
86version_string:
87 .ascii U_BOOT_VERSION
88 .ascii " (", __DATE__, " - ", __TIME__, ")"
89 .ascii " ", CONFIG_IDENT_STRING, "\0"
90
91/*
92 * Vector Table
93 */
94 .text
95 . = EXC_OFF_SYS_RESET
96
97 .globl _start
98 /* Start from here after reset/power on */
99_start:
100 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
101 b boot_cold
102
103 .globl _start_of_vectors
104_start_of_vectors:
105
106/* Machine check */
107 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
108
109/* Data Storage exception. */
110 STD_EXCEPTION(0x300, DataStorage, UnknownException)
111
112/* Instruction Storage exception. */
113 STD_EXCEPTION(0x400, InstStorage, UnknownException)
114
115/* External Interrupt exception. */
116 STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
117
118/* Alignment exception. */
119 . = 0x600
120Alignment:
121 EXCEPTION_PROLOG(SRR0, SRR1)
122 mfspr r4,DAR
123 stw r4,_DAR(r21)
124 mfspr r5,DSISR
125 stw r5,_DSISR(r21)
126 addi r3,r1,STACK_FRAME_OVERHEAD
127 li r20,MSR_KERNEL
128 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
129 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
130 lwz r6,GOT(transfer_to_handler)
131 mtlr r6
132 blrl
133.L_Alignment:
134 .long AlignmentException - _start + EXC_OFF_SYS_RESET
135 .long int_return - _start + EXC_OFF_SYS_RESET
136
137/* Program check exception */
138 . = 0x700
139ProgramCheck:
140 EXCEPTION_PROLOG(SRR0, SRR1)
141 addi r3,r1,STACK_FRAME_OVERHEAD
142 li r20,MSR_KERNEL
143 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
144 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
145 lwz r6,GOT(transfer_to_handler)
146 mtlr r6
147 blrl
148.L_ProgramCheck:
149 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
150 .long int_return - _start + EXC_OFF_SYS_RESET
151
152/* Floating Point Unit unavailable exception */
153 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
154
155/* Decrementer */
156 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
157
158/* Critical interrupt */
159 STD_EXCEPTION(0xa00, Critical, UnknownException)
160
161/* System Call */
162 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
163
164/* Trace interrupt */
165 STD_EXCEPTION(0xd00, Trace, UnknownException)
166
167/* Performance Monitor interrupt */
168 STD_EXCEPTION(0xf00, PerfMon, UnknownException)
169
170/* Intruction Translation Miss */
171 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
172
173/* Data Load Translation Miss */
174 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
175
176/* Data Store Translation Miss */
177 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
178
179/* Instruction Address Breakpoint */
180 STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
181
182/* System Management interrupt */
183 STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
184
185 .globl _end_of_vectors
186_end_of_vectors:
187
188 . = 0x3000
189boot_cold:
190 /* Save msr contents */
191 mfmsr r5
192
193 /* Set IMMR area to our preferred location */
194 lis r4, CONFIG_DEFAULT_IMMR@h
6d0f6bcf
JCPV		 195 lis r3, CONFIG_SYS_IMMR@h
196 ori r3, r3, CONFIG_SYS_IMMR@l
8993e54b
RJ		 197 stw r3, IMMRBAR(r4)
198 mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */
199
200 /* Initialise the machine */
201 bl cpu_early_init
202
203 /*
204 * Set up Local Access Windows:
205 *
206 * 1) Boot/CS0 (boot FLASH)
207 * 2) On-chip SRAM (initial stack purposes)
208 */
209
210 /* Boot CS/CS0 window range */
6d0f6bcf
JCPV		 211 lis r3, CONFIG_SYS_IMMR@h
212 ori r3, r3, CONFIG_SYS_IMMR@l
8993e54b 213
6d0f6bcf
JCPV		 214 lis r4, START_REG(CONFIG_SYS_FLASH_BASE)
215 ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
8993e54b
RJ		 216 stw r4, LPCS0AW(r3)
217
218 /*
219 * The SRAM window has a fixed size (256K), so only the start address
220 * is necessary
221 */
6d0f6bcf 222 lis r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
8993e54b
RJ		 223 stw r4, SRAMBAR(r3)
224
b1b54e35 225 /*
8993e54b 226 * According to MPC5121e RM, configuring local access windows should
b1b54e35 227 * be followed by a dummy read of the config register that was
8993e54b 228 * modified last and an isync
b1b54e35 229 */
8993e54b
RJ		 230 lwz r4, SRAMBAR(r3)
231 isync
232
233 /*
234 * Set configuration of the Boot/CS0, the SRAM window does not have a
235 * config register so no params can be set for it
236 */
6d0f6bcf
JCPV		 237 lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
238 ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
8993e54b 239
6d0f6bcf
JCPV		 240 lis r4, CONFIG_SYS_CS0_CFG@h
241 ori r4, r4, CONFIG_SYS_CS0_CFG@l
b1b54e35 242 stw r4, CS0_CONFIG(r3)
8993e54b
RJ		 243
244 /* Master enable all CS's */
245 lis r4, CS_CTRL_ME@h
246 ori r4, r4, CS_CTRL_ME@l
247 stw r4, CS_CTRL(r3)
248
6d0f6bcf
JCPV		 249 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
250 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
8993e54b
RJ		 251 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
252 mtlr r5
253 blr
254
255in_flash:
6d0f6bcf
JCPV		 256 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
257 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
8993e54b
RJ		 258
259 li r0, 0 /* Make room for stack frame header and */
260 stwu r0, -4(r1) /* clear final stack frame so that */
261 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
262
263 /* let the C-code set up the rest */
264 /* */
265 /* Be careful to keep code relocatable & stack humble */
266 /*------------------------------------------------------*/
267
268 GET_GOT /* initialize GOT access */
269
270 /* r3: IMMR */
6d0f6bcf 271 lis r3, CONFIG_SYS_IMMR@h
8993e54b
RJ		 272 /* run low-level CPU init code (in Flash) */
273 bl cpu_init_f
274
275 /* r3: BOOTFLAG */
276 mr r3, r21
277 /* run 1st part of board init code (in Flash) */
278 bl board_init_f
279
280 /* NOTREACHED - board_init_f() does not return */
281
282/*
283 * This code finishes saving the registers to the exception frame
284 * and jumps to the appropriate handler for the exception.
285 * Register r21 is pointer into trap frame, r1 has new stack pointer.
286 */
287 .globl transfer_to_handler
288transfer_to_handler:
289 stw r22,_NIP(r21)
290 lis r22,MSR_POW@h
291 andc r23,r23,r22
292 stw r23,_MSR(r21)
293 SAVE_GPR(7, r21)
294 SAVE_4GPRS(8, r21)
295 SAVE_8GPRS(12, r21)
296 SAVE_8GPRS(24, r21)
297 mflr r23
298 andi. r24,r23,0x3f00 /* get vector offset */
299 stw r24,TRAP(r21)
300 li r22,0
301 stw r22,RESULT(r21)
302 lwz r24,0(r23) /* virtual address of handler */
303 lwz r23,4(r23) /* where to go when done */
304 mtspr SRR0,r24
305 mtspr SRR1,r20
306 mtlr r23
307 SYNC
308 rfi /* jump to handler, enable MMU */
309
310int_return:
311 mfmsr r28 /* Disable interrupts */
312 li r4,0
313 ori r4,r4,MSR_EE
314 andc r28,r28,r4
315 SYNC /* Some chip revs need this... */
316 mtmsr r28
317 SYNC
318 lwz r2,_CTR(r1)
319 lwz r0,_LINK(r1)
320 mtctr r2
321 mtlr r0
322 lwz r2,_XER(r1)
323 lwz r0,_CCR(r1)
324 mtspr XER,r2
325 mtcrf 0xFF,r0
326 REST_10GPRS(3, r1)
327 REST_10GPRS(13, r1)
328 REST_8GPRS(23, r1)
329 REST_GPR(31, r1)
330 lwz r2,_NIP(r1) /* Restore environment */
331 lwz r0,_MSR(r1)
332 mtspr SRR0,r2
333 mtspr SRR1,r0
334 lwz r0,GPR0(r1)
335 lwz r2,GPR2(r1)
336 lwz r1,GPR1(r1)
337 SYNC
338 rfi
339
340/*
341 * This code initialises the machine, it expects original MSR contents to be in r5.
342 */
343cpu_early_init:
344 /* Initialize machine status; enable machine check interrupt */
345 /*-----------------------------------------------------------*/
346
347 li r3, MSR_KERNEL /* Set ME and RI flags */
348 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */
349#ifdef DEBUG
350 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */
351#endif
352 mtmsr r3
353 SYNC
354 mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */
355
6d0f6bcf 356 lis r3, CONFIG_SYS_IMMR@h
8993e54b
RJ		 357
358#if defined(CONFIG_WATCHDOG)
359 /* Initialise the watchdog and reset it */
360 /*--------------------------------------*/
6d0f6bcf 361 lis r4, CONFIG_SYS_WATCHDOG_VALUE
8993e54b
RJ		 362 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
363 stw r4, SWCRR(r3)
364
365 /* reset */
366 li r4, 0x556C
367 sth r4, SWSRR@l(r3)
368 li r4, 0x0
369 ori r4, r4, 0xAA39
370 sth r4, SWSRR@l(r3)
371#else
372 /* Disable the watchdog */
373 /*----------------------*/
374 lwz r4, SWCRR(r3)
375 /*
376 * Check to see if it's enabled for disabling: once disabled by s/w
377 * it's not possible to re-enable it
378 */
379 andi. r4, r4, 0x4
380 beq 1f
381 xor r4, r4, r4
382 stw r4, SWCRR(r3)
3831:
384#endif /* CONFIG_WATCHDOG */
385
386 /* Initialize the Hardware Implementation-dependent Registers */
387 /* HID0 also contains cache control */
388 /*------------------------------------------------------*/
6d0f6bcf
JCPV		 389 lis r3, CONFIG_SYS_HID0_INIT@h
390 ori r3, r3, CONFIG_SYS_HID0_INIT@l
8993e54b
RJ		 391 SYNC
392 mtspr HID0, r3
393
6d0f6bcf
JCPV		 394 lis r3, CONFIG_SYS_HID0_FINAL@h
395 ori r3, r3, CONFIG_SYS_HID0_FINAL@l
8993e54b
RJ		 396 SYNC
397 mtspr HID0, r3
398
6d0f6bcf
JCPV		 399 lis r3, CONFIG_SYS_HID2@h
400 ori r3, r3, CONFIG_SYS_HID2@l
8993e54b
RJ		 401 SYNC
402 mtspr HID2, r3
403 sync
404 blr
405
406
407/* Cache functions.
408 *
409 * Note: requires that all cache bits in
410 * HID0 are in the low half word.
411 */
412 .globl icache_enable
413icache_enable:
414 mfspr r3, HID0
415 ori r3, r3, HID0_ICE
416 lis r4, 0
417 ori r4, r4, HID0_ILOCK
418 andc r3, r3, r4
419 ori r4, r3, HID0_ICFI
420 isync
421 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
422 isync
423 mtspr HID0, r3 /* clears invalidate */
424 blr
425
426 .globl icache_disable
427icache_disable:
428 mfspr r3, HID0
429 lis r4, 0
430 ori r4, r4, HID0_ICE|HID0_ILOCK
431 andc r3, r3, r4
432 ori r4, r3, HID0_ICFI
433 isync
434 mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
435 isync
436 mtspr HID0, r3 /* clears invalidate */
437 blr
438
439 .globl icache_status
440icache_status:
441 mfspr r3, HID0
442 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
443 blr
444
445 .globl dcache_enable
446dcache_enable:
447 mfspr r3, HID0
448 li r5, HID0_DCFI|HID0_DLOCK
449 andc r3, r3, r5
450 mtspr HID0, r3 /* no invalidate, unlock */
451 ori r3, r3, HID0_DCE
452 ori r5, r3, HID0_DCFI
453 mtspr HID0, r5 /* enable + invalidate */
454 mtspr HID0, r3 /* enable */
455 sync
456 blr
457
458 .globl dcache_disable
459dcache_disable:
460 mfspr r3, HID0
461 lis r4, 0
462 ori r4, r4, HID0_DCE|HID0_DLOCK
463 andc r3, r3, r4
464 ori r4, r3, HID0_DCI
465 sync
466 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
467 sync
468 mtspr HID0, r3 /* clears invalidate */
469 blr
470
471 .globl dcache_status
472dcache_status:
473 mfspr r3, HID0
474 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
475 blr
476
477 .globl get_pvr
478get_pvr:
479 mfspr r3, PVR
480 blr
481
8993e54b
RJ		 482/*-------------------------------------------------------------------*/
483
484/*
485 * void relocate_code (addr_sp, gd, addr_moni)
486 *
487 * This "function" does not return, instead it continues in RAM
488 * after relocating the monitor code.
489 *
490 * r3 = dest
491 * r4 = src
492 * r5 = length in bytes
493 * r6 = cachelinesize
494 */
495 .globl relocate_code
496relocate_code:
497 mr r1, r3 /* Set new stack pointer */
498 mr r9, r4 /* Save copy of Global Data pointer */
499 mr r10, r5 /* Save copy of Destination Address */
500
501 mr r3, r5 /* Destination Address */
6d0f6bcf
JCPV		 502 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
503 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
8993e54b
RJ		 504 lwz r5, GOT(__init_end)
505 sub r5, r5, r4
6d0f6bcf 506 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
8993e54b
RJ		 507
508 /*
509 * Fix GOT pointer:
510 *
6d0f6bcf 511 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
8993e54b
RJ		 512 * + Destination Address
513 *
514 * Offset:
515 */
516 sub r15, r10, r4
517
518 /* First our own GOT */
519 add r14, r14, r15
520 /* then the one used by the C code */
521 add r30, r30, r15
522
523 /*
524 * Now relocate code
525 */
526 cmplw cr1,r3,r4
527 addi r0,r5,3
528 srwi. r0,r0,2
529 beq cr1,4f /* In place copy is not necessary */
530 beq 7f /* Protect against 0 count */
531 mtctr r0
532 bge cr1,2f
533 la r8,-4(r4)
534 la r7,-4(r3)
535
536 /* copy */
5371: lwzu r0,4(r8)
538 stwu r0,4(r7)
539 bdnz 1b
540
541 addi r0,r5,3
542 srwi. r0,r0,2
543 mtctr r0
544 la r8,-4(r4)
545 la r7,-4(r3)
546
547 /* and compare */
54820: lwzu r20,4(r8)
549 lwzu r21,4(r7)
550 xor. r22, r20, r21
551 bne 30f
552 bdnz 20b
553 b 4f
554
555 /* compare failed */
55630: li r3, 0
557 blr
558
5592: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
560 add r8,r4,r0
561 add r7,r3,r0
5623: lwzu r0,-4(r8)
563 stwu r0,-4(r7)
564 bdnz 3b
565
566/*
567 * Now flush the cache: note that we must start from a cache aligned
568 * address. Otherwise we might miss one cache line.
569 */
5704: cmpwi r6,0
571 add r5,r3,r5
572 beq 7f /* Always flush prefetch queue in any case */
573 subi r0,r6,1
574 andc r3,r3,r0
575 mr r4,r3
5765: dcbst 0,r4
577 add r4,r4,r6
578 cmplw r4,r5
579 blt 5b
580 sync /* Wait for all dcbst to complete on bus */
581 mr r4,r3
5826: icbi 0,r4
583 add r4,r4,r6
584 cmplw r4,r5
585 blt 6b
5867: sync /* Wait for all icbi to complete on bus */
587 isync
588
589/*
590 * We are done. Do not return, instead branch to second part of board
591 * initialization, now running from RAM.
592 */
593 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
594 mtlr r0
595 blr
596
597in_ram:
598 /*
599 * Relocation Function, r14 point to got2+0x8000
600 *
601 * Adjust got2 pointers, no need to check for 0, this code
602 * already puts a few entries in the table.
603 */
604 li r0,__got2_entries@sectoff@l
605 la r3,GOT(_GOT2_TABLE_)
606 lwz r11,GOT(_GOT2_TABLE_)
607 mtctr r0
608 sub r11,r3,r11
609 addi r3,r3,-4
6101: lwzu r0,4(r3)
611 add r0,r0,r11
612 stw r0,0(r3)
613 bdnz 1b
614
615 /*
616 * Now adjust the fixups and the pointers to the fixups
617 * in case we need to move ourselves again.
618 */
6192: li r0,__fixup_entries@sectoff@l
620 lwz r3,GOT(_FIXUP_TABLE_)
621 cmpwi r0,0
622 mtctr r0
623 addi r3,r3,-4
624 beq 4f
6253: lwzu r4,4(r3)
626 lwzux r0,r4,r11
627 add r0,r0,r11
628 stw r10,0(r3)
629 stw r0,0(r4)
630 bdnz 3b
6314:
632clear_bss:
633 /*
634 * Now clear BSS segment
635 */
636 lwz r3,GOT(__bss_start)
637 lwz r4,GOT(_end)
638
639 cmplw 0, r3, r4
640 beq 6f
641
642 li r0, 0
6435:
644 stw r0, 0(r3)
645 addi r3, r3, 4
646 cmplw 0, r3, r4
647 bne 5b
6486:
649 mr r3, r9 /* Global Data pointer */
650 mr r4, r10 /* Destination Address */
651 bl board_init_r
652
653 /*
654 * Copy exception vector code to low memory
655 *
656 * r3: dest_addr
657 * r7: source address, r8: end address, r9: target address
658 */
659 .globl trap_init
660trap_init:
661 lwz r7, GOT(_start)
662 lwz r8, GOT(_end_of_vectors)
663
664 li r9, 0x100 /* reset vector at 0x100 */
665
666 cmplw 0, r7, r8
667 bgelr /* return if r7>=r8 - just in case */
668
669 mflr r4 /* save link register */
6701:
671 lwz r0, 0(r7)
672 stw r0, 0(r9)
673 addi r7, r7, 4
674 addi r9, r9, 4
675 cmplw 0, r7, r8
676 bne 1b
677
678 /*
679 * relocate `hdlr' and `int_return' entries
680 */
681 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
682 li r8, Alignment - _start + EXC_OFF_SYS_RESET
6832:
684 bl trap_reloc
685 addi r7, r7, 0x100 /* next exception vector */
686 cmplw 0, r7, r8
687 blt 2b
688
689 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
690 bl trap_reloc
691
692 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
693 bl trap_reloc
694
695 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
696 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
6973:
698 bl trap_reloc
699 addi r7, r7, 0x100 /* next exception vector */
700 cmplw 0, r7, r8
701 blt 3b
702
703 li r7, .L_Trace - _start + EXC_OFF_SYS_RESET
704 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
7054:
706 bl trap_reloc
707 addi r7, r7, 0x100 /* next exception vector */
708 cmplw 0, r7, r8
709 blt 4b
710
711 mfmsr r3 /* now that the vectors have */
712 lis r7, MSR_IP@h /* relocated into low memory */
713 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
714 andc r3, r3, r7 /* (if it was on) */
715 SYNC /* Some chip revs need this... */
716 mtmsr r3
717 SYNC
718
719 mtlr r4 /* restore link register */
720 blr
721
722 /*
723 * Function: relocate entries for one exception vector
724 */
725trap_reloc:
726 lwz r0, 0(r7) /* hdlr ... */
727 add r0, r0, r3 /* ... += dest_addr */
728 stw r0, 0(r7)
729
730 lwz r0, 4(r7) /* int_return ... */
731 add r0, r0, r3 /* ... += dest_addr */
732 stw r0, 4(r7)
733
734 blr
"Das U-Boot" Source Tree