[people/ms/u-boot.git] / cpu / mpc5xx / start.S

/*
 *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
 *  Copyright (C) 2000, 2001, 2002 Wolfgang Denk <wd@denx.de>
 *  Copyright (C) 2003  Martin Winistoerfer, martinwinistoerfer@gmx.ch.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * File:		start.S
 *
 * Discription:		startup code
 *
 */

#include <config.h>
#include <mpc5xx.h>
#include <version.h>

#define CONFIG_5xx 1		/* needed for Linux kernel header files */
#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <linux/config.h>
#include <asm/processor.h>

#ifndef  CONFIG_IDENT_STRING
#define  CONFIG_IDENT_STRING ""
#endif

/* We don't have a MMU.
*/
#undef	MSR_KERNEL
#define MSR_KERNEL ( MSR_ME | MSR_RI )		/* Machine Check and Recoverable Interr. */

/*
 * Set up GOT: Global Offset Table
 *
 * Use r14 to access the GOT
 */
	START_GOT
	GOT_ENTRY(_GOT2_TABLE_)
	GOT_ENTRY(_FIXUP_TABLE_)

	GOT_ENTRY(_start)
	GOT_ENTRY(_start_of_vectors)
	GOT_ENTRY(_end_of_vectors)
	GOT_ENTRY(transfer_to_handler)

	GOT_ENTRY(__init_end)
	GOT_ENTRY(_end)
	GOT_ENTRY(__bss_start)
	END_GOT

/*
 * r3 - 1st arg to board_init(): IMMP pointer
 * r4 - 2nd arg to board_init(): boot flag
 */
	.text
	.long	0x27051956			/* U-Boot Magic Number */
	.globl	version_string
version_string:
	.ascii U_BOOT_VERSION
	.ascii " (", __DATE__, " - ", __TIME__, ")"
	.ascii CONFIG_IDENT_STRING, "\0"

	. = EXC_OFF_SYS_RESET
	.globl	_start
_start:
	mfspr	r3, 638
	li	r4, CFG_ISB			/* Set ISB bit */
	or	r3, r3, r4
	mtspr	638, r3
	li	r21, BOOTFLAG_COLD		/* Normal Power-On: Boot from FLASH	*/
	b	boot_cold

	. = EXC_OFF_SYS_RESET + 0x20

	.globl	_start_warm
_start_warm:
	li	r21, BOOTFLAG_WARM		/* Software reboot */
	b	boot_warm

boot_cold:
boot_warm:

	/* Initialize machine status; enable machine check interrupt		*/
	/*----------------------------------------------------------------------*/
	li	r3, MSR_KERNEL			/* Set ME, RI flags */
	mtmsr	r3
	mtspr	SRR1, r3			/* Make SRR1 match MSR */

	/* Initialize debug port registers					*/
	/*----------------------------------------------------------------------*/
	xor	r0, r0, r0			/* Clear R0 */
	mtspr	LCTRL1, r0			/* Initialize debug port regs */
	mtspr	LCTRL2, r0
	mtspr	COUNTA, r0
	mtspr	COUNTB, r0

	/*
	 * Calculate absolute address in FLASH and jump there
	 *----------------------------------------------------------------------*/

	lis	r3, CFG_MONITOR_BASE@h
	ori	r3, r3, CFG_MONITOR_BASE@l
	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
	mtlr	r3
	blr

in_flash:

	/* Initialize some SPRs that are hard to access from C			*/
	/*----------------------------------------------------------------------*/

	lis     r3, CFG_IMMR@h          	/* Pass IMMR as arg1 to C routine */
	lis	r2, CFG_INIT_SP_ADDR@h
	ori	r1, r2, CFG_INIT_SP_ADDR@l	/* Set up the stack in internal SRAM */
	/* Note: R0 is still 0 here */
	stwu	r0, -4(r1)			/* Clear final stack frame so that	*/
	stwu	r0, -4(r1)			/* stack backtraces terminate cleanly	*/

	/*
	 * Disable serialized ifetch and show cycles
	 * (i.e. set processor to normal mode) for maximum
	 * performance.
	 */

	li	r2, 0x0007
	mtspr	ICTRL, r2

	/* Set up debug mode entry */

	lis	r2, CFG_DER@h
	ori	r2, r2, CFG_DER@l
	mtspr	DER, r2

	/* Let the C-code set up the rest					*/
	/*									*/
	/* Be careful to keep code relocatable !				*/
	/*----------------------------------------------------------------------*/

	GET_GOT			/* initialize GOT access			*/

	/* r3: IMMR */
	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/

	mr	r3, r21
	/* r3: BOOTFLAG */
	bl	board_init_f	/* run 1st part of board init code (from Flash) */


	.globl	_start_of_vectors
_start_of_vectors:

/* Machine check */
	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)

/* Data Storage exception.  "Never" generated on the 860. */
	STD_EXCEPTION(0x300, DataStorage, UnknownException)

/* Instruction Storage exception.  "Never" generated on the 860. */
	STD_EXCEPTION(0x400, InstStorage, UnknownException)

/* External Interrupt exception. */
	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)

/* Alignment exception. */
	. = 0x600
Alignment:
	EXCEPTION_PROLOG
	mfspr	r4,DAR
	stw	r4,_DAR(r21)
	mfspr	r5,DSISR
	stw	r5,_DSISR(r21)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	li	r20,MSR_KERNEL
	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
	lwz	r6,GOT(transfer_to_handler)
	mtlr	r6
	blrl
.L_Alignment:
	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
	.long	int_return - _start + EXC_OFF_SYS_RESET

/* Program check exception */
	. = 0x700
ProgramCheck:
	EXCEPTION_PROLOG
	addi	r3,r1,STACK_FRAME_OVERHEAD
	li	r20,MSR_KERNEL
	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
	lwz	r6,GOT(transfer_to_handler)
	mtlr	r6
	blrl
.L_ProgramCheck:
	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
	.long	int_return - _start + EXC_OFF_SYS_RESET

	/* FPU on MPC5xx available. We will use it later.
	*/
	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)

	/* I guess we could implement decrementer, and may have
	 * to someday for timekeeping.
	 */
	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
	STD_EXCEPTION(0xd00, SingleStep, UnknownException)

	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)

	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
	 * for all unimplemented and illegal instructions.
	 */
	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)

	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)

	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)


	.globl	_end_of_vectors
_end_of_vectors:


	. = 0x2000

/*
 * This code finishes saving the registers to the exception frame
 * and jumps to the appropriate handler for the exception.
 * Register r21 is pointer into trap frame, r1 has new stack pointer.
 */
	.globl	transfer_to_handler
transfer_to_handler:
	stw	r22,_NIP(r21)
	lis	r22,MSR_POW@h
	andc	r23,r23,r22
	stw	r23,_MSR(r21)
	SAVE_GPR(7, r21)
	SAVE_4GPRS(8, r21)
	SAVE_8GPRS(12, r21)
	SAVE_8GPRS(24, r21)
	mflr	r23
	andi.	r24,r23,0x3f00		/* get vector offset */
	stw	r24,TRAP(r21)
	li	r22,0
	stw	r22,RESULT(r21)
	mtspr	SPRG2,r22		/* r1 is now kernel sp */
	lwz	r24,0(r23)		/* virtual address of handler */
	lwz	r23,4(r23)		/* where to go when done */
	mtspr	SRR0,r24
	mtspr	SRR1,r20
	mtlr	r23
	SYNC
	rfi				/* jump to handler, enable MMU */

int_return:
	mfmsr	r28			/* Disable interrupts */
	li	r4,0
	ori	r4,r4,MSR_EE
	andc	r28,r28,r4
	SYNC				/* Some chip revs need this... */
	mtmsr	r28
	SYNC
	lwz	r2,_CTR(r1)
	lwz	r0,_LINK(r1)
	mtctr	r2
	mtlr	r0
	lwz	r2,_XER(r1)
	lwz	r0,_CCR(r1)
	mtspr	XER,r2
	mtcrf	0xFF,r0
	REST_10GPRS(3, r1)
	REST_10GPRS(13, r1)
	REST_8GPRS(23, r1)
	REST_GPR(31, r1)
	lwz	r2,_NIP(r1)		/* Restore environment */
	lwz	r0,_MSR(r1)
	mtspr	SRR0,r2
	mtspr	SRR1,r0
	lwz	r0,GPR0(r1)
	lwz	r2,GPR2(r1)
	lwz	r1,GPR1(r1)
	SYNC
	rfi


/*
 * unsigned int get_immr (unsigned int mask)
 *
 * return (mask ? (IMMR & mask) : IMMR);
 */
	.globl	get_immr
get_immr:
	mr	r4,r3		/* save mask */
	mfspr	r3, IMMR	/* IMMR */
	cmpwi	0,r4,0		/* mask != 0 ? */
	beq	4f
	and	r3,r3,r4	/* IMMR & mask */
4:
	blr

	.globl get_pvr
get_pvr:
	mfspr	r3, PVR
	blr


/*------------------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 * r3 = dest
 * r4 = src
 * r5 = length in bytes
 * r6 = cachelinesize
 */
	.globl	relocate_code
relocate_code:
	mr	r1,  r3		/* Set new stack pointer in SRAM	*/
	mr	r9,  r4		/* Save copy of global data pointer in SRAM */
	mr	r10, r5		/* Save copy of monitor destination Address in SRAM */

	mr	r3,  r5				/* Destination Address	*/
	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address	*/
	ori	r4, r4, CFG_MONITOR_BASE@l
	lwz	r5, GOT(__init_end)
	sub	r5, r5, r4

	/*
	 * Fix GOT pointer:
	 *
	 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
	 *
	 * Offset:
	 */
	sub	r15, r10, r4

	/* First our own GOT */
	add	r14, r14, r15
	/* the the one used by the C code */
	add	r30, r30, r15

	/*
	 * Now relocate code
	 */

	cmplw	cr1,r3,r4
	addi	r0,r5,3
	srwi.	r0,r0,2
	beq	cr1,4f		/* In place copy is not necessary	*/
	beq	4f		/* Protect against 0 count		*/
	mtctr	r0
	bge	cr1,2f

	la	r8,-4(r4)
	la	r7,-4(r3)
1:	lwzu	r0,4(r8)
	stwu	r0,4(r7)
	bdnz	1b
	b	4f

2:	slwi	r0,r0,2
	add	r8,r4,r0
	add	r7,r3,r0
3:	lwzu	r0,-4(r8)
	stwu	r0,-4(r7)
	bdnz	3b

4:	sync
	isync

/*
 * We are done. Do not return, instead branch to second part of board
 * initialization, now running from RAM.
 */

	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
	mtlr	r0
	blr

in_ram:

	/*
	 * Relocation Function, r14 point to got2+0x8000
	 *
	 * Adjust got2 pointers, no need to check for 0, this code
	 * already puts a few entries in the table.
	 */
	li	r0,__got2_entries@sectoff@l
	la	r3,GOT(_GOT2_TABLE_)
	lwz	r11,GOT(_GOT2_TABLE_)
	mtctr	r0
	sub	r11,r3,r11
	addi	r3,r3,-4
1:	lwzu	r0,4(r3)
	add	r0,r0,r11
	stw	r0,0(r3)
	bdnz	1b

	/*
	 * Now adjust the fixups and the pointers to the fixups
	 * in case we need to move ourselves again.
	 */
2:	li	r0,__fixup_entries@sectoff@l
	lwz	r3,GOT(_FIXUP_TABLE_)
	cmpwi	r0,0
	mtctr	r0
	addi	r3,r3,-4
	beq	4f
3:	lwzu	r4,4(r3)
	lwzux	r0,r4,r11
	add	r0,r0,r11
	stw	r10,0(r3)
	stw	r0,0(r4)
	bdnz	3b
4:
clear_bss:
	/*
	 * Now clear BSS segment
	 */
	lwz	r3,GOT(__bss_start)
	lwz	r4,GOT(_end)
	cmplw	0, r3, r4
	beq	6f

	li	r0, 0
5:
	stw	r0, 0(r3)
	addi	r3, r3, 4
	cmplw	0, r3, r4
	bne	5b
6:

	mr	r3, r9		/* Global Data pointer		*/
	mr	r4, r10		/* Destination Address		*/
	bl	board_init_r

	/*
	 * Copy exception vector code to low memory
	 *
	 * r3: dest_addr
	 * r7: source address, r8: end address, r9: target address
	 */
	.globl	trap_init
trap_init:
	lwz	r7, GOT(_start)
	lwz	r8, GOT(_end_of_vectors)

	li	r9, 0x100		/* reset vector always at 0x100 */

	cmplw	0, r7, r8
	bgelr				/* return if r7>=r8 - just in case */

	mflr	r4			/* save link register		*/
1:
	lwz	r0, 0(r7)
	stw	r0, 0(r9)
	addi	r7, r7, 4
	addi	r9, r9, 4
	cmplw	0, r7, r8
	bne	1b

	/*
	 * relocate `hdlr' and `int_return' entries
	 */
	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
2:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	2b

	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	3b

	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector	*/
	cmplw	0, r7, r8
	blt	4b

	mtlr	r4			/* restore link register	*/
	blr

	/*
	 * Function: relocate entries for one exception vector
	 */
trap_reloc:
	lwz	r0, 0(r7)		/* hdlr ...			*/
	add	r0, r0, r3		/*  ... += dest_addr		*/
	stw	r0, 0(r7)

	lwz	r0, 4(r7)		/* int_return ...		*/
	add	r0, r0, r3		/*  ... += dest_addr		*/
	stw	r0, 4(r7)

	sync
	isync

	blr
Commit	Line	Data
0db5bca8 WD	1	/*
	2	* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
	3	* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
	4	* Copyright (C) 2000, 2001, 2002 Wolfgang Denk <wd@denx.de>
	5	* Copyright (C) 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch.
8bde7f77	6	*
0db5bca8 WD	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	/*
	27	* File: start.S
8bde7f77	28	*
0db5bca8 WD	29	* Discription: startup code
	30	*
	31	*/
	32
	33	#include <config.h>
	34	#include <mpc5xx.h>
	35	#include <version.h>
	36
	37	#define CONFIG_5xx 1 /* needed for Linux kernel header files */
	38	#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
	39
	40	#include <ppc_asm.tmpl>
	41	#include <ppc_defs.h>
8bde7f77	42
0db5bca8	43	#include <linux/config.h>
8bde7f77	44	#include <asm/processor.h>
0db5bca8 WD	45
	46	#ifndef CONFIG_IDENT_STRING
	47	#define CONFIG_IDENT_STRING ""
	48	#endif
	49
	50	/* We don't have a MMU.
	51	*/
	52	#undef MSR_KERNEL
	53	#define MSR_KERNEL ( MSR_ME \| MSR_RI ) /* Machine Check and Recoverable Interr. */
	54
	55	/*
	56	* Set up GOT: Global Offset Table
	57	*
	58	* Use r14 to access the GOT
	59	*/
	60	START_GOT
	61	GOT_ENTRY(_GOT2_TABLE_)
	62	GOT_ENTRY(_FIXUP_TABLE_)
	63
	64	GOT_ENTRY(_start)
	65	GOT_ENTRY(_start_of_vectors)
	66	GOT_ENTRY(_end_of_vectors)
	67	GOT_ENTRY(transfer_to_handler)
	68
3b57fe0a	69	GOT_ENTRY(__init_end)
0db5bca8	70	GOT_ENTRY(_end)
5d232d0e	71	GOT_ENTRY(__bss_start)
0db5bca8 WD	72	END_GOT
	73
	74	/*
	75	* r3 - 1st arg to board_init(): IMMP pointer
	76	* r4 - 2nd arg to board_init(): boot flag
	77	*/
	78	.text
	79	.long 0x27051956 /* U-Boot Magic Number */
	80	.globl version_string
	81	version_string:
	82	.ascii U_BOOT_VERSION
	83	.ascii " (", __DATE__, " - ", __TIME__, ")"
	84	.ascii CONFIG_IDENT_STRING, "\0"
	85
	86	. = EXC_OFF_SYS_RESET
	87	.globl _start
	88	_start:
	89	mfspr r3, 638
	90	li r4, CFG_ISB /* Set ISB bit */
8bde7f77	91	or r3, r3, r4
0db5bca8 WD	92	mtspr 638, r3
	93	li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
	94	b boot_cold
	95
	96	. = EXC_OFF_SYS_RESET + 0x20
	97
	98	.globl _start_warm
	99	_start_warm:
	100	li r21, BOOTFLAG_WARM /* Software reboot */
	101	b boot_warm
	102
	103	boot_cold:
	104	boot_warm:
	105
	106	/* Initialize machine status; enable machine check interrupt */
	107	/----------------------------------------------------------------------/
	108	li r3, MSR_KERNEL /* Set ME, RI flags */
	109	mtmsr r3
	110	mtspr SRR1, r3 /* Make SRR1 match MSR */
	111
	112	/* Initialize debug port registers */
	113	/----------------------------------------------------------------------/
	114	xor r0, r0, r0 /* Clear R0 */
	115	mtspr LCTRL1, r0 /* Initialize debug port regs */
	116	mtspr LCTRL2, r0
	117	mtspr COUNTA, r0
	118	mtspr COUNTB, r0
	119
	120	/*
	121	* Calculate absolute address in FLASH and jump there
	122	----------------------------------------------------------------------/
	123
	124	lis r3, CFG_MONITOR_BASE@h
	125	ori r3, r3, CFG_MONITOR_BASE@l
	126	addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
	127	mtlr r3
	128	blr
	129
	130	in_flash:
	131
	132	/* Initialize some SPRs that are hard to access from C */
	133	/----------------------------------------------------------------------/
8bde7f77	134
0db5bca8 WD	135	lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */
	136	lis r2, CFG_INIT_SP_ADDR@h
	137	ori r1, r2, CFG_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */
	138	/* Note: R0 is still 0 here */
	139	stwu r0, -4(r1) /* Clear final stack frame so that */
	140	stwu r0, -4(r1) /* stack backtraces terminate cleanly */
	141
	142	/*
	143	* Disable serialized ifetch and show cycles
	144	* (i.e. set processor to normal mode) for maximum
	145	* performance.
	146	*/
	147
	148	li r2, 0x0007
	149	mtspr ICTRL, r2
	150
	151	/* Set up debug mode entry */
	152
	153	lis r2, CFG_DER@h
	154	ori r2, r2, CFG_DER@l
	155	mtspr DER, r2
	156
	157	/* Let the C-code set up the rest */
	158	/* */
	159	/* Be careful to keep code relocatable ! */
	160	/----------------------------------------------------------------------/
	161
	162	GET_GOT /* initialize GOT access */
	163
	164	/* r3: IMMR */
	165	bl cpu_init_f /* run low-level CPU init code (from Flash) */
	166
	167	mr r3, r21
	168	/* r3: BOOTFLAG */
	169	bl board_init_f /* run 1st part of board init code (from Flash) */
	170
	171
0db5bca8 WD	172	.globl _start_of_vectors
	173	_start_of_vectors:
	174
	175	/* Machine check */
	176	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
	177
	178	/* Data Storage exception. "Never" generated on the 860. */
	179	STD_EXCEPTION(0x300, DataStorage, UnknownException)
	180
	181	/* Instruction Storage exception. "Never" generated on the 860. */
	182	STD_EXCEPTION(0x400, InstStorage, UnknownException)
	183
	184	/* External Interrupt exception. */
	185	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
	186
	187	/* Alignment exception. */
	188	. = 0x600
	189	Alignment:
	190	EXCEPTION_PROLOG
	191	mfspr r4,DAR
	192	stw r4,_DAR(r21)
	193	mfspr r5,DSISR
	194	stw r5,_DSISR(r21)
	195	addi r3,r1,STACK_FRAME_OVERHEAD
	196	li r20,MSR_KERNEL
	197	rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
	198	lwz r6,GOT(transfer_to_handler)
	199	mtlr r6
	200	blrl
	201	.L_Alignment:
	202	.long AlignmentException - _start + EXC_OFF_SYS_RESET
	203	.long int_return - _start + EXC_OFF_SYS_RESET
	204
	205	/* Program check exception */
	206	. = 0x700
	207	ProgramCheck:
	208	EXCEPTION_PROLOG
	209	addi r3,r1,STACK_FRAME_OVERHEAD
	210	li r20,MSR_KERNEL
	211	rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
	212	lwz r6,GOT(transfer_to_handler)
	213	mtlr r6
	214	blrl
	215	.L_ProgramCheck:
	216	.long ProgramCheckException - _start + EXC_OFF_SYS_RESET
	217	.long int_return - _start + EXC_OFF_SYS_RESET
	218
	219	/* FPU on MPC5xx available. We will use it later.
	220	*/
	221	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
	222
	223	/* I guess we could implement decrementer, and may have
	224	* to someday for timekeeping.
	225	*/
	226	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
	227	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
	228	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
27b207fd	229	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
0db5bca8 WD	230	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
	231
	232	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
	233	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
	234
	235	/* On the MPC8xx, this is a software emulation interrupt. It occurs
	236	* for all unimplemented and illegal instructions.
	237	*/
	238	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
	239	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
	240	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
	241	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
	242	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
	243
	244	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
	245	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
	246	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
	247	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
	248	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
	249	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
	250	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
	251
	252	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
	253	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
	254	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
	255	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
	256
	257
	258	.globl _end_of_vectors
	259	_end_of_vectors:
	260
	261
	262	. = 0x2000
	263
	264	/*
	265	* This code finishes saving the registers to the exception frame
	266	* and jumps to the appropriate handler for the exception.
	267	* Register r21 is pointer into trap frame, r1 has new stack pointer.
	268	*/
	269	.globl transfer_to_handler
	270	transfer_to_handler:
	271	stw r22,_NIP(r21)
	272	lis r22,MSR_POW@h
	273	andc r23,r23,r22
	274	stw r23,_MSR(r21)
	275	SAVE_GPR(7, r21)
	276	SAVE_4GPRS(8, r21)
	277	SAVE_8GPRS(12, r21)
	278	SAVE_8GPRS(24, r21)
	279	mflr r23
	280	andi. r24,r23,0x3f00 /* get vector offset */
	281	stw r24,TRAP(r21)
	282	li r22,0
	283	stw r22,RESULT(r21)
	284	mtspr SPRG2,r22 /* r1 is now kernel sp */
	285	lwz r24,0(r23) /* virtual address of handler */
	286	lwz r23,4(r23) /* where to go when done */
	287	mtspr SRR0,r24
	288	mtspr SRR1,r20
	289	mtlr r23
	290	SYNC
	291	rfi /* jump to handler, enable MMU */
	292
	293	int_return:
294	mfmsr r28 /* Disable interrupts */
295	li r4,0
296	ori r4,r4,MSR_EE
297	andc r28,r28,r4
298	SYNC /* Some chip revs need this... */
299	mtmsr r28
300	SYNC
301	lwz r2,_CTR(r1)
302	lwz r0,_LINK(r1)
303	mtctr r2
304	mtlr r0
305	lwz r2,_XER(r1)
306	lwz r0,_CCR(r1)
307	mtspr XER,r2
308	mtcrf 0xFF,r0
309	REST_10GPRS(3, r1)
310	REST_10GPRS(13, r1)
311	REST_8GPRS(23, r1)
312	REST_GPR(31, r1)
313	lwz r2,_NIP(r1) /* Restore environment */
314	lwz r0,_MSR(r1)
315	mtspr SRR0,r2
316	mtspr SRR1,r0
317	lwz r0,GPR0(r1)
318	lwz r2,GPR2(r1)
319	lwz r1,GPR1(r1)
320	SYNC
321	rfi
322
8bde7f77	323
0db5bca8 WD	324	/*
	325	* unsigned int get_immr (unsigned int mask)
	326	*
	327	* return (mask ? (IMMR & mask) : IMMR);
	328	*/
	329	.globl get_immr
	330	get_immr:
	331	mr r4,r3 /* save mask */
	332	mfspr r3, IMMR /* IMMR */
	333	cmpwi 0,r4,0 /* mask != 0 ? */
	334	beq 4f
	335	and r3,r3,r4 /* IMMR & mask */
	336	4:
	337	blr
	338
	339	.globl get_pvr
	340	get_pvr:
	341	mfspr r3, PVR
	342	blr
	343
	344
	345	/------------------------------------------------------------------------------/
	346
	347	/*
	348	* void relocate_code (addr_sp, gd, addr_moni)
	349	*
	350	* This "function" does not return, instead it continues in RAM
	351	* after relocating the monitor code.
	352	*
	353	* r3 = dest
	354	* r4 = src
	355	* r5 = length in bytes
	356	* r6 = cachelinesize
	357	*/
	358	.globl relocate_code
	359	relocate_code:
	360	mr r1, r3 /* Set new stack pointer in SRAM */
	361	mr r9, r4 /* Save copy of global data pointer in SRAM */
	362	mr r10, r5 /* Save copy of monitor destination Address in SRAM */
	363
	364	mr r3, r5 /* Destination Address */
	365	lis r4, CFG_MONITOR_BASE@h /* Source Address */
	366	ori r4, r4, CFG_MONITOR_BASE@l
3b57fe0a WD	367	lwz r5, GOT(__init_end)
3b57fe0a WD	368	sub r5, r5, r4
0db5bca8 WD	369
	370	/*
	371	* Fix GOT pointer:
	372	*
	373	* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
	374	*
	375	* Offset:
	376	*/
	377	sub r15, r10, r4
	378
	379	/* First our own GOT */
	380	add r14, r14, r15
	381	/* the the one used by the C code */
	382	add r30, r30, r15
	383
	384	/*
	385	* Now relocate code
	386	*/
	387
	388	cmplw cr1,r3,r4
	389	addi r0,r5,3
	390	srwi. r0,r0,2
	391	beq cr1,4f /* In place copy is not necessary */
	392	beq 4f /* Protect against 0 count */
	393	mtctr r0
	394	bge cr1,2f
	395
	396	la r8,-4(r4)
	397	la r7,-4(r3)
	398	1: lwzu r0,4(r8)
	399	stwu r0,4(r7)
	400	bdnz 1b
	401	b 4f
	402
	403	2: slwi r0,r0,2
	404	add r8,r4,r0
	405	add r7,r3,r0
	406	3: lwzu r0,-4(r8)
	407	stwu r0,-4(r7)
	408	bdnz 3b
	409
8bde7f77	410	4: sync
0db5bca8 WD	411	isync
	412
	413	/*
	414	* We are done. Do not return, instead branch to second part of board
	415	* initialization, now running from RAM.
	416	*/
	417
	418	addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
	419	mtlr r0
	420	blr
	421
	422	in_ram:
	423
	424	/*
	425	* Relocation Function, r14 point to got2+0x8000
	426	*
8bde7f77 WD	427	* Adjust got2 pointers, no need to check for 0, this code
8bde7f77 WD	428	* already puts a few entries in the table.
0db5bca8 WD	429	*/
	430	li r0,__got2_entries@sectoff@l
	431	la r3,GOT(_GOT2_TABLE_)
	432	lwz r11,GOT(_GOT2_TABLE_)
	433	mtctr r0
	434	sub r11,r3,r11
	435	addi r3,r3,-4
	436	1: lwzu r0,4(r3)
	437	add r0,r0,r11
	438	stw r0,0(r3)
	439	bdnz 1b
	440
	441	/*
8bde7f77	442	* Now adjust the fixups and the pointers to the fixups
0db5bca8 WD	443	* in case we need to move ourselves again.
	444	*/
	445	2: li r0,__fixup_entries@sectoff@l
	446	lwz r3,GOT(_FIXUP_TABLE_)
	447	cmpwi r0,0
	448	mtctr r0
	449	addi r3,r3,-4
	450	beq 4f
	451	3: lwzu r4,4(r3)
	452	lwzux r0,r4,r11
	453	add r0,r0,r11
	454	stw r10,0(r3)
	455	stw r0,0(r4)
	456	bdnz 3b
	457	4:
	458	clear_bss:
	459	/*
	460	* Now clear BSS segment
	461	*/
5d232d0e	462	lwz r3,GOT(__bss_start)
0db5bca8 WD	463	lwz r4,GOT(_end)
	464	cmplw 0, r3, r4
	465	beq 6f
	466
	467	li r0, 0
	468	5:
	469	stw r0, 0(r3)
	470	addi r3, r3, 4
	471	cmplw 0, r3, r4
	472	bne 5b
	473	6:
	474
	475	mr r3, r9 /* Global Data pointer */
	476	mr r4, r10 /* Destination Address */
	477	bl board_init_r
	478
0db5bca8 WD	479	/*
	480	* Copy exception vector code to low memory
	481	*
	482	* r3: dest_addr
	483	* r7: source address, r8: end address, r9: target address
	484	*/
	485	.globl trap_init
	486	trap_init:
	487	lwz r7, GOT(_start)
	488	lwz r8, GOT(_end_of_vectors)
	489
682011ff	490	li r9, 0x100 /* reset vector always at 0x100 */
0db5bca8 WD	491
	492	cmplw 0, r7, r8
	493	bgelr /* return if r7>=r8 - just in case */
	494
	495	mflr r4 /* save link register */
	496	1:
	497	lwz r0, 0(r7)
	498	stw r0, 0(r9)
	499	addi r7, r7, 4
	500	addi r9, r9, 4
	501	cmplw 0, r7, r8
	502	bne 1b
	503
	504	/*
	505	* relocate `hdlr' and `int_return' entries
	506	*/
	507	li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	508	li r8, Alignment - _start + EXC_OFF_SYS_RESET
	509	2:
	510	bl trap_reloc
	511	addi r7, r7, 0x100 /* next exception vector */
	512	cmplw 0, r7, r8
	513	blt 2b
	514
	515	li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	516	bl trap_reloc
	517
	518	li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	519	bl trap_reloc
	520
	521	li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	522	li r8, SystemCall - _start + EXC_OFF_SYS_RESET
	523	3:
	524	bl trap_reloc
	525	addi r7, r7, 0x100 /* next exception vector */
	526	cmplw 0, r7, r8
	527	blt 3b
	528
	529	li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
	530	li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
	531	4:
	532	bl trap_reloc
	533	addi r7, r7, 0x100 /* next exception vector */
	534	cmplw 0, r7, r8
	535	blt 4b
	536
	537	mtlr r4 /* restore link register */
	538	blr
	539
	540	/*
	541	* Function: relocate entries for one exception vector
	542	*/
	543	trap_reloc:
	544	lwz r0, 0(r7) /* hdlr ... */
	545	add r0, r0, r3 /* ... += dest_addr */
	546	stw r0, 0(r7)
	547
	548	lwz r0, 4(r7) /* int_return ... */
	549	add r0, r0, r3 /* ... += dest_addr */
	550	stw r0, 4(r7)
	551
	552	sync
	553	isync
	554
555	blr