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* Make sure HUSH is initialized for running auto-update scripts
[people/ms/u-boot.git] / cpu / mpc5xxx / fec.c
CommitLineData
945af8d7
WD		 1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
7 */
8
9#include <common.h>
10#include <mpc5xxx.h>
11#include <malloc.h>
12#include <net.h>
13#include <miiphy.h>
14#include "sdma.h"
15#include "fec.h"
16
77846748 17/* #define DEBUG 0x28 */
945af8d7
WD		 18
19#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
20 defined(CONFIG_MPC5XXX_FEC)
21
22#if (DEBUG & 0x60)
23static void tfifo_print(mpc5xxx_fec_priv *fec);
24static void rfifo_print(mpc5xxx_fec_priv *fec);
25#endif /* DEBUG */
26
27#if (DEBUG & 0x40)
28static uint32 local_crc32(char *string, unsigned int crc_value, int len);
29#endif
30
77846748
WD		 31typedef struct {
32 uint8 data[1500]; /* actual data */
33 int length; /* actual length */
34 int used; /* buffer in use or not */
35 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
36} NBUF;
37
945af8d7
WD		 38/********************************************************************/
39static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
40{
41 int ix;
42 char *data;
77846748 43 static int once = 0;
945af8d7 44
945af8d7 45 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
77846748
WD		 46 if (!once) {
47 data = (char *)malloc(FEC_MAX_PKT_SIZE);
48 if (data == NULL) {
49 printf ("RBD INIT FAILED\n");
50 return -1;
51 }
52 fec->rbdBase[ix].dataPointer = (uint32)data;
945af8d7
WD		 53 }
54 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
55 fec->rbdBase[ix].dataLength = 0;
945af8d7 56 }
77846748 57 once ++;
945af8d7
WD		 58
59 /*
60 * have the last RBD to close the ring
61 */
62 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
63 fec->rbdIndex = 0;
64
65 return 0;
66}
67
68/********************************************************************/
69static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
70{
71 int ix;
72
73 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
74 fec->tbdBase[ix].status = 0;
75 }
76
77 /*
78 * Have the last TBD to close the ring
79 */
80 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
81
82 /*
83 * Initialize some indices
84 */
85 fec->tbdIndex = 0;
86 fec->usedTbdIndex = 0;
87 fec->cleanTbdNum = FEC_TBD_NUM;
88}
89
90/********************************************************************/
91static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, FEC_RBD * pRbd)
92{
93 /*
94 * Reset buffer descriptor as empty
95 */
96 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
97 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
98 else
99 pRbd->status = FEC_RBD_EMPTY;
100
101 pRbd->dataLength = 0;
102
103 /*
104 * Now, we have an empty RxBD, restart the SmartDMA receive task
105 */
106 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
107
108 /*
109 * Increment BD count
110 */
111 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
112}
113
114/********************************************************************/
115static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
116{
117 FEC_TBD *pUsedTbd;
118
119#if (DEBUG & 0x1)
120 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
121 fec->cleanTbdNum, fec->usedTbdIndex);
122#endif
123
124 /*
125 * process all the consumed TBDs
126 */
127 while (fec->cleanTbdNum < FEC_TBD_NUM) {
128 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
129 if (pUsedTbd->status & FEC_TBD_READY) {
130#if (DEBUG & 0x20)
131 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
132#endif
133 return;
134 }
135
136 /*
137 * clean this buffer descriptor
138 */
139 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
140 pUsedTbd->status = FEC_TBD_WRAP;
141 else
142 pUsedTbd->status = 0;
143
144 /*
145 * update some indeces for a correct handling of the TBD ring
146 */
147 fec->cleanTbdNum++;
148 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
149 }
150}
151
152/********************************************************************/
153static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
154{
155 uint8 currByte; /* byte for which to compute the CRC */
156 int byte; /* loop - counter */
157 int bit; /* loop - counter */
158 uint32 crc = 0xffffffff; /* initial value */
159
160 /*
161 * The algorithm used is the following:
162 * we loop on each of the six bytes of the provided address,
163 * and we compute the CRC by left-shifting the previous
164 * value by one position, so that each bit in the current
165 * byte of the address may contribute the calculation. If
166 * the latter and the MSB in the CRC are different, then
167 * the CRC value so computed is also ex-ored with the
168 * "polynomium generator". The current byte of the address
169 * is also shifted right by one bit at each iteration.
170 * This is because the CRC generatore in hardware is implemented
171 * as a shift-register with as many ex-ores as the radixes
172 * in the polynomium. This suggests that we represent the
173 * polynomiumm itself as a 32-bit constant.
174 */
175 for (byte = 0; byte < 6; byte++) {
176 currByte = mac[byte];
177 for (bit = 0; bit < 8; bit++) {
178 if ((currByte & 0x01) ^ (crc & 0x01)) {
179 crc >>= 1;
180 crc = crc ^ 0xedb88320;
181 } else {
182 crc >>= 1;
183 }
184 currByte >>= 1;
185 }
186 }
187
188 crc = crc >> 26;
189
190 /*
191 * Set individual hash table register
192 */
193 if (crc >= 32) {
194 fec->eth->iaddr1 = (1 << (crc - 32));
195 fec->eth->iaddr2 = 0;
196 } else {
197 fec->eth->iaddr1 = 0;
198 fec->eth->iaddr2 = (1 << crc);
199 }
200
201 /*
202 * Set physical address
203 */
204 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
205 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
206}
207
208/********************************************************************/
209static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
210{
7152b1d0 211 DECLARE_GLOBAL_DATA_PTR;
945af8d7
WD		 212 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
213 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
214 const uint8 phyAddr = 0; /* Only one PHY */
215
216#if (DEBUG & 0x1)
217 printf ("mpc5xxx_fec_init... Begin\n");
218#endif
219
220 /*
221 * Initialize RxBD/TxBD rings
222 */
223 mpc5xxx_fec_rbd_init(fec);
224 mpc5xxx_fec_tbd_init(fec);
225
226 /*
227 * Initialize GPIO pins
228 */
229 if (fec->xcv_type == SEVENWIRE) {
230 /* 10MBit with 7-wire operation */
231 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
232 } else {
233 /* 100MBit with MD operation */
234 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
235 }
236
237 /*
238 * Clear FEC-Lite interrupt event register(IEVENT)
239 */
240 fec->eth->ievent = 0xffffffff;
241
242 /*
243 * Set interrupt mask register
244 */
245 fec->eth->imask = 0x00000000;
246
247 /*
248 * Set FEC-Lite receive control register(R_CNTRL):
249 */
250 if (fec->xcv_type == SEVENWIRE) {
251 /*
252 * Frame length=1518; 7-wire mode
253 */
254 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
255 } else {
256 /*
257 * Frame length=1518; MII mode;
258 */
259 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
260 }
261
262 if (fec->xcv_type == SEVENWIRE) {
263 /*
264 * Set FEC-Lite transmit control register(X_CNTRL):
265 */
266 /*fec->eth->x_cntrl = 0x00000002; */ /* half-duplex, heartbeat */
267 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
268 } else {
269 /*fec->eth->x_cntrl = 0x00000006; */ /* full-duplex, heartbeat */
270 fec->eth->x_cntrl = 0x00000004; /* full-duplex, heartbeat disabled */
271
272 /*
7152b1d0 273 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
945af8d7
WD		 274 * and do not drop the Preamble.
275 */
7152b1d0 276 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
945af8d7
WD		 277 }
278
279 /*
280 * Set Opcode/Pause Duration Register
281 */
282 fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */
283
284 /*
285 * Set Rx FIFO alarm and granularity value
286 */
287 fec->eth->rfifo_cntrl = 0x0c000000;
288 fec->eth->rfifo_alarm = 0x0000030c;
289#if (DEBUG & 0x22)
290 if (fec->eth->rfifo_status & 0x00700000 ) {
291 printf("mpc5xxx_fec_init() RFIFO error\n");
292 }
293#endif
294
295 /*
296 * Set Tx FIFO granularity value
297 */
298 fec->eth->tfifo_cntrl = 0x0c000000;
299#if (DEBUG & 0x2)
300 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
301 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
302#endif
303
304 /*
305 * Set transmit fifo watermark register(X_WMRK), default = 64
306 */
307 fec->eth->tfifo_alarm = 0x00000080;
308 fec->eth->x_wmrk = 0x2;
309
310 /*
311 * Set individual address filter for unicast address
312 * and set physical address registers.
313 */
314 mpc5xxx_fec_set_hwaddr(fec, dev->enetaddr);
315
316 /*
317 * Set multicast address filter
318 */
319 fec->eth->gaddr1 = 0x00000000;
320 fec->eth->gaddr2 = 0x00000000;
321
322 /*
323 * Turn ON cheater FSM: ????
324 */
325 fec->eth->xmit_fsm = 0x03000000;
326
327#if defined(CONFIG_MPC5200)
328 /*
329 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
330 * work w/ the current receive task.
331 */
332 sdma->PtdCntrl |= 0x00000001;
333#endif
334
335 /*
336 * Set priority of different initiators
337 */
338 sdma->IPR0 = 7; /* always */
339 sdma->IPR3 = 6; /* Eth RX */
340 sdma->IPR4 = 5; /* Eth Tx */
341
342 /*
343 * Clear SmartDMA task interrupt pending bits
344 */
345 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
346
945af8d7
WD		 347 /*
348 * Initialize SmartDMA parameters stored in SRAM
349 */
350 *(int *)FEC_TBD_BASE = (int)fec->tbdBase;
351 *(int *)FEC_RBD_BASE = (int)fec->rbdBase;
352 *(int *)FEC_TBD_NEXT = (int)fec->tbdBase;
353 *(int *)FEC_RBD_NEXT = (int)fec->rbdBase;
354
355 if (fec->xcv_type != SEVENWIRE) {
356 /*
357 * Initialize PHY(LXT971A):
358 *
359 * Generally, on power up, the LXT971A reads its configuration
360 * pins to check for forced operation, If not cofigured for
361 * forced operation, it uses auto-negotiation/parallel detection
362 * to automatically determine line operating conditions.
363 * If the PHY device on the other side of the link supports
364 * auto-negotiation, the LXT971A auto-negotiates with it
365 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
366 * support auto-negotiation, the LXT971A automatically detects
367 * the presence of either link pulses(10Mbps PHY) or Idle
368 * symbols(100Mbps) and sets its operating conditions accordingly.
369 *
370 * When auto-negotiation is controlled by software, the following
371 * steps are recommended.
372 *
373 * Note:
374 * The physical address is dependent on hardware configuration.
375 *
376 */
377 int timeout = 1;
378 uint16 phyStatus;
379
380 /*
381 * Reset PHY, then delay 300ns
382 */
383 miiphy_write(phyAddr, 0x0, 0x8000);
384 udelay(1000);
385
386 if (fec->xcv_type == MII10) {
387 /*
388 * Force 10Base-T, FDX operation
389 */
a57106fc 390#if (DEBUG & 0x2)
945af8d7 391 printf("Forcing 10 Mbps ethernet link... ");
a57106fc 392#endif
945af8d7
WD		 393 miiphy_read(phyAddr, 0x1, &phyStatus);
394 /*
395 miiphy_write(fec, phyAddr, 0x0, 0x0100);
396 */
397 miiphy_write(phyAddr, 0x0, 0x0180);
398
399 timeout = 20;
400 do { /* wait for link status to go down */
401 udelay(10000);
402 if ((timeout--) == 0) {
403#if (DEBUG & 0x2)
404 printf("hmmm, should not have waited...");
405#endif
406 break;
407 }
408 miiphy_read(phyAddr, 0x1, &phyStatus);
409#if (DEBUG & 0x2)
410 printf("=");
411#endif
412 } while ((phyStatus & 0x0004)); /* !link up */
413
414 timeout = 1000;
415 do { /* wait for link status to come back up */
416 udelay(10000);
417 if ((timeout--) == 0) {
418 printf("failed. Link is down.\n");
419 break;
420 }
421 miiphy_read(phyAddr, 0x1, &phyStatus);
422#if (DEBUG & 0x2)
423 printf("+");
424#endif
425 } while (!(phyStatus & 0x0004)); /* !link up */
426
ab209d51 427#if (DEBUG & 0x2)
945af8d7 428 printf ("done.\n");
ab209d51 429#endif
945af8d7
WD		 430 } else { /* MII100 */
431 /*
432 * Set the auto-negotiation advertisement register bits
433 */
434 miiphy_write(phyAddr, 0x4, 0x01e1);
435
436 /*
437 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
438 */
439 miiphy_write(phyAddr, 0x0, 0x1200);
440
441 /*
442 * Wait for AN completion
443 */
444 timeout = 5000;
445 do {
446 udelay(1000);
447
448 if ((timeout--) == 0) {
449#if (DEBUG & 0x2)
450 printf("PHY auto neg 0 failed...\n");
451#endif
452 return -1;
453 }
454
455 if (miiphy_read(phyAddr, 0x1, &phyStatus) != 0) {
456#if (DEBUG & 0x2)
457 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
458#endif
459 return -1;
460 }
461 } while ((phyStatus & 0x0020) != 0x0020);
462
463#if (DEBUG & 0x2)
464 printf("PHY auto neg complete! \n");
465#endif
466 }
467
468 }
469
470 /*
471 * Enable FEC-Lite controller
472 */
473 fec->eth->ecntrl |= 0x00000006;
474
475 if (fec->xcv_type != SEVENWIRE) {
476#if (DEBUG & 0x2)
477 uint16 phyStatus, i;
478 uint8 phyAddr = 0;
479
480 for (i = 0; i < 9; i++) {
481 miiphy_read(phyAddr, i, &phyStatus);
482 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
483 }
484 for (i = 16; i < 21; i++) {
485 miiphy_read(phyAddr, i, &phyStatus);
486 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
487 }
488#endif
489 }
490 /*
491 * Enable SmartDMA receive task
492 */
493 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
494
495#if (DEBUG & 0x1)
496 printf("mpc5xxx_fec_init... Done \n");
497#endif
498
013dc8d9 499 return 1;
945af8d7
WD		 500}
501
502/********************************************************************/
503static void mpc5xxx_fec_halt(struct eth_device *dev)
504{
77846748 505#if defined(CONFIG_MPC5200)
945af8d7 506 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
77846748
WD		 507#endif
508 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
945af8d7
WD		 509 int counter = 0xffff;
510
511#if (DEBUG & 0x2)
512 if (fec->xcv_type != SEVENWIRE) {
513 uint16 phyStatus, i;
514 uint8 phyAddr = 0;
515
516 for (i = 0; i < 9; i++) {
517 miiphy_read(phyAddr, i, &phyStatus);
518 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
519 }
520 for (i = 16; i < 21; i++) {
521 miiphy_read(phyAddr, i, &phyStatus);
522 printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
523 }
524 }
525#endif
526
527
528 /*
529 * mask FEC chip interrupts
530 */
531 fec->eth->imask = 0;
532
533 /*
534 * issue graceful stop command to the FEC transmitter if necessary
535 */
536 fec->eth->x_cntrl |= 0x00000001;
537
538 /*
539 * wait for graceful stop to register
540 */
541 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
542
945af8d7
WD		 543 /*
544 * Disable SmartDMA tasks
545 */
546 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
547 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
548
549#if defined(CONFIG_MPC5200)
550 /*
551 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
552 * done. It doesn't work w/ the current receive task.
553 */
554 sdma->PtdCntrl &= ~0x00000001;
555#endif
556
557 /*
558 * Disable the Ethernet Controller
559 */
560 fec->eth->ecntrl &= 0xfffffffd;
561
562 /*
563 * Clear FIFO status registers
564 */
565 fec->eth->rfifo_status &= 0x00700000;
566 fec->eth->tfifo_status &= 0x00700000;
567
568 fec->eth->reset_cntrl = 0x01000000;
569
570 /*
571 * Issue a reset command to the FEC chip
572 */
573 fec->eth->ecntrl |= 0x1;
574
575 /*
576 * wait at least 16 clock cycles
577 */
578 udelay(10);
579
580#if (DEBUG & 0x3)
581 printf("Ethernet task stopped\n");
582#endif
583}
584
585#if (DEBUG & 0x60)
586/********************************************************************/
587
588static void tfifo_print(mpc5xxx_fec_priv *fec)
589{
590 uint16 phyAddr = 0;
591 uint16 phyStatus;
592
593 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
594 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
595
596 miiphy_read(phyAddr, 0x1, &phyStatus);
597 printf("\nphyStatus: 0x%04x\n", phyStatus);
598 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
599 printf("ievent: 0x%08x\n", fec->eth->ievent);
600 printf("x_status: 0x%08x\n", fec->eth->x_status);
601 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
602
603 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
604 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
605 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
606 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
607 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
608 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
609 }
610}
611
612static void rfifo_print(mpc5xxx_fec_priv *fec)
613{
614 uint16 phyAddr = 0;
615 uint16 phyStatus;
616
617 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
618 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
619
620 miiphy_read(phyAddr, 0x1, &phyStatus);
621 printf("\nphyStatus: 0x%04x\n", phyStatus);
622 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
623 printf("ievent: 0x%08x\n", fec->eth->ievent);
624 printf("x_status: 0x%08x\n", fec->eth->x_status);
625 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
626
627 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
628 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
629 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
630 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
631 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
632 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
633 }
634}
635#endif /* DEBUG */
636
637/********************************************************************/
638
639static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
640 int data_length)
641{
642 /*
643 * This routine transmits one frame. This routine only accepts
644 * 6-byte Ethernet addresses.
645 */
646 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
647 FEC_TBD *pTbd;
648
649#if (DEBUG & 0x20)
650 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
651 tfifo_print(fec);
652#endif
653
654 /*
655 * Clear Tx BD ring at first
656 */
657 mpc5xxx_fec_tbd_scrub(fec);
658
659 /*
660 * Check for valid length of data.
661 */
662 if ((data_length > 1500) || (data_length <= 0)) {
663 return -1;
664 }
665
666 /*
667 * Check the number of vacant TxBDs.
668 */
669 if (fec->cleanTbdNum < 1) {
670#if (DEBUG & 0x20)
671 printf("No available TxBDs ...\n");
672#endif
673 return -1;
674 }
675
676 /*
677 * Get the first TxBD to send the mac header
678 */
679 pTbd = &fec->tbdBase[fec->tbdIndex];
680 pTbd->dataLength = data_length;
681 pTbd->dataPointer = (uint32)eth_data;
77846748 682 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
945af8d7
WD		 683 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
684
685#if (DEBUG & 0x100)
686 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
687#endif
688
689 /*
690 * Kick the MII i/f
691 */
692 if (fec->xcv_type != SEVENWIRE) {
693 uint16 phyStatus;
694 miiphy_read(0, 0x1, &phyStatus);
695 }
696
697 /*
698 * Enable SmartDMA transmit task
699 */
700
701#if (DEBUG & 0x20)
702 tfifo_print(fec);
703#endif
704 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
705#if (DEBUG & 0x20)
706 tfifo_print(fec);
707#endif
708#if (DEBUG & 0x8)
709 printf( "+" );
710#endif
711
712 fec->cleanTbdNum -= 1;
713
714#if (DEBUG & 0x129) && (DEBUG & 0x80000000)
715 printf ("smartDMA ethernet Tx task enabled\n");
716#endif
717 /*
718 * wait until frame is sent .
719 */
720 while (pTbd->status & FEC_TBD_READY) {
721 udelay(10);
722#if (DEBUG & 0x8)
723 printf ("TDB status = %04x\n", pTbd->status);
724#endif
725 }
726
727 return 0;
728}
729
730
731/********************************************************************/
732static int mpc5xxx_fec_recv(struct eth_device *dev)
733{
734 /*
735 * This command pulls one frame from the card
736 */
737 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
738 FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
739 unsigned long ievent;
77846748
WD		 740 int frame_length, len = 0;
741 NBUF *frame;
742 char buff[FEC_MAX_PKT_SIZE];
945af8d7
WD		 743
744#if (DEBUG & 0x1)
745 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
746#endif
747#if (DEBUG & 0x8)
748 printf( "-" );
749#endif
750
751 /*
752 * Check if any critical events have happened
753 */
754 ievent = fec->eth->ievent;
755 fec->eth->ievent = ievent;
756 if (ievent & 0x20060000) {
757 /* BABT, Rx/Tx FIFO errors */
758 mpc5xxx_fec_halt(dev);
759 mpc5xxx_fec_init(dev, NULL);
760 return 0;
761 }
762 if (ievent & 0x80000000) {
763 /* Heartbeat error */
764 fec->eth->x_cntrl |= 0x00000001;
765 }
766 if (ievent & 0x10000000) {
767 /* Graceful stop complete */
768 if (fec->eth->x_cntrl & 0x00000001) {
769 mpc5xxx_fec_halt(dev);
770 fec->eth->x_cntrl &= ~0x00000001;
771 mpc5xxx_fec_init(dev, NULL);
772 }
773 }
774
77846748
WD		 775 if (!(pRbd->status & FEC_RBD_EMPTY)) {
776 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
777 ((pRbd->dataLength - 4) > 14)) {
945af8d7 778
77846748
WD		 779 /*
780 * Get buffer address and size
781 */
782 frame = (NBUF *)pRbd->dataPointer;
783 frame_length = pRbd->dataLength - 4;
784
785#if (DEBUG & 0x20)
786 {
787 int i;
788 printf("recv data hdr:");
789 for (i = 0; i < 14; i++)
790 printf("%x ", *(frame->head + i));
791 printf("\n");
792 }
945af8d7 793#endif
77846748
WD		 794 /*
795 * Fill the buffer and pass it to upper layers
796 */
797 memcpy(buff, frame->head, 14);
798 memcpy(buff + 14, frame->data, frame_length);
799 NetReceive(buff, frame_length);
800 len = frame_length;
801 }
802 /*
803 * Reset buffer descriptor as empty
804 */
805 mpc5xxx_fec_rbd_clean(fec, pRbd);
945af8d7 806 }
77846748
WD		 807 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
808 return len;
945af8d7
WD		 809}
810
811
812/********************************************************************/
813int mpc5xxx_fec_initialize(bd_t * bis)
814{
815 mpc5xxx_fec_priv *fec;
816 struct eth_device *dev;
12f34241
WD		 817 char *tmp, *end;
818 char env_enetaddr[6];
819 int i;
945af8d7
WD		 820
821 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
822 dev = (struct eth_device *)malloc(sizeof(*dev));
12f34241 823 memset(dev, 0, sizeof *dev);
945af8d7
WD		 824
825 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
826 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
827 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
828#ifdef CONFIG_ICECUBE
a57106fc 829#ifndef CONFIG_FEC_10MBIT
945af8d7 830 fec->xcv_type = MII100;
a57106fc
WD		 831#else
832 fec->xcv_type = MII10;
833#endif
834#else
835#error fec->xcv_type not initialized.
945af8d7
WD		 836#endif
837
838 dev->priv = (void *)fec;
839 dev->iobase = MPC5XXX_FEC;
840 dev->init = mpc5xxx_fec_init;
841 dev->halt = mpc5xxx_fec_halt;
842 dev->send = mpc5xxx_fec_send;
843 dev->recv = mpc5xxx_fec_recv;
844
77846748 845 sprintf(dev->name, "FEC ETHERNET");
945af8d7
WD		 846 eth_register(dev);
847
12f34241
WD		 848 /*
849 * Try to set the mac address now. The fec mac address is
850 * a garbage after reset. When not using fec for booting
851 * the Linux fec driver will try to work with this garbage.
852 */
853 tmp = getenv("ethaddr");
854 if (tmp) {
855 for (i=0; i<6; i++) {
856 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
857 if (tmp)
858 tmp = (*end) ? end+1 : end;
859 }
860 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
861 }
862
945af8d7
WD		 863 return 1;
864}
865
866/* MII-interface related functions */
867/********************************************************************/
868int miiphy_read(uint8 phyAddr, uint8 regAddr, uint16 * retVal)
869{
870 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
871 uint32 reg; /* convenient holder for the PHY register */
872 uint32 phy; /* convenient holder for the PHY */
873 int timeout = 0xffff;
874
875 /*
876 * reading from any PHY's register is done by properly
877 * programming the FEC's MII data register.
878 */
879 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
880 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
881
882 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
883
884 /*
885 * wait for the related interrupt
886 */
887 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
888
889 if (timeout == 0) {
890#if (DEBUG & 0x2)
891 printf ("Read MDIO failed...\n");
892#endif
893 return -1;
894 }
895
896 /*
897 * clear mii interrupt bit
898 */
899 eth->ievent = 0x00800000;
900
901 /*
902 * it's now safe to read the PHY's register
903 */
904 *retVal = (uint16) eth->mii_data;
905
906 return 0;
907}
908
909/********************************************************************/
910int miiphy_write(uint8 phyAddr, uint8 regAddr, uint16 data)
911{
912 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
913 uint32 reg; /* convenient holder for the PHY register */
914 uint32 phy; /* convenient holder for the PHY */
915 int timeout = 0xffff;
916
917 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
918 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
919
920 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
921 FEC_MII_DATA_TA | phy | reg | data);
922
923 /*
924 * wait for the MII interrupt
925 */
926 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
927
928 if (timeout == 0) {
929#if (DEBUG & 0x2)
930 printf ("Write MDIO failed...\n");
931#endif
932 return -1;
933 }
934
935 /*
936 * clear MII interrupt bit
937 */
938 eth->ievent = 0x00800000;
939
940 return 0;
941}
942
943#if (DEBUG & 0x40)
944static uint32 local_crc32(char *string, unsigned int crc_value, int len)
945{
946 int i;
947 char c;
948 unsigned int crc, count;
949
950 /*
951 * crc32 algorithm
952 */
953 /*
954 * crc = 0xffffffff; * The initialized value should be 0xffffffff
955 */
956 crc = crc_value;
957
958 for (i = len; --i >= 0;) {
959 c = *string++;
960 for (count = 0; count < 8; count++) {
961 if ((c & 0x01) ^ (crc & 0x01)) {
962 crc >>= 1;
963 crc = crc ^ 0xedb88320;
964 } else {
965 crc >>= 1;
966 }
967 c >>= 1;
968 }
969 }
970
971 /*
972 * In big endian system, do byte swaping for crc value
973 */
974 /**/ return crc;
975}
976#endif /* DEBUG */
977
978#endif /* CONFIG_MPC5XXX_FEC */
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