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[people/ms/u-boot.git] / cpu / mpc5xxx / fec.c
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945af8d7
WD		 1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
7 */
8
9#include <common.h>
10#include <mpc5xxx.h>
11#include <malloc.h>
12#include <net.h>
13#include <miiphy.h>
14#include "sdma.h"
15#include "fec.h"
16
77846748 17/* #define DEBUG 0x28 */
945af8d7
WD		 18
19#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
20 defined(CONFIG_MPC5XXX_FEC)
21
22#if (DEBUG & 0x60)
23static void tfifo_print(mpc5xxx_fec_priv *fec);
24static void rfifo_print(mpc5xxx_fec_priv *fec);
25#endif /* DEBUG */
26
27#if (DEBUG & 0x40)
28static uint32 local_crc32(char *string, unsigned int crc_value, int len);
29#endif
30
77846748
WD		 31typedef struct {
32 uint8 data[1500]; /* actual data */
33 int length; /* actual length */
34 int used; /* buffer in use or not */
35 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
36} NBUF;
37
945af8d7
WD		 38/********************************************************************/
39static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
40{
41 int ix;
42 char *data;
77846748 43 static int once = 0;
945af8d7 44
945af8d7 45 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
77846748
WD		 46 if (!once) {
47 data = (char *)malloc(FEC_MAX_PKT_SIZE);
48 if (data == NULL) {
49 printf ("RBD INIT FAILED\n");
50 return -1;
51 }
52 fec->rbdBase[ix].dataPointer = (uint32)data;
945af8d7
WD		 53 }
54 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
55 fec->rbdBase[ix].dataLength = 0;
945af8d7 56 }
77846748 57 once ++;
945af8d7
WD		 58
59 /*
60 * have the last RBD to close the ring
61 */
62 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
63 fec->rbdIndex = 0;
64
65 return 0;
66}
67
68/********************************************************************/
69static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
70{
71 int ix;
72
73 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
74 fec->tbdBase[ix].status = 0;
75 }
76
77 /*
78 * Have the last TBD to close the ring
79 */
80 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
81
82 /*
83 * Initialize some indices
84 */
85 fec->tbdIndex = 0;
86 fec->usedTbdIndex = 0;
87 fec->cleanTbdNum = FEC_TBD_NUM;
88}
89
90/********************************************************************/
91static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, FEC_RBD * pRbd)
92{
93 /*
94 * Reset buffer descriptor as empty
95 */
96 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
97 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
98 else
99 pRbd->status = FEC_RBD_EMPTY;
100
101 pRbd->dataLength = 0;
102
103 /*
104 * Now, we have an empty RxBD, restart the SmartDMA receive task
105 */
106 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
107
108 /*
109 * Increment BD count
110 */
111 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
112}
113
114/********************************************************************/
115static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
116{
117 FEC_TBD *pUsedTbd;
118
119#if (DEBUG & 0x1)
120 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
121 fec->cleanTbdNum, fec->usedTbdIndex);
122#endif
123
124 /*
125 * process all the consumed TBDs
126 */
127 while (fec->cleanTbdNum < FEC_TBD_NUM) {
128 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
129 if (pUsedTbd->status & FEC_TBD_READY) {
130#if (DEBUG & 0x20)
131 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
132#endif
133 return;
134 }
135
136 /*
137 * clean this buffer descriptor
138 */
139 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
140 pUsedTbd->status = FEC_TBD_WRAP;
141 else
142 pUsedTbd->status = 0;
143
144 /*
145 * update some indeces for a correct handling of the TBD ring
146 */
147 fec->cleanTbdNum++;
148 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
149 }
150}
151
152/********************************************************************/
153static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
154{
155 uint8 currByte; /* byte for which to compute the CRC */
156 int byte; /* loop - counter */
157 int bit; /* loop - counter */
158 uint32 crc = 0xffffffff; /* initial value */
159
160 /*
161 * The algorithm used is the following:
162 * we loop on each of the six bytes of the provided address,
163 * and we compute the CRC by left-shifting the previous
164 * value by one position, so that each bit in the current
165 * byte of the address may contribute the calculation. If
166 * the latter and the MSB in the CRC are different, then
167 * the CRC value so computed is also ex-ored with the
168 * "polynomium generator". The current byte of the address
169 * is also shifted right by one bit at each iteration.
170 * This is because the CRC generatore in hardware is implemented
171 * as a shift-register with as many ex-ores as the radixes
172 * in the polynomium. This suggests that we represent the
173 * polynomiumm itself as a 32-bit constant.
174 */
175 for (byte = 0; byte < 6; byte++) {
176 currByte = mac[byte];
177 for (bit = 0; bit < 8; bit++) {
178 if ((currByte & 0x01) ^ (crc & 0x01)) {
179 crc >>= 1;
180 crc = crc ^ 0xedb88320;
181 } else {
182 crc >>= 1;
183 }
184 currByte >>= 1;
185 }
186 }
187
188 crc = crc >> 26;
189
190 /*
191 * Set individual hash table register
192 */
193 if (crc >= 32) {
194 fec->eth->iaddr1 = (1 << (crc - 32));
195 fec->eth->iaddr2 = 0;
196 } else {
197 fec->eth->iaddr1 = 0;
198 fec->eth->iaddr2 = (1 << crc);
199 }
200
201 /*
202 * Set physical address
203 */
204 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
205 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
206}
207
208/********************************************************************/
209static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
210{
211 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
212 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
213 const uint8 phyAddr = 0; /* Only one PHY */
214
215#if (DEBUG & 0x1)
216 printf ("mpc5xxx_fec_init... Begin\n");
217#endif
218
219 /*
220 * Initialize RxBD/TxBD rings
221 */
222 mpc5xxx_fec_rbd_init(fec);
223 mpc5xxx_fec_tbd_init(fec);
224
225 /*
226 * Initialize GPIO pins
227 */
228 if (fec->xcv_type == SEVENWIRE) {
229 /* 10MBit with 7-wire operation */
230 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
231 } else {
232 /* 100MBit with MD operation */
233 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
234 }
235
236 /*
237 * Clear FEC-Lite interrupt event register(IEVENT)
238 */
239 fec->eth->ievent = 0xffffffff;
240
241 /*
242 * Set interrupt mask register
243 */
244 fec->eth->imask = 0x00000000;
245
246 /*
247 * Set FEC-Lite receive control register(R_CNTRL):
248 */
249 if (fec->xcv_type == SEVENWIRE) {
250 /*
251 * Frame length=1518; 7-wire mode
252 */
253 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
254 } else {
255 /*
256 * Frame length=1518; MII mode;
257 */
258 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
259 }
260
261 if (fec->xcv_type == SEVENWIRE) {
262 /*
263 * Set FEC-Lite transmit control register(X_CNTRL):
264 */
265 /*fec->eth->x_cntrl = 0x00000002; */ /* half-duplex, heartbeat */
266 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
267 } else {
268 /*fec->eth->x_cntrl = 0x00000006; */ /* full-duplex, heartbeat */
269 fec->eth->x_cntrl = 0x00000004; /* full-duplex, heartbeat disabled */
270
271 /*
272 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock(25Mhz)
273 * and do not drop the Preamble.
274 */
275 fec->eth->mii_speed = (0x5 << 1); /* No MII for 7-wire mode */
276 }
277
278 /*
279 * Set Opcode/Pause Duration Register
280 */
281 fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */
282
283 /*
284 * Set Rx FIFO alarm and granularity value
285 */
286 fec->eth->rfifo_cntrl = 0x0c000000;
287 fec->eth->rfifo_alarm = 0x0000030c;
288#if (DEBUG & 0x22)
289 if (fec->eth->rfifo_status & 0x00700000 ) {
290 printf("mpc5xxx_fec_init() RFIFO error\n");
291 }
292#endif
293
294 /*
295 * Set Tx FIFO granularity value
296 */
297 fec->eth->tfifo_cntrl = 0x0c000000;
298#if (DEBUG & 0x2)
299 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
300 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
301#endif
302
303 /*
304 * Set transmit fifo watermark register(X_WMRK), default = 64
305 */
306 fec->eth->tfifo_alarm = 0x00000080;
307 fec->eth->x_wmrk = 0x2;
308
309 /*
310 * Set individual address filter for unicast address
311 * and set physical address registers.
312 */
313 mpc5xxx_fec_set_hwaddr(fec, dev->enetaddr);
314
315 /*
316 * Set multicast address filter
317 */
318 fec->eth->gaddr1 = 0x00000000;
319 fec->eth->gaddr2 = 0x00000000;
320
321 /*
322 * Turn ON cheater FSM: ????
323 */
324 fec->eth->xmit_fsm = 0x03000000;
325
326#if defined(CONFIG_MPC5200)
327 /*
328 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
329 * work w/ the current receive task.
330 */
331 sdma->PtdCntrl |= 0x00000001;
332#endif
333
334 /*
335 * Set priority of different initiators
336 */
337 sdma->IPR0 = 7; /* always */
338 sdma->IPR3 = 6; /* Eth RX */
339 sdma->IPR4 = 5; /* Eth Tx */
340
341 /*
342 * Clear SmartDMA task interrupt pending bits
343 */
344 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
345
945af8d7
WD		 346 /*
347 * Initialize SmartDMA parameters stored in SRAM
348 */
349 *(int *)FEC_TBD_BASE = (int)fec->tbdBase;
350 *(int *)FEC_RBD_BASE = (int)fec->rbdBase;
351 *(int *)FEC_TBD_NEXT = (int)fec->tbdBase;
352 *(int *)FEC_RBD_NEXT = (int)fec->rbdBase;
353
354 if (fec->xcv_type != SEVENWIRE) {
355 /*
356 * Initialize PHY(LXT971A):
357 *
358 * Generally, on power up, the LXT971A reads its configuration
359 * pins to check for forced operation, If not cofigured for
360 * forced operation, it uses auto-negotiation/parallel detection
361 * to automatically determine line operating conditions.
362 * If the PHY device on the other side of the link supports
363 * auto-negotiation, the LXT971A auto-negotiates with it
364 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
365 * support auto-negotiation, the LXT971A automatically detects
366 * the presence of either link pulses(10Mbps PHY) or Idle
367 * symbols(100Mbps) and sets its operating conditions accordingly.
368 *
369 * When auto-negotiation is controlled by software, the following
370 * steps are recommended.
371 *
372 * Note:
373 * The physical address is dependent on hardware configuration.
374 *
375 */
376 int timeout = 1;
377 uint16 phyStatus;
378
379 /*
380 * Reset PHY, then delay 300ns
381 */
382 miiphy_write(phyAddr, 0x0, 0x8000);
383 udelay(1000);
384
385 if (fec->xcv_type == MII10) {
386 /*
387 * Force 10Base-T, FDX operation
388 */
389 printf("Forcing 10 Mbps ethernet link... ");
390 miiphy_read(phyAddr, 0x1, &phyStatus);
391 /*
392 miiphy_write(fec, phyAddr, 0x0, 0x0100);
393 */
394 miiphy_write(phyAddr, 0x0, 0x0180);
395
396 timeout = 20;
397 do { /* wait for link status to go down */
398 udelay(10000);
399 if ((timeout--) == 0) {
400#if (DEBUG & 0x2)
401 printf("hmmm, should not have waited...");
402#endif
403 break;
404 }
405 miiphy_read(phyAddr, 0x1, &phyStatus);
406#if (DEBUG & 0x2)
407 printf("=");
408#endif
409 } while ((phyStatus & 0x0004)); /* !link up */
410
411 timeout = 1000;
412 do { /* wait for link status to come back up */
413 udelay(10000);
414 if ((timeout--) == 0) {
415 printf("failed. Link is down.\n");
416 break;
417 }
418 miiphy_read(phyAddr, 0x1, &phyStatus);
419#if (DEBUG & 0x2)
420 printf("+");
421#endif
422 } while (!(phyStatus & 0x0004)); /* !link up */
423
424 printf ("done.\n");
425 } else { /* MII100 */
426 /*
427 * Set the auto-negotiation advertisement register bits
428 */
429 miiphy_write(phyAddr, 0x4, 0x01e1);
430
431 /*
432 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
433 */
434 miiphy_write(phyAddr, 0x0, 0x1200);
435
436 /*
437 * Wait for AN completion
438 */
439 timeout = 5000;
440 do {
441 udelay(1000);
442
443 if ((timeout--) == 0) {
444#if (DEBUG & 0x2)
445 printf("PHY auto neg 0 failed...\n");
446#endif
447 return -1;
448 }
449
450 if (miiphy_read(phyAddr, 0x1, &phyStatus) != 0) {
451#if (DEBUG & 0x2)
452 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
453#endif
454 return -1;
455 }
456 } while ((phyStatus & 0x0020) != 0x0020);
457
458#if (DEBUG & 0x2)
459 printf("PHY auto neg complete! \n");
460#endif
461 }
462
463 }
464
465 /*
466 * Enable FEC-Lite controller
467 */
468 fec->eth->ecntrl |= 0x00000006;
469
470 if (fec->xcv_type != SEVENWIRE) {
471#if (DEBUG & 0x2)
472 uint16 phyStatus, i;
473 uint8 phyAddr = 0;
474
475 for (i = 0; i < 9; i++) {
476 miiphy_read(phyAddr, i, &phyStatus);
477 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
478 }
479 for (i = 16; i < 21; i++) {
480 miiphy_read(phyAddr, i, &phyStatus);
481 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
482 }
483#endif
484 }
485 /*
486 * Enable SmartDMA receive task
487 */
488 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
489
490#if (DEBUG & 0x1)
491 printf("mpc5xxx_fec_init... Done \n");
492#endif
493
494 return 0;
495}
496
497/********************************************************************/
498static void mpc5xxx_fec_halt(struct eth_device *dev)
499{
77846748 500#if defined(CONFIG_MPC5200)
945af8d7 501 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
77846748
WD		 502#endif
503 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
945af8d7
WD		 504 int counter = 0xffff;
505
506#if (DEBUG & 0x2)
507 if (fec->xcv_type != SEVENWIRE) {
508 uint16 phyStatus, i;
509 uint8 phyAddr = 0;
510
511 for (i = 0; i < 9; i++) {
512 miiphy_read(phyAddr, i, &phyStatus);
513 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
514 }
515 for (i = 16; i < 21; i++) {
516 miiphy_read(phyAddr, i, &phyStatus);
517 printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
518 }
519 }
520#endif
521
522
523 /*
524 * mask FEC chip interrupts
525 */
526 fec->eth->imask = 0;
527
528 /*
529 * issue graceful stop command to the FEC transmitter if necessary
530 */
531 fec->eth->x_cntrl |= 0x00000001;
532
533 /*
534 * wait for graceful stop to register
535 */
536 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
537
945af8d7
WD		 538 /*
539 * Disable SmartDMA tasks
540 */
541 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
542 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
543
544#if defined(CONFIG_MPC5200)
545 /*
546 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
547 * done. It doesn't work w/ the current receive task.
548 */
549 sdma->PtdCntrl &= ~0x00000001;
550#endif
551
552 /*
553 * Disable the Ethernet Controller
554 */
555 fec->eth->ecntrl &= 0xfffffffd;
556
557 /*
558 * Clear FIFO status registers
559 */
560 fec->eth->rfifo_status &= 0x00700000;
561 fec->eth->tfifo_status &= 0x00700000;
562
563 fec->eth->reset_cntrl = 0x01000000;
564
565 /*
566 * Issue a reset command to the FEC chip
567 */
568 fec->eth->ecntrl |= 0x1;
569
570 /*
571 * wait at least 16 clock cycles
572 */
573 udelay(10);
574
575#if (DEBUG & 0x3)
576 printf("Ethernet task stopped\n");
577#endif
578}
579
580#if (DEBUG & 0x60)
581/********************************************************************/
582
583static void tfifo_print(mpc5xxx_fec_priv *fec)
584{
585 uint16 phyAddr = 0;
586 uint16 phyStatus;
587
588 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
589 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
590
591 miiphy_read(phyAddr, 0x1, &phyStatus);
592 printf("\nphyStatus: 0x%04x\n", phyStatus);
593 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
594 printf("ievent: 0x%08x\n", fec->eth->ievent);
595 printf("x_status: 0x%08x\n", fec->eth->x_status);
596 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
597
598 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
599 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
600 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
601 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
602 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
603 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
604 }
605}
606
607static void rfifo_print(mpc5xxx_fec_priv *fec)
608{
609 uint16 phyAddr = 0;
610 uint16 phyStatus;
611
612 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
613 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
614
615 miiphy_read(phyAddr, 0x1, &phyStatus);
616 printf("\nphyStatus: 0x%04x\n", phyStatus);
617 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
618 printf("ievent: 0x%08x\n", fec->eth->ievent);
619 printf("x_status: 0x%08x\n", fec->eth->x_status);
620 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
621
622 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
623 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
624 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
625 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
626 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
627 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
628 }
629}
630#endif /* DEBUG */
631
632/********************************************************************/
633
634static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
635 int data_length)
636{
637 /*
638 * This routine transmits one frame. This routine only accepts
639 * 6-byte Ethernet addresses.
640 */
641 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
642 FEC_TBD *pTbd;
643
644#if (DEBUG & 0x20)
645 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
646 tfifo_print(fec);
647#endif
648
649 /*
650 * Clear Tx BD ring at first
651 */
652 mpc5xxx_fec_tbd_scrub(fec);
653
654 /*
655 * Check for valid length of data.
656 */
657 if ((data_length > 1500) || (data_length <= 0)) {
658 return -1;
659 }
660
661 /*
662 * Check the number of vacant TxBDs.
663 */
664 if (fec->cleanTbdNum < 1) {
665#if (DEBUG & 0x20)
666 printf("No available TxBDs ...\n");
667#endif
668 return -1;
669 }
670
671 /*
672 * Get the first TxBD to send the mac header
673 */
674 pTbd = &fec->tbdBase[fec->tbdIndex];
675 pTbd->dataLength = data_length;
676 pTbd->dataPointer = (uint32)eth_data;
77846748 677 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
945af8d7
WD		 678 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
679
680#if (DEBUG & 0x100)
681 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
682#endif
683
684 /*
685 * Kick the MII i/f
686 */
687 if (fec->xcv_type != SEVENWIRE) {
688 uint16 phyStatus;
689 miiphy_read(0, 0x1, &phyStatus);
690 }
691
692 /*
693 * Enable SmartDMA transmit task
694 */
695
696#if (DEBUG & 0x20)
697 tfifo_print(fec);
698#endif
699 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
700#if (DEBUG & 0x20)
701 tfifo_print(fec);
702#endif
703#if (DEBUG & 0x8)
704 printf( "+" );
705#endif
706
707 fec->cleanTbdNum -= 1;
708
709#if (DEBUG & 0x129) && (DEBUG & 0x80000000)
710 printf ("smartDMA ethernet Tx task enabled\n");
711#endif
712 /*
713 * wait until frame is sent .
714 */
715 while (pTbd->status & FEC_TBD_READY) {
716 udelay(10);
717#if (DEBUG & 0x8)
718 printf ("TDB status = %04x\n", pTbd->status);
719#endif
720 }
721
722 return 0;
723}
724
725
726/********************************************************************/
727static int mpc5xxx_fec_recv(struct eth_device *dev)
728{
729 /*
730 * This command pulls one frame from the card
731 */
732 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
733 FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
734 unsigned long ievent;
77846748
WD		 735 int frame_length, len = 0;
736 NBUF *frame;
737 char buff[FEC_MAX_PKT_SIZE];
945af8d7
WD		 738
739#if (DEBUG & 0x1)
740 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
741#endif
742#if (DEBUG & 0x8)
743 printf( "-" );
744#endif
745
746 /*
747 * Check if any critical events have happened
748 */
749 ievent = fec->eth->ievent;
750 fec->eth->ievent = ievent;
751 if (ievent & 0x20060000) {
752 /* BABT, Rx/Tx FIFO errors */
753 mpc5xxx_fec_halt(dev);
754 mpc5xxx_fec_init(dev, NULL);
755 return 0;
756 }
757 if (ievent & 0x80000000) {
758 /* Heartbeat error */
759 fec->eth->x_cntrl |= 0x00000001;
760 }
761 if (ievent & 0x10000000) {
762 /* Graceful stop complete */
763 if (fec->eth->x_cntrl & 0x00000001) {
764 mpc5xxx_fec_halt(dev);
765 fec->eth->x_cntrl &= ~0x00000001;
766 mpc5xxx_fec_init(dev, NULL);
767 }
768 }
769
77846748
WD		 770 if (!(pRbd->status & FEC_RBD_EMPTY)) {
771 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
772 ((pRbd->dataLength - 4) > 14)) {
945af8d7 773
77846748
WD		 774 /*
775 * Get buffer address and size
776 */
777 frame = (NBUF *)pRbd->dataPointer;
778 frame_length = pRbd->dataLength - 4;
779
780#if (DEBUG & 0x20)
781 {
782 int i;
783 printf("recv data hdr:");
784 for (i = 0; i < 14; i++)
785 printf("%x ", *(frame->head + i));
786 printf("\n");
787 }
945af8d7 788#endif
77846748
WD		 789 /*
790 * Fill the buffer and pass it to upper layers
791 */
792 memcpy(buff, frame->head, 14);
793 memcpy(buff + 14, frame->data, frame_length);
794 NetReceive(buff, frame_length);
795 len = frame_length;
796 }
797 /*
798 * Reset buffer descriptor as empty
799 */
800 mpc5xxx_fec_rbd_clean(fec, pRbd);
945af8d7 801 }
77846748
WD		 802 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
803 return len;
945af8d7
WD		 804}
805
806
807/********************************************************************/
808int mpc5xxx_fec_initialize(bd_t * bis)
809{
810 mpc5xxx_fec_priv *fec;
811 struct eth_device *dev;
812
813 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
814 dev = (struct eth_device *)malloc(sizeof(*dev));
815
816 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
817 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
818 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
819#ifdef CONFIG_ICECUBE
820 fec->xcv_type = MII100;
821#endif
822
823 dev->priv = (void *)fec;
824 dev->iobase = MPC5XXX_FEC;
825 dev->init = mpc5xxx_fec_init;
826 dev->halt = mpc5xxx_fec_halt;
827 dev->send = mpc5xxx_fec_send;
828 dev->recv = mpc5xxx_fec_recv;
829
77846748 830 sprintf(dev->name, "FEC ETHERNET");
945af8d7
WD		 831 eth_register(dev);
832
833 return 1;
834}
835
836/* MII-interface related functions */
837/********************************************************************/
838int miiphy_read(uint8 phyAddr, uint8 regAddr, uint16 * retVal)
839{
840 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
841 uint32 reg; /* convenient holder for the PHY register */
842 uint32 phy; /* convenient holder for the PHY */
843 int timeout = 0xffff;
844
845 /*
846 * reading from any PHY's register is done by properly
847 * programming the FEC's MII data register.
848 */
849 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
850 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
851
852 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
853
854 /*
855 * wait for the related interrupt
856 */
857 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
858
859 if (timeout == 0) {
860#if (DEBUG & 0x2)
861 printf ("Read MDIO failed...\n");
862#endif
863 return -1;
864 }
865
866 /*
867 * clear mii interrupt bit
868 */
869 eth->ievent = 0x00800000;
870
871 /*
872 * it's now safe to read the PHY's register
873 */
874 *retVal = (uint16) eth->mii_data;
875
876 return 0;
877}
878
879/********************************************************************/
880int miiphy_write(uint8 phyAddr, uint8 regAddr, uint16 data)
881{
882 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
883 uint32 reg; /* convenient holder for the PHY register */
884 uint32 phy; /* convenient holder for the PHY */
885 int timeout = 0xffff;
886
887 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
888 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
889
890 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
891 FEC_MII_DATA_TA | phy | reg | data);
892
893 /*
894 * wait for the MII interrupt
895 */
896 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
897
898 if (timeout == 0) {
899#if (DEBUG & 0x2)
900 printf ("Write MDIO failed...\n");
901#endif
902 return -1;
903 }
904
905 /*
906 * clear MII interrupt bit
907 */
908 eth->ievent = 0x00800000;
909
910 return 0;
911}
912
913#if (DEBUG & 0x40)
914static uint32 local_crc32(char *string, unsigned int crc_value, int len)
915{
916 int i;
917 char c;
918 unsigned int crc, count;
919
920 /*
921 * crc32 algorithm
922 */
923 /*
924 * crc = 0xffffffff; * The initialized value should be 0xffffffff
925 */
926 crc = crc_value;
927
928 for (i = len; --i >= 0;) {
929 c = *string++;
930 for (count = 0; count < 8; count++) {
931 if ((c & 0x01) ^ (crc & 0x01)) {
932 crc >>= 1;
933 crc = crc ^ 0xedb88320;
934 } else {
935 crc >>= 1;
936 }
937 c >>= 1;
938 }
939 }
940
941 /*
942 * In big endian system, do byte swaping for crc value
943 */
944 /**/ return crc;
945}
946#endif /* DEBUG */
947
948#endif /* CONFIG_MPC5XXX_FEC */
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