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80885a9d WD |
1 | /* |
2 | * URB OHCI HCD (Host Controller Driver) for USB. | |
3 | * | |
4 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
5 | * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net> | |
6 | * | |
7 | * usb-ohci.h | |
8 | */ | |
9 | ||
10 | ||
11 | static int cc_to_error[16] = { | |
12 | ||
13 | /* mapping of the OHCI CC status to error codes */ | |
14 | /* No Error */ 0, | |
15 | /* CRC Error */ USB_ST_CRC_ERR, | |
16 | /* Bit Stuff */ USB_ST_BIT_ERR, | |
17 | /* Data Togg */ USB_ST_CRC_ERR, | |
18 | /* Stall */ USB_ST_STALLED, | |
19 | /* DevNotResp */ -1, | |
20 | /* PIDCheck */ USB_ST_BIT_ERR, | |
21 | /* UnExpPID */ USB_ST_BIT_ERR, | |
22 | /* DataOver */ USB_ST_BUF_ERR, | |
23 | /* DataUnder */ USB_ST_BUF_ERR, | |
24 | /* reservd */ -1, | |
25 | /* reservd */ -1, | |
26 | /* BufferOver */ USB_ST_BUF_ERR, | |
27 | /* BuffUnder */ USB_ST_BUF_ERR, | |
28 | /* Not Access */ -1, | |
29 | /* Not Access */ -1 | |
30 | }; | |
31 | ||
32 | /* ED States */ | |
33 | ||
34 | #define ED_NEW 0x00 | |
35 | #define ED_UNLINK 0x01 | |
36 | #define ED_OPER 0x02 | |
37 | #define ED_DEL 0x04 | |
38 | #define ED_URB_DEL 0x08 | |
39 | ||
40 | /* usb_ohci_ed */ | |
41 | struct ed { | |
42 | __u32 hwINFO; | |
43 | __u32 hwTailP; | |
44 | __u32 hwHeadP; | |
45 | __u32 hwNextED; | |
46 | ||
47 | struct ed *ed_prev; | |
48 | __u8 int_period; | |
49 | __u8 int_branch; | |
50 | __u8 int_load; | |
51 | __u8 int_interval; | |
52 | __u8 state; | |
53 | __u8 type; | |
54 | __u16 last_iso; | |
55 | struct ed *ed_rm_list; | |
56 | ||
57 | struct usb_device *usb_dev; | |
58 | __u32 unused[3]; | |
59 | } __attribute((aligned(16))); | |
60 | typedef struct ed ed_t; | |
61 | ||
62 | ||
63 | /* TD info field */ | |
64 | #define TD_CC 0xf0000000 | |
65 | #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) | |
66 | #define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) | |
67 | #define TD_EC 0x0C000000 | |
68 | #define TD_T 0x03000000 | |
69 | #define TD_T_DATA0 0x02000000 | |
70 | #define TD_T_DATA1 0x03000000 | |
71 | #define TD_T_TOGGLE 0x00000000 | |
72 | #define TD_R 0x00040000 | |
73 | #define TD_DI 0x00E00000 | |
74 | #define TD_DI_SET(X) (((X) & 0x07)<< 21) | |
75 | #define TD_DP 0x00180000 | |
76 | #define TD_DP_SETUP 0x00000000 | |
77 | #define TD_DP_IN 0x00100000 | |
78 | #define TD_DP_OUT 0x00080000 | |
79 | ||
80 | #define TD_ISO 0x00010000 | |
81 | #define TD_DEL 0x00020000 | |
82 | ||
83 | /* CC Codes */ | |
84 | #define TD_CC_NOERROR 0x00 | |
85 | #define TD_CC_CRC 0x01 | |
86 | #define TD_CC_BITSTUFFING 0x02 | |
87 | #define TD_CC_DATATOGGLEM 0x03 | |
88 | #define TD_CC_STALL 0x04 | |
89 | #define TD_DEVNOTRESP 0x05 | |
90 | #define TD_PIDCHECKFAIL 0x06 | |
91 | #define TD_UNEXPECTEDPID 0x07 | |
92 | #define TD_DATAOVERRUN 0x08 | |
93 | #define TD_DATAUNDERRUN 0x09 | |
94 | #define TD_BUFFEROVERRUN 0x0C | |
95 | #define TD_BUFFERUNDERRUN 0x0D | |
96 | #define TD_NOTACCESSED 0x0F | |
97 | ||
98 | ||
99 | #define MAXPSW 1 | |
100 | ||
101 | struct td { | |
102 | __u32 hwINFO; | |
103 | __u32 hwCBP; /* Current Buffer Pointer */ | |
104 | __u32 hwNextTD; /* Next TD Pointer */ | |
105 | __u32 hwBE; /* Memory Buffer End Pointer */ | |
106 | ||
80885a9d WD |
107 | __u8 unused; |
108 | __u8 index; | |
109 | struct ed *ed; | |
110 | struct td *next_dl_td; | |
111 | struct usb_device *usb_dev; | |
112 | int transfer_len; | |
113 | __u32 data; | |
114 | ||
115 | __u32 unused2[2]; | |
116 | } __attribute((aligned(32))); | |
117 | typedef struct td td_t; | |
118 | ||
119 | #define OHCI_ED_SKIP (1 << 14) | |
120 | ||
121 | /* | |
122 | * The HCCA (Host Controller Communications Area) is a 256 byte | |
123 | * structure defined in the OHCI spec. that the host controller is | |
124 | * told the base address of. It must be 256-byte aligned. | |
125 | */ | |
126 | ||
127 | #define NUM_INTS 32 /* part of the OHCI standard */ | |
128 | struct ohci_hcca { | |
129 | __u32 int_table[NUM_INTS]; /* Interrupt ED table */ | |
130 | #if defined(CONFIG_MPC5200) | |
131 | __u16 pad1; /* set to 0 on each frame_no change */ | |
132 | __u16 frame_no; /* current frame number */ | |
133 | #else | |
134 | __u16 frame_no; /* current frame number */ | |
135 | __u16 pad1; /* set to 0 on each frame_no change */ | |
136 | #endif | |
137 | __u32 done_head; /* info returned for an interrupt */ | |
138 | u8 reserved_for_hc[116]; | |
139 | } __attribute((aligned(256))); | |
140 | ||
141 | ||
142 | /* | |
143 | * Maximum number of root hub ports. | |
144 | */ | |
145 | #define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ | |
146 | ||
147 | /* | |
148 | * This is the structure of the OHCI controller's memory mapped I/O | |
149 | * region. This is Memory Mapped I/O. You must use the readl() and | |
150 | * writel() macros defined in asm/io.h to access these!! | |
151 | */ | |
152 | struct ohci_regs { | |
153 | /* control and status registers */ | |
154 | __u32 revision; | |
155 | __u32 control; | |
156 | __u32 cmdstatus; | |
157 | __u32 intrstatus; | |
158 | __u32 intrenable; | |
159 | __u32 intrdisable; | |
160 | /* memory pointers */ | |
161 | __u32 hcca; | |
162 | __u32 ed_periodcurrent; | |
163 | __u32 ed_controlhead; | |
164 | __u32 ed_controlcurrent; | |
165 | __u32 ed_bulkhead; | |
166 | __u32 ed_bulkcurrent; | |
167 | __u32 donehead; | |
168 | /* frame counters */ | |
169 | __u32 fminterval; | |
170 | __u32 fmremaining; | |
171 | __u32 fmnumber; | |
172 | __u32 periodicstart; | |
173 | __u32 lsthresh; | |
174 | /* Root hub ports */ | |
175 | struct ohci_roothub_regs { | |
176 | __u32 a; | |
177 | __u32 b; | |
178 | __u32 status; | |
179 | __u32 portstatus[MAX_ROOT_PORTS]; | |
180 | } roothub; | |
181 | } __attribute((aligned(32))); | |
182 | ||
183 | ||
184 | /* OHCI CONTROL AND STATUS REGISTER MASKS */ | |
185 | ||
186 | /* | |
187 | * HcControl (control) register masks | |
188 | */ | |
189 | #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ | |
190 | #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ | |
191 | #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ | |
192 | #define OHCI_CTRL_CLE (1 << 4) /* control list enable */ | |
193 | #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ | |
194 | #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ | |
195 | #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ | |
196 | #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ | |
197 | #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ | |
198 | ||
199 | /* pre-shifted values for HCFS */ | |
200 | # define OHCI_USB_RESET (0 << 6) | |
201 | # define OHCI_USB_RESUME (1 << 6) | |
202 | # define OHCI_USB_OPER (2 << 6) | |
203 | # define OHCI_USB_SUSPEND (3 << 6) | |
204 | ||
205 | /* | |
206 | * HcCommandStatus (cmdstatus) register masks | |
207 | */ | |
208 | #define OHCI_HCR (1 << 0) /* host controller reset */ | |
209 | #define OHCI_CLF (1 << 1) /* control list filled */ | |
210 | #define OHCI_BLF (1 << 2) /* bulk list filled */ | |
211 | #define OHCI_OCR (1 << 3) /* ownership change request */ | |
212 | #define OHCI_SOC (3 << 16) /* scheduling overrun count */ | |
213 | ||
214 | /* | |
215 | * masks used with interrupt registers: | |
216 | * HcInterruptStatus (intrstatus) | |
217 | * HcInterruptEnable (intrenable) | |
218 | * HcInterruptDisable (intrdisable) | |
219 | */ | |
220 | #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ | |
221 | #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ | |
222 | #define OHCI_INTR_SF (1 << 2) /* start frame */ | |
223 | #define OHCI_INTR_RD (1 << 3) /* resume detect */ | |
224 | #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ | |
225 | #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ | |
226 | #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ | |
227 | #define OHCI_INTR_OC (1 << 30) /* ownership change */ | |
228 | #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ | |
229 | ||
230 | ||
231 | /* Virtual Root HUB */ | |
232 | struct virt_root_hub { | |
233 | int devnum; /* Address of Root Hub endpoint */ | |
234 | void *dev; /* was urb */ | |
235 | void *int_addr; | |
236 | int send; | |
237 | int interval; | |
238 | }; | |
239 | ||
240 | /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ | |
241 | ||
242 | /* destination of request */ | |
243 | #define RH_INTERFACE 0x01 | |
244 | #define RH_ENDPOINT 0x02 | |
245 | #define RH_OTHER 0x03 | |
246 | ||
247 | #define RH_CLASS 0x20 | |
248 | #define RH_VENDOR 0x40 | |
249 | ||
250 | /* Requests: bRequest << 8 | bmRequestType */ | |
251 | #define RH_GET_STATUS 0x0080 | |
252 | #define RH_CLEAR_FEATURE 0x0100 | |
253 | #define RH_SET_FEATURE 0x0300 | |
254 | #define RH_SET_ADDRESS 0x0500 | |
255 | #define RH_GET_DESCRIPTOR 0x0680 | |
256 | #define RH_SET_DESCRIPTOR 0x0700 | |
257 | #define RH_GET_CONFIGURATION 0x0880 | |
258 | #define RH_SET_CONFIGURATION 0x0900 | |
259 | #define RH_GET_STATE 0x0280 | |
260 | #define RH_GET_INTERFACE 0x0A80 | |
261 | #define RH_SET_INTERFACE 0x0B00 | |
262 | #define RH_SYNC_FRAME 0x0C80 | |
263 | /* Our Vendor Specific Request */ | |
264 | #define RH_SET_EP 0x2000 | |
265 | ||
266 | ||
267 | /* Hub port features */ | |
268 | #define RH_PORT_CONNECTION 0x00 | |
269 | #define RH_PORT_ENABLE 0x01 | |
270 | #define RH_PORT_SUSPEND 0x02 | |
271 | #define RH_PORT_OVER_CURRENT 0x03 | |
272 | #define RH_PORT_RESET 0x04 | |
273 | #define RH_PORT_POWER 0x08 | |
274 | #define RH_PORT_LOW_SPEED 0x09 | |
275 | ||
276 | #define RH_C_PORT_CONNECTION 0x10 | |
277 | #define RH_C_PORT_ENABLE 0x11 | |
278 | #define RH_C_PORT_SUSPEND 0x12 | |
279 | #define RH_C_PORT_OVER_CURRENT 0x13 | |
280 | #define RH_C_PORT_RESET 0x14 | |
281 | ||
282 | /* Hub features */ | |
283 | #define RH_C_HUB_LOCAL_POWER 0x00 | |
284 | #define RH_C_HUB_OVER_CURRENT 0x01 | |
285 | ||
286 | #define RH_DEVICE_REMOTE_WAKEUP 0x00 | |
287 | #define RH_ENDPOINT_STALL 0x01 | |
288 | ||
289 | #define RH_ACK 0x01 | |
290 | #define RH_REQ_ERR -1 | |
291 | #define RH_NACK 0x00 | |
292 | ||
293 | ||
294 | /* OHCI ROOT HUB REGISTER MASKS */ | |
295 | ||
296 | /* roothub.portstatus [i] bits */ | |
297 | #define RH_PS_CCS 0x00000001 /* current connect status */ | |
298 | #define RH_PS_PES 0x00000002 /* port enable status*/ | |
299 | #define RH_PS_PSS 0x00000004 /* port suspend status */ | |
300 | #define RH_PS_POCI 0x00000008 /* port over current indicator */ | |
301 | #define RH_PS_PRS 0x00000010 /* port reset status */ | |
302 | #define RH_PS_PPS 0x00000100 /* port power status */ | |
303 | #define RH_PS_LSDA 0x00000200 /* low speed device attached */ | |
304 | #define RH_PS_CSC 0x00010000 /* connect status change */ | |
305 | #define RH_PS_PESC 0x00020000 /* port enable status change */ | |
306 | #define RH_PS_PSSC 0x00040000 /* port suspend status change */ | |
307 | #define RH_PS_OCIC 0x00080000 /* over current indicator change */ | |
308 | #define RH_PS_PRSC 0x00100000 /* port reset status change */ | |
309 | ||
310 | /* roothub.status bits */ | |
311 | #define RH_HS_LPS 0x00000001 /* local power status */ | |
312 | #define RH_HS_OCI 0x00000002 /* over current indicator */ | |
313 | #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ | |
314 | #define RH_HS_LPSC 0x00010000 /* local power status change */ | |
315 | #define RH_HS_OCIC 0x00020000 /* over current indicator change */ | |
316 | #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ | |
317 | ||
318 | /* roothub.b masks */ | |
319 | #define RH_B_DR 0x0000ffff /* device removable flags */ | |
320 | #define RH_B_PPCM 0xffff0000 /* port power control mask */ | |
321 | ||
322 | /* roothub.a masks */ | |
323 | #define RH_A_NDP (0xff << 0) /* number of downstream ports */ | |
324 | #define RH_A_PSM (1 << 8) /* power switching mode */ | |
325 | #define RH_A_NPS (1 << 9) /* no power switching */ | |
326 | #define RH_A_DT (1 << 10) /* device type (mbz) */ | |
327 | #define RH_A_OCPM (1 << 11) /* over current protection mode */ | |
328 | #define RH_A_NOCP (1 << 12) /* no over current protection */ | |
329 | #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ | |
330 | ||
331 | /* urb */ | |
332 | #define N_URB_TD 48 | |
333 | typedef struct | |
334 | { | |
335 | ed_t *ed; | |
336 | __u16 length; /* number of tds associated with this request */ | |
337 | __u16 td_cnt; /* number of tds already serviced */ | |
338 | int state; | |
339 | unsigned long pipe; | |
340 | int actual_length; | |
341 | td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ | |
342 | } urb_priv_t; | |
343 | #define URB_DEL 1 | |
344 | ||
345 | /* | |
346 | * This is the full ohci controller description | |
347 | * | |
348 | * Note how the "proper" USB information is just | |
349 | * a subset of what the full implementation needs. (Linus) | |
350 | */ | |
351 | ||
352 | ||
353 | typedef struct ohci { | |
354 | struct ohci_hcca *hcca; /* hcca */ | |
355 | /*dma_addr_t hcca_dma;*/ | |
356 | ||
357 | int irq; | |
358 | int disabled; /* e.g. got a UE, we're hung */ | |
359 | int sleeping; | |
360 | unsigned long flags; /* for HC bugs */ | |
361 | ||
362 | struct ohci_regs *regs; /* OHCI controller's memory */ | |
363 | ||
364 | ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ | |
365 | ed_t *ed_bulktail; /* last endpoint of bulk list */ | |
366 | ed_t *ed_controltail; /* last endpoint of control list */ | |
367 | int intrstatus; | |
368 | __u32 hc_control; /* copy of the hc control reg */ | |
369 | struct usb_device *dev[32]; | |
370 | struct virt_root_hub rh; | |
371 | ||
372 | const char *slot_name; | |
373 | } ohci_t; | |
374 | ||
375 | #define NUM_EDS 8 /* num of preallocated endpoint descriptors */ | |
376 | ||
377 | struct ohci_device { | |
378 | ed_t ed[NUM_EDS]; | |
379 | int ed_cnt; | |
380 | }; | |
381 | ||
382 | /* hcd */ | |
383 | /* endpoint */ | |
384 | static int ep_link(ohci_t * ohci, ed_t * ed); | |
385 | static int ep_unlink(ohci_t * ohci, ed_t * ed); | |
386 | static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); | |
387 | ||
388 | /*-------------------------------------------------------------------------*/ | |
389 | ||
390 | /* we need more TDs than EDs */ | |
391 | #define NUM_TD 64 | |
392 | ||
393 | /* +1 so we can align the storage */ | |
394 | td_t gtd[NUM_TD+1]; | |
395 | /* pointers to aligned storage */ | |
396 | td_t *ptd; | |
397 | ||
398 | /* TDs ... */ | |
399 | static inline struct td * | |
400 | td_alloc (struct usb_device *usb_dev) | |
401 | { | |
402 | int i; | |
403 | struct td *td; | |
404 | ||
405 | td = NULL; | |
406 | for (i = 0; i < NUM_TD; i++) | |
407 | { | |
408 | if (ptd[i].usb_dev == NULL) | |
409 | { | |
410 | td = &ptd[i]; | |
411 | td->usb_dev = usb_dev; | |
412 | break; | |
413 | } | |
414 | } | |
415 | ||
416 | return td; | |
417 | } | |
418 | ||
419 | static inline void | |
420 | ed_free (struct ed *ed) | |
421 | { | |
422 | ed->usb_dev = NULL; | |
423 | } |