[u-boot.git] / cpu / mpc824x / drivers / i2o / i2o.h

#ifndef I2O_H
#define I2O_H
/*********************************************************
 *
 * copyright @ Motorola, 1999
 *
 *********************************************************/

#define I2O_REG_OFFSET 0x0004

#define PCI_CFG_CLA    0x0B
#define PCI_CFG_SCL    0x0A
#define PCI_CFG_PIC    0x09

#define I2O_IMR0 0x0050
#define I2O_IMR1 0x0054
#define I2O_OMR0 0x0058
#define I2O_OMR1 0x005C

#define I2O_ODBR 0x0060
#define I2O_IDBR 0x0068

#define I2O_OMISR  0x0030
#define I2O_OMIMR  0x0034
#define I2O_IMISR  0x0100
#define I2O_IMIMR  0x0104

/* accessable to PCI master but local processor */
#define I2O_IFQPR  0x0040
#define I2O_OFQPR  0x0044

/* accessable to local processor */
#define I2O_IFHPR  0x0120
#define I2O_IFTPR  0x0128
#define I2O_IPHPR  0x0130
#define I2O_IPTPR  0x0138
#define I2O_OFHPR  0x0140
#define I2O_OFTPR  0x0148
#define I2O_OPHPR  0x0150
#define I2O_OPTPR  0x0158
#define I2O_MUCR   0x0164
#define I2O_QBAR   0x0170

#define I2O_NUM_MSG 2

typedef enum _i2o_status
{
	I2OSUCCESS = 0,
	I2OINVALID,
	I2OMSGINVALID,
	I2ODBINVALID,
	I2OQUEINVALID,
	I2OQUEEMPTY,
	I2OQUEFULL,
	I2ONOEVENT,
} I2OSTATUS;

typedef enum _queue_size
{
    QSIZE_4K = 0x02,
    QSIZE_8K = 0x04,
    QSIZE_16K = 0x08,
    QSIZE_32K = 0x10,
    QSIZe_64K = 0x20,
} QUEUE_SIZE;

typedef enum _location
{
    LOCAL = 0,     /* used by local processor to access its own on board device,
		      local processor's eumbbar is required */
    REMOTE,        /* used by PCI master to access the devices on its PCI device,
		      device's pcsrbar is required */
} LOCATION;

/* door bell */
typedef enum _i2o_in_db
{
  IN_DB = 1,
  MC,         /* machine check */
} I2O_IN_DB;

/* I2O PCI configuration identification */
typedef struct _i2o_iop
{
	unsigned int base_class : 8;
	unsigned int sub_class  : 8;
	unsigned int prg_code   : 8;
} I2OIOP;

/* I2O Outbound Message Interrupt Status Register */
typedef struct _i2o_om_stat
{
	unsigned int rsvd0 : 26;
	unsigned int opqi  : 1;
	unsigned int rsvd1 : 1;
	unsigned int odi   : 1;
	unsigned int rsvd2 : 1;
	unsigned int om1i  : 1;
	unsigned int om0i  : 1;
} I2OOMSTAT;

/* I2O inbound Message Interrupt Status Register */
typedef struct _i2o_im_stat
{
	unsigned int rsvd0 : 23;
	unsigned int ofoi  : 1;
	unsigned int ipoi  : 1;
	unsigned int rsvd1 : 1;
	unsigned int ipqi  : 1;
	unsigned int mci   : 1;
	unsigned int idi   : 1;
	unsigned int rsvd2 : 1;
	unsigned int im1i  : 1;
	unsigned int im0i  : 1;
} I2OIMSTAT;

/**
 Enable the interrupt associated with in/out bound msg

 Inbound message interrupt generated by PCI master and serviced by local processor
 local processor needs to enable its inbound interrupts it wants to handle (LOCAL)

 Outbound message interrupt generated by local processor and serviced by PCI master
 PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE)
 **/
extern I2OSTATUS I2OMsgEnable( LOCATION,            /*  REMOTE/LOCAL   */
			       unsigned int base,   /* pcsrbar/eumbbar */
			       unsigned char n );   /* b'1' - msg 0
									     * b'10'- msg 1
									     * b'11'- both
									     */

/**
 Disable the interrupt associated with in/out bound msg

 local processor needs to disable its inbound interrupts it is not interested (LOCAL)

 PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE)
 **/
extern I2OSTATUS I2OMsgDisable( LOCATION,          /*  REMOTE/LOCAL   */
				unsigned int base, /* pcsrbar/eumbbar */
				unsigned char n ); /* b'1' - msg 0
									    * b'10'- msg 1
									    * b'11'- both
									    */

/**
 Read the msg register either from local inbound msg 0/1,
 or an outbound msg 0/1 of devices.

 If it is not local, pcsrbar must be passed to the function.
 Otherwise eumbbar is passed.

 If it is remote, outbound msg of the device is read.
 Otherwise local inbound msg is read.
 **/
extern I2OSTATUS I2OMsgGet ( LOCATION,                 /* REMOTE/LOCAL */
			     unsigned int base,        /*pcsrbar/eumbbar */
			     unsigned int n,           /* 0 or 1 */
			     unsigned int *msg );

/**
 Write to nth Msg register either on local outbound msg 0/1,
 or aninbound msg 0/1 of devices

 If it is not local, pcsrbar must be passed to the function.
 Otherwise eumbbar is passed.

 If it is remote, inbound msg on the device is written.
 Otherwise local outbound msg is written.
 **/
extern I2OSTATUS I2OMsgPost( LOCATION,                 /* REMOTE/LOCAL */
				unsigned int base,        /*pcsrbar/eumbbar */
				unsigned int n,           /* 0 or 1 */
				unsigned int msg );

/**
 Enable the In/Out DoorBell Interrupt

 InDoorBell interrupt is generated by PCI master and serviced by local processor
 local processor needs to enable its inbound doorbell interrupts it wants to handle

 OutDoorbell interrupt is generated by local processor and serviced by PCI master
 PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle
 **/
extern I2OSTATUS I2ODBEnable( LOCATION,            /*  REMOTE/LOCAL   */
			      unsigned int base,   /* pcsrbar/eumbbar */
			      unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */

/**
 Disable the In/Out DoorBell Interrupt

 local processor needs to disable its inbound doorbell interrupts it is not interested

 PCI master needs to disable outbound doorbell interrupts of devices it is not interested

 **/
extern I2OSTATUS I2ODBDisable( LOCATION,              /*  REMOTE/LOCAL   */
			       unsigned int base,     /* pcsrbar/eumbbar */
			       unsigned int in_db );  /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */

/**
 Read a local indoorbell register, or an outdoorbell of devices.
 Reading a doorbell register, the register will be cleared.

 If it is not local, pcsrbar must be passed to the function.
 Otherwise eumbbar is passed.

 If it is remote, outdoorbell register on the device is read.
 Otherwise local in doorbell is read
 **/
extern unsigned int I2ODBGet( LOCATION,             /*  REMOTE/LOCAL   */
			      unsigned int base);   /* pcsrbar/eumbbar */

/**
 Write to a local outdoorbell register, or an indoorbell register of devices.

 If it is not local, pcsrbar must be passed to the function.
 Otherwise eumbbar is passed.

 If it is remote, in doorbell register on the device is written.
 Otherwise local out doorbell is written
 **/
extern void I2ODBPost( LOCATION,                 /*  REMOTE/LOCAL   */
		       unsigned int base,        /* pcsrbar/eumbbar */
		       unsigned int msg );       /*   in   / out    */

/**
 Read the outbound msg unit interrupt status of devices. Reading an interrupt status register,
 the register will be cleared.

 The outbound interrupt status is AND with the outbound
 interrupt mask. The result is returned.

 PCI master must pass the pcsrbar to the function.
 **/
extern I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT * );

/**
 Read the inbound msg unit interrupt status. Reading an interrupt status register,
 the register will be cleared.

 The inbound interrupt status is AND with the inbound
 interrupt mask. The result is returned.

 Local process must pass its eumbbar to the function.
**/
extern I2OSTATUS I2OInMsgStatGet( unsigned int eumbbar, I2OIMSTAT * );

/**
 Configure the I2O FIFO, including QBAR, IFHPR/IFTPR,IPHPR/IPTPR,OFHPR/OFTPR, OPHPR/OPTPR,
 MUCR.
 **/
extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar,
					      QUEUE_SIZE,
					      unsigned int qba);/* queue base address that must be aligned at 1M */
/**
 Enable the circular queue
 **/
extern I2OSTATUS I2OFIFOEnable( unsigned int eumbbar );

/**
 Disable the circular queue
 **/
extern void I2OFIFODisable( unsigned int eumbbar );

/**
 Enable the circular queue interrupt
 PCI master enables outbound FIFO interrupt of device
 Device enables its inbound FIFO interrupt
 **/
extern void I2OFIFOIntEnable( LOCATION, unsigned int base  );

/**
 Disable the circular queue interrupt
 PCI master disables outbound FIFO interrupt of device
 Device disables its inbound FIFO interrupt
 **/
extern void I2OFIFOIntDisable( LOCATION, unsigned int base );

/**
 Enable the circular queue overflow interrupt
 **/
extern void I2OFIFOOverflowIntEnable( unsigned int eumbbar );

/**
 Disable the circular queue overflow interrupt
 **/
extern void I2OFIFOOverflowIntDisable( unsigned int eumbbar );

/**
 Allocate a free msg frame from free FIFO.

 PCI Master allocates a free msg frame through inbound queue port of device(IFQPR)
 while local processor allocates a free msg frame from outbound free queue(OFTPR)

 Unless both free queues are initialized, allocating a free MF will return 0xffffffff
 **/
extern I2OSTATUS I2OFIFOAlloc( LOCATION,
					       unsigned int base,
					       void         **pMsg);
/**
 Free a used msg frame back to free queue
 PCI Master frees a MFA through outbound queue port of device(OFQPR)
 while local processor frees a MFA into its inbound free queue(IFHPR)

 Used msg frame does not need to be recycled in the order they
 read

 This function has to be called by PCI master to initialize Inbound free queue
 and by device to initialize Outbound free queue before I2OFIFOAlloc can be used.
 **/
extern I2OSTATUS I2OFIFOFree( LOCATION,
					  unsigned int base,
					  void        *pMsg );

/**
 Post a msg into FIFO
 PCI Master posts a msg through inbound queue port of device(IFQPR)
 while local processor post a msg into its outbound post queue(OPHPR)

 The total number of msg must be less than the max size of the queue
 Otherwise queue overflow interrupt will assert.
 **/
extern I2OSTATUS I2OFIFOPost( LOCATION,
				      unsigned int base,
				      void         *pMsg );

/**
 Read a msg from FIFO
 PCI Master reads a msg through outbound queue port of device(OFQPR)
 while local processor reads a msg from its inbound post queue(IPTPR)
 **/
extern I2OSTATUS I2OFIFOGet( LOCATION,
					  unsigned int base,
							  void     **pMsg );

/**
 Get the I2O PCI configuration identification register
 **/
extern I2OSTATUS I2OPCIConfigGet( LOCATION,
					   unsigned int base,
							   I2OIOP *);

#endif
Commit	Line	Data
327f7a02 WD	1	#ifndef I2O_H
	2	#define I2O_H
	3	/*********************************************************
	4	*
	5	* copyright @ Motorola, 1999
	6	*
	7	*********************************************************/
	8
	9	#define I2O_REG_OFFSET 0x0004
	10
	11	#define PCI_CFG_CLA 0x0B
	12	#define PCI_CFG_SCL 0x0A
	13	#define PCI_CFG_PIC 0x09
	14
	15	#define I2O_IMR0 0x0050
	16	#define I2O_IMR1 0x0054
	17	#define I2O_OMR0 0x0058
	18	#define I2O_OMR1 0x005C
	19
	20	#define I2O_ODBR 0x0060
	21	#define I2O_IDBR 0x0068
	22
	23	#define I2O_OMISR 0x0030
	24	#define I2O_OMIMR 0x0034
	25	#define I2O_IMISR 0x0100
	26	#define I2O_IMIMR 0x0104
	27
	28	/* accessable to PCI master but local processor */
	29	#define I2O_IFQPR 0x0040
	30	#define I2O_OFQPR 0x0044
	31
	32	/* accessable to local processor */
	33	#define I2O_IFHPR 0x0120
	34	#define I2O_IFTPR 0x0128
	35	#define I2O_IPHPR 0x0130
	36	#define I2O_IPTPR 0x0138
	37	#define I2O_OFHPR 0x0140
	38	#define I2O_OFTPR 0x0148
	39	#define I2O_OPHPR 0x0150
	40	#define I2O_OPTPR 0x0158
	41	#define I2O_MUCR 0x0164
	42	#define I2O_QBAR 0x0170
	43
	44	#define I2O_NUM_MSG 2
	45
	46	typedef enum _i2o_status
	47	{
	48	I2OSUCCESS = 0,
	49	I2OINVALID,
	50	I2OMSGINVALID,
	51	I2ODBINVALID,
	52	I2OQUEINVALID,
	53	I2OQUEEMPTY,
	54	I2OQUEFULL,
	55	I2ONOEVENT,
	56	} I2OSTATUS;
	57
	58	typedef enum _queue_size
	59	{
	60	QSIZE_4K = 0x02,
	61	QSIZE_8K = 0x04,
	62	QSIZE_16K = 0x08,
	63	QSIZE_32K = 0x10,
	64	QSIZe_64K = 0x20,
65	} QUEUE_SIZE;
66
67	typedef enum _location
68	{
69	LOCAL = 0, /* used by local processor to access its own on board device,
70	local processor's eumbbar is required */
71	REMOTE, /* used by PCI master to access the devices on its PCI device,
72	device's pcsrbar is required */
73	} LOCATION;
74
75	/* door bell */
76	typedef enum _i2o_in_db
77	{
78	IN_DB = 1,
79	MC, /* machine check */
80	} I2O_IN_DB;
81
82	/* I2O PCI configuration identification */
83	typedef struct _i2o_iop
84	{
85	unsigned int base_class : 8;
86	unsigned int sub_class : 8;
87	unsigned int prg_code : 8;
88	} I2OIOP;
89
90	/* I2O Outbound Message Interrupt Status Register */
91	typedef struct _i2o_om_stat
92	{
93	unsigned int rsvd0 : 26;
94	unsigned int opqi : 1;
95	unsigned int rsvd1 : 1;
96	unsigned int odi : 1;
97	unsigned int rsvd2 : 1;
98	unsigned int om1i : 1;
99	unsigned int om0i : 1;
100	} I2OOMSTAT;
101
102	/* I2O inbound Message Interrupt Status Register */
103	typedef struct _i2o_im_stat
104	{
105	unsigned int rsvd0 : 23;
106	unsigned int ofoi : 1;
107	unsigned int ipoi : 1;
108	unsigned int rsvd1 : 1;
109	unsigned int ipqi : 1;
110	unsigned int mci : 1;
111	unsigned int idi : 1;
112	unsigned int rsvd2 : 1;
113	unsigned int im1i : 1;
114	unsigned int im0i : 1;
115	} I2OIMSTAT;
116
117	/**
118	Enable the interrupt associated with in/out bound msg
119
120	Inbound message interrupt generated by PCI master and serviced by local processor
121	local processor needs to enable its inbound interrupts it wants to handle (LOCAL)
122
123	Outbound message interrupt generated by local processor and serviced by PCI master
124	PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE)
125	**/
126	extern I2OSTATUS I2OMsgEnable( LOCATION, /* REMOTE/LOCAL */
8bde7f77 WD	127	unsigned int base, /* pcsrbar/eumbbar */
	128	unsigned char n ); /* b'1' - msg 0
	129	* b'10'- msg 1
	130	* b'11'- both
	131	*/
327f7a02 WD	132
	133	/**
	134	Disable the interrupt associated with in/out bound msg
	135
	136	local processor needs to disable its inbound interrupts it is not interested (LOCAL)
	137
	138	PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE)
	139	**/
	140	extern I2OSTATUS I2OMsgDisable( LOCATION, /* REMOTE/LOCAL */
8bde7f77 WD	141	unsigned int base, /* pcsrbar/eumbbar */
	142	unsigned char n ); /* b'1' - msg 0
	143	* b'10'- msg 1
	144	* b'11'- both
	145	*/
327f7a02 WD	146
	147	/**
	148	Read the msg register either from local inbound msg 0/1,
	149	or an outbound msg 0/1 of devices.
	150
	151	If it is not local, pcsrbar must be passed to the function.
	152	Otherwise eumbbar is passed.
	153
	154	If it is remote, outbound msg of the device is read.
	155	Otherwise local inbound msg is read.
	156	**/
	157	extern I2OSTATUS I2OMsgGet ( LOCATION, /* REMOTE/LOCAL */
8bde7f77 WD	158	unsigned int base, /pcsrbar/eumbbar /
	159	unsigned int n, /* 0 or 1 */
	160	unsigned int *msg );
327f7a02 WD	161
	162	/**
	163	Write to nth Msg register either on local outbound msg 0/1,
	164	or aninbound msg 0/1 of devices
	165
	166	If it is not local, pcsrbar must be passed to the function.
	167	Otherwise eumbbar is passed.
	168
	169	If it is remote, inbound msg on the device is written.
	170	Otherwise local outbound msg is written.
	171	**/
	172	extern I2OSTATUS I2OMsgPost( LOCATION, /* REMOTE/LOCAL */
8bde7f77 WD	173	unsigned int base, /pcsrbar/eumbbar /
	174	unsigned int n, /* 0 or 1 */
	175	unsigned int msg );
327f7a02 WD	176
	177	/**
	178	Enable the In/Out DoorBell Interrupt
	179
	180	InDoorBell interrupt is generated by PCI master and serviced by local processor
	181	local processor needs to enable its inbound doorbell interrupts it wants to handle
	182
	183	OutDoorbell interrupt is generated by local processor and serviced by PCI master
	184	PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle
	185	**/
	186	extern I2OSTATUS I2ODBEnable( LOCATION, /* REMOTE/LOCAL */
8bde7f77 WD	187	unsigned int base, /* pcsrbar/eumbbar */
8bde7f77 WD	188	unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB\|MC */
327f7a02 WD	189
	190	/**
	191	Disable the In/Out DoorBell Interrupt
	192
	193	local processor needs to disable its inbound doorbell interrupts it is not interested
	194
	195	PCI master needs to disable outbound doorbell interrupts of devices it is not interested
	196
	197	**/
	198	extern I2OSTATUS I2ODBDisable( LOCATION, /* REMOTE/LOCAL */
8bde7f77 WD	199	unsigned int base, /* pcsrbar/eumbbar */
8bde7f77 WD	200	unsigned int in_db ); /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB\|MC */
327f7a02 WD	201
	202	/**
	203	Read a local indoorbell register, or an outdoorbell of devices.
	204	Reading a doorbell register, the register will be cleared.
	205
	206	If it is not local, pcsrbar must be passed to the function.
	207	Otherwise eumbbar is passed.
	208
	209	If it is remote, outdoorbell register on the device is read.
	210	Otherwise local in doorbell is read
	211	**/
	212	extern unsigned int I2ODBGet( LOCATION, /* REMOTE/LOCAL */
8bde7f77	213	unsigned int base); /* pcsrbar/eumbbar */
327f7a02 WD	214
	215	/**
	216	Write to a local outdoorbell register, or an indoorbell register of devices.
	217
	218	If it is not local, pcsrbar must be passed to the function.
	219	Otherwise eumbbar is passed.
	220
	221	If it is remote, in doorbell register on the device is written.
	222	Otherwise local out doorbell is written
	223	**/
	224	extern void I2ODBPost( LOCATION, /* REMOTE/LOCAL */
8bde7f77 WD	225	unsigned int base, /* pcsrbar/eumbbar */
8bde7f77 WD	226	unsigned int msg ); /* in / out */
327f7a02 WD	227
	228	/**
	229	Read the outbound msg unit interrupt status of devices. Reading an interrupt status register,
	230	the register will be cleared.
	231
	232	The outbound interrupt status is AND with the outbound
	233	interrupt mask. The result is returned.
	234
	235	PCI master must pass the pcsrbar to the function.
	236	**/
	237	extern I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT * );
	238
	239	/**
	240	Read the inbound msg unit interrupt status. Reading an interrupt status register,
	241	the register will be cleared.
	242
	243	The inbound interrupt status is AND with the inbound
	244	interrupt mask. The result is returned.
	245
	246	Local process must pass its eumbbar to the function.
	247	**/
	248	extern I2OSTATUS I2OInMsgStatGet( unsigned int eumbbar, I2OIMSTAT * );
	249
	250	/**
	251	Configure the I2O FIFO, including QBAR, IFHPR/IFTPR,IPHPR/IPTPR,OFHPR/OFTPR, OPHPR/OPTPR,
	252	MUCR.
	253	**/
	254	extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar,
8bde7f77 WD	255	QUEUE_SIZE,
8bde7f77 WD	256	unsigned int qba);/* queue base address that must be aligned at 1M */
327f7a02 WD	257	/**
	258	Enable the circular queue
	259	**/
	260	extern I2OSTATUS I2OFIFOEnable( unsigned int eumbbar );
	261
	262	/**
	263	Disable the circular queue
	264	**/
	265	extern void I2OFIFODisable( unsigned int eumbbar );
	266
	267	/**
	268	Enable the circular queue interrupt
	269	PCI master enables outbound FIFO interrupt of device
	270	Device enables its inbound FIFO interrupt
	271	**/
	272	extern void I2OFIFOIntEnable( LOCATION, unsigned int base );
	273
	274	/**
	275	Disable the circular queue interrupt
	276	PCI master disables outbound FIFO interrupt of device
	277	Device disables its inbound FIFO interrupt
	278	**/
	279	extern void I2OFIFOIntDisable( LOCATION, unsigned int base );
	280
	281	/**
	282	Enable the circular queue overflow interrupt
	283	**/
	284	extern void I2OFIFOOverflowIntEnable( unsigned int eumbbar );
	285
	286	/**
	287	Disable the circular queue overflow interrupt
	288	**/
	289	extern void I2OFIFOOverflowIntDisable( unsigned int eumbbar );
	290
	291	/**
	292	Allocate a free msg frame from free FIFO.
	293
	294	PCI Master allocates a free msg frame through inbound queue port of device(IFQPR)
	295	while local processor allocates a free msg frame from outbound free queue(OFTPR)
	296
	297	Unless both free queues are initialized, allocating a free MF will return 0xffffffff
	298	**/
	299	extern I2OSTATUS I2OFIFOAlloc( LOCATION,
8bde7f77 WD	300	unsigned int base,
8bde7f77 WD	301	void **pMsg);
327f7a02 WD	302	/**
	303	Free a used msg frame back to free queue
	304	PCI Master frees a MFA through outbound queue port of device(OFQPR)
	305	while local processor frees a MFA into its inbound free queue(IFHPR)
	306
	307	Used msg frame does not need to be recycled in the order they
	308	read
	309
	310	This function has to be called by PCI master to initialize Inbound free queue
	311	and by device to initialize Outbound free queue before I2OFIFOAlloc can be used.
	312	**/
	313	extern I2OSTATUS I2OFIFOFree( LOCATION,
8bde7f77 WD	314	unsigned int base,
8bde7f77 WD	315	void *pMsg );
327f7a02 WD	316
	317	/**
	318	Post a msg into FIFO
	319	PCI Master posts a msg through inbound queue port of device(IFQPR)
	320	while local processor post a msg into its outbound post queue(OPHPR)
	321
	322	The total number of msg must be less than the max size of the queue
	323	Otherwise queue overflow interrupt will assert.
	324	**/
	325	extern I2OSTATUS I2OFIFOPost( LOCATION,
8bde7f77 WD	326	unsigned int base,
8bde7f77 WD	327	void *pMsg );
327f7a02 WD	328
	329	/**
	330	Read a msg from FIFO
	331	PCI Master reads a msg through outbound queue port of device(OFQPR)
	332	while local processor reads a msg from its inbound post queue(IPTPR)
	333	**/
	334	extern I2OSTATUS I2OFIFOGet( LOCATION,
8bde7f77	335	unsigned int base,
327f7a02 WD	336	void **pMsg );
	337
	338	/**
	339	Get the I2O PCI configuration identification register
	340	**/
	341	extern I2OSTATUS I2OPCIConfigGet( LOCATION,
8bde7f77	342	unsigned int base,
327f7a02 WD	343	I2OIOP *);
	344
	345	#endif