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Patches by Murray Jensen, 17 Jun 2003:
[people/ms/u-boot.git] / cpu / mpc8260 / ether_fcc.c
CommitLineData
affae2bf
WD		 1/*
2 * MPC8260 FCC Fast Ethernet
3 *
4 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
5 *
6 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28/*
29 * MPC8260 FCC Fast Ethernet
30 * Basic ET HW initialization and packet RX/TX routines
31 *
32 * This code will not perform the IO port configuration. This should be
33 * done in the iop_conf_t structure specific for the board.
34 *
35 * TODO:
36 * add a PHY driver to do the negotiation
37 * reflect negotiation results in FPSMR
38 * look for ways to configure the board specific stuff elsewhere, eg.
39 * config_xxx.h or the board directory
40 */
41
42#include <common.h>
aacf9a49 43#include <malloc.h>
affae2bf
WD		 44#include <asm/cpm_8260.h>
45#include <mpc8260.h>
affae2bf
WD		 46#include <command.h>
47#include <config.h>
aacf9a49 48#include <net.h>
affae2bf 49
aacf9a49
WD		 50#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
51 defined(CONFIG_NET_MULTI)
affae2bf 52
aacf9a49
WD		 53static struct ether_fcc_info_s
54{
55 int ether_index;
56 int proff_enet;
57 ulong cpm_cr_enet_sblock;
58 ulong cpm_cr_enet_page;
59 ulong cmxfcr_mask;
60 ulong cmxfcr_value;
61}
62 ether_fcc_info[] =
63{
64#ifdef CONFIG_ETHER_ON_FCC1
65{
66 0,
67 PROFF_FCC1,
68 CPM_CR_FCC1_SBLOCK,
69 CPM_CR_FCC1_PAGE,
70 CFG_CMXFCR_MASK1,
71 CFG_CMXFCR_VALUE1
72},
73#endif
affae2bf 74
aacf9a49
WD		 75#ifdef CONFIG_ETHER_ON_FCC2
76{
77 1,
78 PROFF_FCC2,
79 CPM_CR_FCC2_SBLOCK,
80 CPM_CR_FCC2_PAGE,
81 CFG_CMXFCR_MASK2,
82 CFG_CMXFCR_VALUE2
83},
84#endif
affae2bf 85
aacf9a49
WD		 86#ifdef CONFIG_ETHER_ON_FCC3
87{
88 2,
89 PROFF_FCC3,
90 CPM_CR_FCC3_SBLOCK,
91 CPM_CR_FCC3_PAGE,
92 CFG_CMXFCR_MASK3,
93 CFG_CMXFCR_VALUE3
94},
affae2bf 95#endif
aacf9a49
WD		 96};
97
affae2bf
WD		 98/*---------------------------------------------------------------------*/
99
100/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
101#define PKT_MAXDMA_SIZE 1520
102
103/* The FCC stores dest/src/type, data, and checksum for receive packets. */
104#define PKT_MAXBUF_SIZE 1518
105#define PKT_MINBUF_SIZE 64
106
107/* Maximum input buffer size. Must be a multiple of 32. */
108#define PKT_MAXBLR_SIZE 1536
109
110#define TOUT_LOOP 1000000
111
112#define TX_BUF_CNT 2
113#ifdef __GNUC__
114static char txbuf[TX_BUF_CNT][PKT_MAXBLR_SIZE] __attribute__ ((aligned(8)));
115#else
116#error "txbuf must be 64-bit aligned"
117#endif
118
119static uint rxIdx; /* index of the current RX buffer */
120static uint txIdx; /* index of the current TX buffer */
121
122/*
123 * FCC Ethernet Tx and Rx buffer descriptors.
124 * Provide for Double Buffering
125 * Note: PKTBUFSRX is defined in net.h
126 */
127
128typedef volatile struct rtxbd {
129 cbd_t rxbd[PKTBUFSRX];
130 cbd_t txbd[TX_BUF_CNT];
131} RTXBD;
132
133/* Good news: the FCC supports external BDs! */
134#ifdef __GNUC__
135static RTXBD rtx __attribute__ ((aligned(8)));
136#else
137#error "rtx must be 64-bit aligned"
138#endif
139
aacf9a49 140static int fec_send(struct eth_device* dev, volatile void *packet, int length)
affae2bf
WD		 141{
142 int i;
143 int result = 0;
144
145 if (length <= 0) {
146 printf("fec: bad packet size: %d\n", length);
147 goto out;
148 }
149
150 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
151 if (i >= TOUT_LOOP) {
152 printf("fec: tx buffer not ready\n");
153 goto out;
154 }
155 }
156
157 rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
158 rtx.txbd[txIdx].cbd_datlen = length;
159 rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
160 BD_ENET_TX_WRAP);
161
162 for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
163 if (i >= TOUT_LOOP) {
164 printf("fec: tx error\n");
165 goto out;
166 }
167 }
168
169#ifdef ET_DEBUG
170 printf("cycles: %d status: %04x\n", i, rtx.txbd[txIdx].cbd_sc);
171#endif
172
173 /* return only status bits */
174 result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
175
176out:
177 return result;
178}
179
aacf9a49 180static int fec_recv(struct eth_device* dev)
affae2bf
WD		 181{
182 int length;
183
184 for (;;)
185 {
186 if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
187 length = -1;
188 break; /* nothing received - leave for() loop */
189 }
190 length = rtx.rxbd[rxIdx].cbd_datlen;
191
192 if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
193 printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
194 }
195 else {
196 /* Pass the packet up to the protocol layers. */
197 NetReceive(NetRxPackets[rxIdx], length - 4);
198 }
199
200
201 /* Give the buffer back to the FCC. */
202 rtx.rxbd[rxIdx].cbd_datlen = 0;
203
204 /* wrap around buffer index when necessary */
205 if ((rxIdx + 1) >= PKTBUFSRX) {
206 rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
207 rxIdx = 0;
208 }
209 else {
210 rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
211 rxIdx++;
212 }
213 }
214 return length;
215}
216
217
aacf9a49 218static int fec_init(struct eth_device* dev, bd_t *bis)
affae2bf 219{
aacf9a49 220 struct ether_fcc_info_s * info = dev->priv;
affae2bf
WD		 221 int i;
222 volatile immap_t *immr = (immap_t *)CFG_IMMR;
223 volatile cpm8260_t *cp = &(immr->im_cpm);
224 fcc_enet_t *pram_ptr;
225 unsigned long mem_addr;
226
227#if 0
228 mii_discover_phy();
229#endif
230
231 /* 28.9 - (1-2): ioports have been set up already */
232
233 /* 28.9 - (3): connect FCC's tx and rx clocks */
234 immr->im_cpmux.cmx_uar = 0;
aacf9a49
WD		 235 immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~info->cmxfcr_mask) |
236 info->cmxfcr_value;
affae2bf
WD		 237
238 /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
aacf9a49 239 immr->im_fcc[info->ether_index].fcc_gfmr =
affae2bf
WD		 240 FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
241
242 /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */
aacf9a49 243 immr->im_fcc[info->ether_index].fcc_fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
affae2bf
WD		 244
245 /* 28.9 - (6): FDSR: Ethernet Syn */
aacf9a49 246 immr->im_fcc[info->ether_index].fcc_fdsr = 0xD555;
affae2bf
WD		 247
248 /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
249 rxIdx = 0;
250 txIdx = 0;
251
252 /* Setup Receiver Buffer Descriptors */
253 for (i = 0; i < PKTBUFSRX; i++)
254 {
255 rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
256 rtx.rxbd[i].cbd_datlen = 0;
257 rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
258 }
259 rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
260
261 /* Setup Ethernet Transmitter Buffer Descriptors */
262 for (i = 0; i < TX_BUF_CNT; i++)
263 {
264 rtx.txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
265 rtx.txbd[i].cbd_datlen = 0;
266 rtx.txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
267 }
268 rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
269
270 /* 28.9 - (7): initialise parameter ram */
aacf9a49 271 pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[info->proff_enet]);
affae2bf
WD		 272
273 /* clear whole structure to make sure all reserved fields are zero */
274 memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
275
276 /*
277 * common Parameter RAM area
278 *
279 * Allocate space in the reserved FCC area of DPRAM for the
280 * internal buffers. No one uses this space (yet), so we
281 * can do this. Later, we will add resource management for
282 * this area.
283 */
aacf9a49 284 mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
affae2bf
WD		 285 pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
286 pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
287 /*
288 * Set maximum bytes per receive buffer.
289 * It must be a multiple of 32.
290 */
291 pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
292 pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
293 CFG_CPMFCR_RAMTYPE) << 24;
294 pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
295 pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
296 CFG_CPMFCR_RAMTYPE) << 24;
297 pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
298
299 /* protocol-specific area */
300 pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
301 pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
302 pram_ptr->fen_retlim = 15; /* Retry limit threshold */
303 pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
304 /*
305 * Set Ethernet station address.
306 *
307 * This is supplied in the board information structure, so we
308 * copy that into the controller.
309 * So, far we have only been given one Ethernet address. We make
310 * it unique by setting a few bits in the upper byte of the
311 * non-static part of the address.
312 */
aacf9a49 313#define ea eth_get_dev()->enetaddr
affae2bf
WD		 314 pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
315 pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
316 pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
317#undef ea
318 pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
319 /* pad pointer. use tiptr since we don't need a specific padding char */
320 pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
321 pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */
322 pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */
323 pram_ptr->fen_rfthr = 1;
324 pram_ptr->fen_rfcnt = 1;
325#if 0
326 printf("pram_ptr->fen_genfcc.fcc_rbase %08lx\n",
327 pram_ptr->fen_genfcc.fcc_rbase);
328 printf("pram_ptr->fen_genfcc.fcc_tbase %08lx\n",
329 pram_ptr->fen_genfcc.fcc_tbase);
330#endif
331
332 /* 28.9 - (8): clear out events in FCCE */
aacf9a49 333 immr->im_fcc[info->ether_index].fcc_fcce = ~0x0;
affae2bf
WD		 334
335 /* 28.9 - (9): FCCM: mask all events */
aacf9a49 336 immr->im_fcc[info->ether_index].fcc_fccm = 0;
affae2bf
WD		 337
338 /* 28.9 - (10-12): we don't use ethernet interrupts */
339
340 /* 28.9 - (13)
341 *
342 * Let's re-initialize the channel now. We have to do it later
343 * than the manual describes because we have just now finished
344 * the BD initialization.
345 */
aacf9a49
WD		 346 cp->cp_cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
347 info->cpm_cr_enet_sblock,
affae2bf
WD		 348 0x0c,
349 CPM_CR_INIT_TRX) | CPM_CR_FLG;
350 do {
351 __asm__ __volatile__ ("eieio");
352 } while (cp->cp_cpcr & CPM_CR_FLG);
353
354 /* 28.9 - (14): enable tx/rx in gfmr */
aacf9a49 355 immr->im_fcc[info->ether_index].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
affae2bf
WD		 356
357 return 1;
358}
359
aacf9a49 360static void fec_halt(struct eth_device* dev)
affae2bf 361{
aacf9a49 362 struct ether_fcc_info_s * info = dev->priv;
affae2bf
WD		 363 volatile immap_t *immr = (immap_t *)CFG_IMMR;
364
365 /* write GFMR: disable tx/rx */
aacf9a49 366 immr->im_fcc[info->ether_index].fcc_gfmr &=
affae2bf
WD		 367 ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
368}
369
aacf9a49
WD		 370int fec_initialize(bd_t *bis)
371{
372 struct eth_device* dev;
373 int i;
374
375 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
376 {
377 dev = (struct eth_device*) malloc(sizeof *dev);
378 memset(dev, 0, sizeof *dev);
379
380 sprintf(dev->name, "FCC%d ETHERNET",
381 ether_fcc_info[i].ether_index + 1);
382 dev->priv = &ether_fcc_info[i];
383 dev->init = fec_init;
384 dev->halt = fec_halt;
385 dev->send = fec_send;
386 dev->recv = fec_recv;
387
388 eth_register(dev);
389 }
390
391 return 1;
392}
393
6dd652fa
WD		 394#ifdef CONFIG_ETHER_LOOPBACK_TEST
395
396#define ELBT_BUFSZ 1024 /* must be multiple of 32 */
397
398#define ELBT_CRCSZ 4
399
400#define ELBT_NRXBD 4 /* must be at least 2 */
401#define ELBT_NTXBD 4
402
403#define ELBT_MAXRXERR 32
404#define ELBT_MAXTXERR 32
405
406#define ELBT_CLSWAIT 1000 /* msec to wait for further input frames */
407
408typedef
409 struct {
410 uint off;
411 char *lab;
412 }
413elbt_prdesc;
414
415typedef
416 struct {
417 uint _l, _f, m, bc, mc, lg, no, sh, cr, ov, cl;
418 uint badsrc, badtyp, badlen, badbit;
419 }
420elbt_rxeacc;
421
422static elbt_prdesc rxeacc_descs[] = {
423 { offsetof(elbt_rxeacc, _l), "Not Last in Frame" },
424 { offsetof(elbt_rxeacc, _f), "Not First in Frame" },
425 { offsetof(elbt_rxeacc, m), "Address Miss" },
426 { offsetof(elbt_rxeacc, bc), "Broadcast Address" },
427 { offsetof(elbt_rxeacc, mc), "Multicast Address" },
428 { offsetof(elbt_rxeacc, lg), "Frame Length Violation"},
429 { offsetof(elbt_rxeacc, no), "Non-Octet Alignment" },
430 { offsetof(elbt_rxeacc, sh), "Short Frame" },
431 { offsetof(elbt_rxeacc, cr), "CRC Error" },
432 { offsetof(elbt_rxeacc, ov), "Overrun" },
433 { offsetof(elbt_rxeacc, cl), "Collision" },
434 { offsetof(elbt_rxeacc, badsrc), "Bad Src Address" },
435 { offsetof(elbt_rxeacc, badtyp), "Bad Frame Type" },
436 { offsetof(elbt_rxeacc, badlen), "Bad Frame Length" },
437 { offsetof(elbt_rxeacc, badbit), "Data Compare Errors" },
438};
439static int rxeacc_ndesc = sizeof (rxeacc_descs) / sizeof (rxeacc_descs[0]);
440
441typedef
442 struct {
443 uint def, hb, lc, rl, rc, un, csl;
444 }
445elbt_txeacc;
446
447static elbt_prdesc txeacc_descs[] = {
448 { offsetof(elbt_txeacc, def), "Defer Indication" },
449 { offsetof(elbt_txeacc, hb), "Heartbeat" },
450 { offsetof(elbt_txeacc, lc), "Late Collision" },
451 { offsetof(elbt_txeacc, rl), "Retransmission Limit" },
452 { offsetof(elbt_txeacc, rc), "Retry Count" },
453 { offsetof(elbt_txeacc, un), "Underrun" },
454 { offsetof(elbt_txeacc, csl), "Carrier Sense Lost" },
455};
456static int txeacc_ndesc = sizeof (txeacc_descs) / sizeof (txeacc_descs[0]);
457
458typedef
459 struct {
460 uchar rxbufs[ELBT_NRXBD][ELBT_BUFSZ];
461 uchar txbufs[ELBT_NTXBD][ELBT_BUFSZ];
462 cbd_t rxbd[ELBT_NRXBD];
463 cbd_t txbd[ELBT_NTXBD];
464 enum { Idle, Running, Closing, Closed } state;
465 int proff, page, sblock;
466 uint clstime, nsent, ntxerr, nrcvd, nrxerr;
467 ushort rxerrs[ELBT_MAXRXERR], txerrs[ELBT_MAXTXERR];
468 elbt_rxeacc rxeacc;
469 elbt_txeacc txeacc;
470 } __attribute__ ((aligned(8)))
471elbt_chan;
472
473static uchar patbytes[ELBT_NTXBD] = {
474 0xff, 0xaa, 0x55, 0x00
475};
476static uint patwords[ELBT_NTXBD] = {
477 0xffffffff, 0xaaaaaaaa, 0x55555555, 0x00000000
478};
479
480#ifdef __GNUC__
481static elbt_chan elbt_chans[3] __attribute__ ((aligned(8)));
482#else
483#error "elbt_chans must be 64-bit aligned"
484#endif
485
486#define CPM_CR_GRACEFUL_STOP_TX ((ushort)0x0005)
487
488static elbt_prdesc epram_descs[] = {
489 { offsetof(fcc_enet_t, fen_crcec), "CRC Errors" },
490 { offsetof(fcc_enet_t, fen_alec), "Alignment Errors" },
491 { offsetof(fcc_enet_t, fen_disfc), "Discarded Frames" },
492 { offsetof(fcc_enet_t, fen_octc), "Octets" },
493 { offsetof(fcc_enet_t, fen_colc), "Collisions" },
494 { offsetof(fcc_enet_t, fen_broc), "Broadcast Frames" },
495 { offsetof(fcc_enet_t, fen_mulc), "Multicast Frames" },
496 { offsetof(fcc_enet_t, fen_uspc), "Undersize Frames" },
497 { offsetof(fcc_enet_t, fen_frgc), "Fragments" },
498 { offsetof(fcc_enet_t, fen_ospc), "Oversize Frames" },
499 { offsetof(fcc_enet_t, fen_jbrc), "Jabbers" },
500 { offsetof(fcc_enet_t, fen_p64c), "64 Octet Frames" },
501 { offsetof(fcc_enet_t, fen_p65c), "65-127 Octet Frames" },
502 { offsetof(fcc_enet_t, fen_p128c), "128-255 Octet Frames" },
503 { offsetof(fcc_enet_t, fen_p256c), "256-511 Octet Frames" },
504 { offsetof(fcc_enet_t, fen_p512c), "512-1023 Octet Frames" },
505 { offsetof(fcc_enet_t, fen_p1024c), "1024-1518 Octet Frames"},
506};
507static int epram_ndesc = sizeof (epram_descs) / sizeof (epram_descs[0]);
508
509/*
510 * given an elbt_prdesc array and an array of base addresses, print
511 * each prdesc down the screen with the values fetched from each
512 * base address across the screen
513 */
514static void
515print_desc (elbt_prdesc descs[], int ndesc, uchar *bases[], int nbase)
516{
517 elbt_prdesc *dp = descs, *edp = dp + ndesc;
518 int i;
519
520 printf ("%32s", "");
521
522 for (i = 0; i < nbase; i++)
523 printf (" Channel %d", i);
524
525 puts ("\n");
526
527 while (dp < edp) {
528
529 printf ("%-32s", dp->lab);
530
531 for (i = 0; i < nbase; i++) {
532 uint val = *(uint *)(bases[i] + dp->off);
533
534 printf (" %10u", val);
535 }
536
537 puts ("\n");
538
539 dp++;
540 }
541}
542
543/*
544 * return number of bits that are set in a value; value contains
545 * nbits (right-justified) bits.
546 */
547static uint __inline__
548nbs (uint value, uint nbits)
549{
550 uint cnt = 0;
551#if 1
552 uint pos = sizeof (uint) * 8;
553
554 __asm__ __volatile__ ("\
555 mtctr %2\n\
5561: rlwnm. %2,%1,%4,31,31\n\
557 beq 2f\n\
558 addi %0,%0,1\n\
5592: subi %4,%4,1\n\
560 bdnz 1b"
561 : "=r"(cnt)
562 : "r"(value), "r"(nbits), "r"(cnt), "r"(pos)
563 : "ctr", "cc" );
564#else
565 uint mask = 1;
566
567 do {
568 if (value & mask)
569 cnt++;
570 mask <<= 1;
571 } while (--nbits);
572#endif
573
574 return (cnt);
575}
576
577static ulong
578badbits (uchar *bp, int n, ulong pat)
579{
580 ulong *lp, cnt = 0;
581 int nl;
582
583 while (n > 0 && ((ulong)bp & (sizeof (ulong) - 1)) != 0) {
584 uchar diff;
585
586 diff = *bp++ ^ (uchar)pat;
587
588 if (diff)
589 cnt += nbs ((ulong)diff, 8);
590
591 n--;
592 }
593
594 lp = (ulong *)bp;
595 nl = n / sizeof (ulong);
596 n -= nl * sizeof (ulong);
597
598 while (nl > 0) {
599 ulong diff;
600
601 diff = *lp++ ^ pat;
602
603 if (diff)
604 cnt += nbs (diff, 32);
605
606 nl--;
607 }
608
609 bp = (uchar *)lp;
610
611 while (n > 0) {
612 uchar diff;
613
614 diff = *bp++ ^ (uchar)pat;
615
616 if (diff)
617 cnt += nbs ((ulong)diff, 8);
618
619 n--;
620 }
621
622 return (cnt);
623}
624
625static inline unsigned short
626swap16 (unsigned short x)
627{
628 return (((x & 0xff) << 8) | ((x & 0xff00) >> 8));
629}
630
631void
632eth_loopback_test (void)
633{
634 DECLARE_GLOBAL_DATA_PTR;
635
636 volatile immap_t *immr = (immap_t *)CFG_IMMR;
637 volatile cpm8260_t *cp = &(immr->im_cpm);
638 int c, nclosed;
639 ulong runtime, nmsec;
640 uchar *bases[3];
641
642 puts ("FCC Ethernet External loopback test\n");
643
644 memcpy (NetOurEther, gd->bd->bi_enetaddr, 6);
645
646 /*
647 * global initialisations for all FCC channels
648 */
649
650 /* 28.9 - (1-2): ioports have been set up already */
651
652#if defined(CONFIG_HYMOD)
653 /*
654 * Attention: this is board-specific
655 * - FCC1 Rx-CLK is CLK10
656 * - FCC1 Tx-CLK is CLK11
657 * - FCC2 Rx-CLK is CLK13
658 * - FCC2 Tx-CLK is CLK14
659 * - FCC3 Rx-CLK is CLK15
660 * - FCC3 Tx-CLK is CLK16
661 */
662
663 /* 28.9 - (3): connect FCC's tx and rx clocks */
664 immr->im_cpmux.cmx_uar = 0;
665 immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\
666 CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\
667 CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16;
668#else
669#error "eth_loopback_test not supported on your board"
670#endif
671
672 puts ("Initialise FCC channels:");
673
674 for (c = 0; c < 3; c++) {
675 elbt_chan *ecp = &elbt_chans[c];
676 volatile fcc_t *fcp = &immr->im_fcc[c];
677 volatile fcc_enet_t *fpp;
678 int i;
679 ulong addr;
680
681 /*
682 * initialise channel data
683 */
684
685 printf (" %d", c);
686
687 memset ((void *)ecp, 0, sizeof (*ecp));
688
689 ecp->state = Idle;
690
691 switch (c) {
692
693 case 0: /* FCC1 */
694 ecp->proff = PROFF_FCC1;
695 ecp->page = CPM_CR_FCC1_PAGE;
696 ecp->sblock = CPM_CR_FCC1_SBLOCK;
697 break;
698
699 case 1: /* FCC2 */
700 ecp->proff = PROFF_FCC2;
701 ecp->page = CPM_CR_FCC2_PAGE;
702 ecp->sblock = CPM_CR_FCC2_SBLOCK;
703 break;
704
705 case 2: /* FCC3 */
706 ecp->proff = PROFF_FCC3;
707 ecp->page = CPM_CR_FCC3_PAGE;
708 ecp->sblock = CPM_CR_FCC3_SBLOCK;
709 break;
710 }
711
712 /*
713 * set up tx buffers and bds
714 */
715
716 for (i = 0; i < ELBT_NTXBD; i++) {
717 cbd_t *bdp = &ecp->txbd[i];
718 uchar *bp = &ecp->txbufs[i][0];
719
720 bdp->cbd_bufaddr = (uint)bp;
721 /* room for crc */
722 bdp->cbd_datlen = ELBT_BUFSZ - ELBT_CRCSZ;
723 bdp->cbd_sc = BD_ENET_TX_READY | BD_ENET_TX_PAD | \
724 BD_ENET_TX_LAST | BD_ENET_TX_TC;
725
726 memset ((void *)bp, patbytes[i], ELBT_BUFSZ);
727 NetSetEther (bp, NetBcastAddr, 0x8000);
728 }
729 ecp->txbd[ELBT_NTXBD - 1].cbd_sc |= BD_ENET_TX_WRAP;
730
731 /*
732 * set up rx buffers and bds
733 */
734
735 for (i = 0; i < ELBT_NRXBD; i++) {
736 cbd_t *bdp = &ecp->rxbd[i];
737 uchar *bp = &ecp->rxbufs[i][0];
738
739 bdp->cbd_bufaddr = (uint)bp;
740 bdp->cbd_datlen = 0;
741 bdp->cbd_sc = BD_ENET_RX_EMPTY;
742
743 memset ((void *)bp, 0, ELBT_BUFSZ);
744 }
745 ecp->rxbd[ELBT_NRXBD - 1].cbd_sc |= BD_ENET_RX_WRAP;
746
747 /*
748 * set up the FCC channel hardware
749 */
750
751 /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
752 fcp->fcc_gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
753
754 /* 28.9 - (5): FPSMR: fd, enet CRC, Promis, RMON, Rx SHort */
755 fcp->fcc_fpsmr = FCC_PSMR_FDE | FCC_PSMR_LPB | \
756 FCC_PSMR_ENCRC | FCC_PSMR_PRO | \
757 FCC_PSMR_MON | FCC_PSMR_RSH;
758
759 /* 28.9 - (6): FDSR: Ethernet Syn */
760 fcp->fcc_fdsr = 0xD555;
761
762 /* 29.9 - (7): initialise parameter ram */
763 fpp = (fcc_enet_t *)&(immr->im_dprambase[ecp->proff]);
764
765 /* clear whole struct to make sure all resv fields are zero */
766 memset ((void *)fpp, 0, sizeof (fcc_enet_t));
767
768 /*
769 * common Parameter RAM area
770 *
771 * Allocate space in the reserved FCC area of DPRAM for the
772 * internal buffers. No one uses this space (yet), so we
773 * can do this. Later, we will add resource management for
774 * this area.
775 */
776 addr = CPM_FCC_SPECIAL_BASE + (c * 64);
777 fpp->fen_genfcc.fcc_riptr = addr;
778 fpp->fen_genfcc.fcc_tiptr = addr + 32;
779
780 /*
781 * Set maximum bytes per receive buffer.
782 * It must be a multiple of 32.
783 * buffers are in 60x bus memory.
784 */
785 fpp->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
786 fpp->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
787 fpp->fen_genfcc.fcc_rbase = (unsigned int)(&ecp->rxbd[0]);
788 fpp->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
789 fpp->fen_genfcc.fcc_tbase = (unsigned int)(&ecp->txbd[0]);
790
791 /* protocol-specific area */
792 fpp->fen_cmask = 0xdebb20e3; /* CRC mask */
793 fpp->fen_cpres = 0xffffffff; /* CRC preset */
794 fpp->fen_retlim = 15; /* Retry limit threshold */
795 fpp->fen_mflr = PKT_MAXBUF_SIZE;/* max frame length register */
796
797 /*
798 * Set Ethernet station address.
799 *
800 * This is supplied in the board information structure, so we
801 * copy that into the controller.
802 * So, far we have only been given one Ethernet address. We use
803 * the same address for all channels
804 */
805#define ea gd->bd->bi_enetaddr
806 fpp->fen_paddrh = (ea[5] << 8) + ea[4];
807 fpp->fen_paddrm = (ea[3] << 8) + ea[2];
808 fpp->fen_paddrl = (ea[1] << 8) + ea[0];
809#undef ea
810
811 fpp->fen_minflr = PKT_MINBUF_SIZE; /* min frame len register */
812 /*
813 * pad pointer. use tiptr since we don't need
814 * a specific padding char
815 */
816 fpp->fen_padptr = fpp->fen_genfcc.fcc_tiptr;
817 fpp->fen_maxd1 = PKT_MAXDMA_SIZE; /* max DMA1 length */
818 fpp->fen_maxd2 = PKT_MAXDMA_SIZE; /* max DMA2 length */
819 fpp->fen_rfthr = 1;
820 fpp->fen_rfcnt = 1;
821
822 /* 28.9 - (8): clear out events in FCCE */
823 fcp->fcc_fcce = ~0x0;
824
825 /* 28.9 - (9): FCCM: mask all events */
826 fcp->fcc_fccm = 0;
827
828 /* 28.9 - (10-12): we don't use ethernet interrupts */
829
830 /* 28.9 - (13)
831 *
832 * Let's re-initialize the channel now. We have to do it later
833 * than the manual describes because we have just now finished
834 * the BD initialization.
835 */
836 cp->cp_cpcr = mk_cr_cmd (ecp->page, ecp->sblock, \
837 0x0c, CPM_CR_INIT_TRX) | CPM_CR_FLG;
838 do {
839 __asm__ __volatile__ ("eieio");
840 } while (cp->cp_cpcr & CPM_CR_FLG);
841 }
842
843 puts (" done\nStarting test... (Ctrl-C to Finish)\n");
844
845 /*
846 * Note: don't want serial output from here until the end of the
847 * test - the delays would probably stuff things up.
848 */
849
850 clear_ctrlc ();
851 runtime = get_timer (0);
852
853 do {
854 nclosed = 0;
855
856 for (c = 0; c < 3; c++) {
857 volatile fcc_t *fcp = &immr->im_fcc[c];
858 elbt_chan *ecp = &elbt_chans[c];
859 int i;
860
861 switch (ecp->state) {
862
863 case Idle:
864 /*
865 * set the channel Running ...
866 */
867
868 /* 28.9 - (14): enable tx/rx in gfmr */
869 fcp->fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
870
871 ecp->state = Running;
872 break;
873
874 case Running:
875 /*
876 * (while Running only) check for
877 * termination of the test
878 */
879
880 (void)ctrlc ();
881
882 if (had_ctrlc ()) {
883 /*
884 * initiate a "graceful stop transmit"
885 * on the channel
886 */
887 cp->cp_cpcr = mk_cr_cmd (ecp->page, \
888 ecp->sblock, 0x0c, \
889 CPM_CR_GRACEFUL_STOP_TX) | \
890 CPM_CR_FLG;
891 do {
892 __asm__ __volatile__ ("eieio");
893 } while (cp->cp_cpcr & CPM_CR_FLG);
894
895 ecp->clstime = get_timer (0);
896 ecp->state = Closing;
897 }
898 /* fall through ... */
899
900 case Closing:
901 /*
902 * (while Running or Closing) poll the channel:
903 * - check for any non-READY tx buffers and
904 * make them ready
905 * - check for any non-EMPTY rx buffers and
906 * check that they were received correctly,
907 * adjust counters etc, then make empty
908 */
909
910 for (i = 0; i < ELBT_NTXBD; i++) {
911 cbd_t *bdp = &ecp->txbd[i];
912 ushort sc = bdp->cbd_sc;
913
914 if ((sc & BD_ENET_TX_READY) != 0)
915 continue;
916
917 /*
918 * this frame has finished
919 * transmitting
920 */
921 ecp->nsent++;
922
923 if (sc & BD_ENET_TX_STATS) {
924 ulong n;
925
926 /*
927 * we had an error on
928 * the transmission
929 */
930 n = ecp->ntxerr++;
931 if (n < ELBT_MAXTXERR)
932 ecp->txerrs[n] = sc;
933
934 if (sc & BD_ENET_TX_DEF)
935 ecp->txeacc.def++;
936 if (sc & BD_ENET_TX_HB)
937 ecp->txeacc.hb++;
938 if (sc & BD_ENET_TX_LC)
939 ecp->txeacc.lc++;
940 if (sc & BD_ENET_TX_RL)
941 ecp->txeacc.rl++;
942 if (sc & BD_ENET_TX_RCMASK)
943 ecp->txeacc.rc++;
944 if (sc & BD_ENET_TX_UN)
945 ecp->txeacc.un++;
946 if (sc & BD_ENET_TX_CSL)
947 ecp->txeacc.csl++;
948
949 bdp->cbd_sc &= \
950 ~BD_ENET_TX_STATS;
951 }
952
953 if (ecp->state == Closing)
954 ecp->clstime = get_timer (0);
955
956 /* make it ready again */
957 bdp->cbd_sc |= BD_ENET_TX_READY;
958 }
959
960 for (i = 0; i < ELBT_NRXBD; i++) {
961 cbd_t *bdp = &ecp->rxbd[i];
962 ushort sc = bdp->cbd_sc, mask;
963
964 if ((sc & BD_ENET_RX_EMPTY) != 0)
965 continue;
966
967 /* we have a new frame in this buffer */
968 ecp->nrcvd++;
969
970 mask = BD_ENET_RX_LAST|BD_ENET_RX_FIRST;
971 if ((sc & mask) != mask) {
972 /* somethings wrong here ... */
973 if (!(sc & BD_ENET_RX_LAST))
974 ecp->rxeacc._l++;
975 if (!(sc & BD_ENET_RX_FIRST))
976 ecp->rxeacc._f++;
977 }
978
979 if (sc & BD_ENET_RX_STATS) {
980 ulong n;
981
982 /*
983 * we had some sort of error
984 * on the frame
985 */
986 n = ecp->nrxerr++;
987 if (n < ELBT_MAXRXERR)
988 ecp->rxerrs[n] = sc;
989
990 if (sc & BD_ENET_RX_MISS)
991 ecp->rxeacc.m++;
992 if (sc & BD_ENET_RX_BC)
993 ecp->rxeacc.bc++;
994 if (sc & BD_ENET_RX_MC)
995 ecp->rxeacc.mc++;
996 if (sc & BD_ENET_RX_LG)
997 ecp->rxeacc.lg++;
998 if (sc & BD_ENET_RX_NO)
999 ecp->rxeacc.no++;
1000 if (sc & BD_ENET_RX_SH)
1001 ecp->rxeacc.sh++;
1002 if (sc & BD_ENET_RX_CR)
1003 ecp->rxeacc.cr++;
1004 if (sc & BD_ENET_RX_OV)
1005 ecp->rxeacc.ov++;
1006 if (sc & BD_ENET_RX_CL)
1007 ecp->rxeacc.cl++;
1008
1009 bdp->cbd_sc &= \
1010 ~BD_ENET_RX_STATS;
1011 }
1012 else {
1013 ushort datlen = bdp->cbd_datlen;
1014 Ethernet_t *ehp;
1015 ushort prot;
1016 int ours, tb, n, nbytes;
1017
1018 ehp = (Ethernet_t *) \
1019 &ecp->rxbufs[i][0];
1020
1021 ours = memcmp (ehp->et_src, \
1022 NetOurEther, 6);
1023
1024 prot = swap16 (ehp->et_protlen);
1025 tb = prot & 0x8000;
1026 n = prot & 0x7fff;
1027
1028 nbytes = ELBT_BUFSZ - \
1029 offsetof (Ethernet_t, \
1030 et_dsap) - \
1031 ELBT_CRCSZ;
1032
1033 /* check the frame is correct */
1034 if (datlen != ELBT_BUFSZ)
1035 ecp->rxeacc.badlen++;
1036 else if (!ours)
1037 ecp->rxeacc.badsrc++;
1038 else if (!tb || n >= ELBT_NTXBD)
1039 ecp->rxeacc.badtyp++;
1040 else {
1041 ulong patword = \
1042 patwords[n];
1043 uint nbb;
1044
1045 nbb = badbits ( \
1046 &ehp->et_dsap, \
1047 nbytes, \
1048 patword);
1049
1050 ecp->rxeacc.badbit += \
1051 nbb;
1052 }
1053 }
1054
1055 if (ecp->state == Closing)
1056 ecp->clstime = get_timer (0);
1057
1058 /* make it empty again */
1059 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
1060 }
1061
1062 if (ecp->state != Closing)
1063 break;
1064
1065 /*
1066 * (while Closing) check to see if
1067 * waited long enough
1068 */
1069
1070 if (get_timer (ecp->clstime) >= ELBT_CLSWAIT) {
1071 /* write GFMR: disable tx/rx */
1072 fcp->fcc_gfmr &= \
1073 ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
1074 ecp->state = Closed;
1075 }
1076
1077 break;
1078
1079 case Closed:
1080 nclosed++;
1081 break;
1082 }
1083 }
1084
1085 } while (nclosed < 3);
1086
1087 runtime = get_timer (runtime);
1088 if (runtime <= ELBT_CLSWAIT) {
1089 printf ("Whoops! somehow elapsed time (%ld) is wrong (<= %d)\n",
1090 runtime, ELBT_CLSWAIT);
1091 return;
1092 }
1093 nmsec = runtime - ELBT_CLSWAIT;
1094
1095 printf ("Test Finished in %ldms (plus %dms close wait period)!\n\n",
1096 nmsec, ELBT_CLSWAIT);
1097
1098 /*
1099 * now print stats
1100 */
1101
1102 for (c = 0; c < 3; c++) {
1103 elbt_chan *ecp = &elbt_chans[c];
1104 uint rxpps, txpps, nerr;
1105
1106 rxpps = (ecp->nrcvd * 1000) / nmsec;
1107 txpps = (ecp->nsent * 1000) / nmsec;
1108
1109 printf ("Channel %d: %d rcvd (%d pps, %d rxerrs), "
1110 "%d sent (%d pps, %d txerrs)\n\n", c,
1111 ecp->nrcvd, rxpps, ecp->nrxerr,
1112 ecp->nsent, txpps, ecp->ntxerr);
1113
1114 if ((nerr = ecp->nrxerr) > 0) {
1115 ulong i;
1116
1117 printf ("\tFirst %d rx errs:", nerr);
1118 for (i = 0; i < nerr; i++)
1119 printf (" %04x", ecp->rxerrs[i]);
1120 puts ("\n");
1121 }
1122
1123 if ((nerr = ecp->ntxerr) > 0) {
1124 ulong i;
1125
1126 printf ("\tFirst %d tx errs:", nerr);
1127 for (i = 0; i < nerr; i++)
1128 printf (" %04x", ecp->txerrs[i]);
1129 puts ("\n");
1130 }
1131 }
1132
1133 puts ("Receive Error Counts:\n");
1134 for (c = 0; c < 3; c++)
1135 bases[c] = (uchar *)&elbt_chans[c].rxeacc;
1136 print_desc (rxeacc_descs, rxeacc_ndesc, bases, 3);
1137
1138 puts ("\nTransmit Error Counts:\n");
1139 for (c = 0; c < 3; c++)
1140 bases[c] = (uchar *)&elbt_chans[c].txeacc;
1141 print_desc (txeacc_descs, txeacc_ndesc, bases, 3);
1142
1143 puts ("\nRMON(-like) Counters:\n");
1144 for (c = 0; c < 3; c++)
1145 bases[c] = (uchar *)&immr->im_dprambase[elbt_chans[c].proff];
1146 print_desc (epram_descs, epram_ndesc, bases, 3);
1147}
1148
1149#endif /* CONFIG_ETHER_LOOPBACK_TEST */
1150
aacf9a49 1151#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */
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