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fe8c2806 WD |
1 | /* |
2 | * MPC8260 SCC Ethernet | |
3 | * | |
4 | * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net) | |
5 | * | |
6 | * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * (C) Copyright (c) 2001 | |
10 | * Advent Networks, Inc. <http://www.adventnetworks.com> | |
11 | * Jay Monkman <jtm@smoothsmoothie.com> | |
12 | * | |
13 | * See file CREDITS for list of people who contributed to this | |
14 | * project. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License as | |
18 | * published by the Free Software Foundation; either version 2 of | |
19 | * the License, or (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
29 | * MA 02111-1307 USA | |
30 | */ | |
31 | ||
32 | #include <common.h> | |
33 | #include <asm/cpm_8260.h> | |
34 | #include <mpc8260.h> | |
35 | #include <net.h> | |
36 | #include <command.h> | |
37 | #include <config.h> | |
38 | ||
39 | #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_COMMANDS & CFG_CMD_NET) | |
40 | ||
41 | #if (CONFIG_ETHER_INDEX == 1) | |
42 | # define PROFF_ENET PROFF_SCC1 | |
43 | # define CPM_CR_ENET_PAGE CPM_CR_SCC1_PAGE | |
44 | # define CPM_CR_ENET_SBLOCK CPM_CR_SCC1_SBLOCK | |
45 | # define CMXSCR_MASK (CMXSCR_SC1 |\ | |
8bde7f77 WD |
46 | CMXSCR_RS1CS_MSK |\ |
47 | CMXSCR_TS1CS_MSK) | |
fe8c2806 WD |
48 | |
49 | #elif (CONFIG_ETHER_INDEX == 2) | |
50 | # define PROFF_ENET PROFF_SCC2 | |
51 | # define CPM_CR_ENET_PAGE CPM_CR_SCC2_PAGE | |
52 | # define CPM_CR_ENET_SBLOCK CPM_CR_SCC2_SBLOCK | |
53 | # define CMXSCR_MASK (CMXSCR_SC2 |\ | |
8bde7f77 WD |
54 | CMXSCR_RS2CS_MSK |\ |
55 | CMXSCR_TS2CS_MSK) | |
fe8c2806 WD |
56 | |
57 | #elif (CONFIG_ETHER_INDEX == 3) | |
58 | # define PROFF_ENET PROFF_SCC3 | |
59 | # define CPM_CR_ENET_PAGE CPM_CR_SCC3_PAGE | |
60 | # define CPM_CR_ENET_SBLOCK CPM_CR_SCC3_SBLOCK | |
61 | # define CMXSCR_MASK (CMXSCR_SC3 |\ | |
8bde7f77 WD |
62 | CMXSCR_RS3CS_MSK |\ |
63 | CMXSCR_TS3CS_MSK) | |
fe8c2806 WD |
64 | #elif (CONFIG_ETHER_INDEX == 4) |
65 | # define PROFF_ENET PROFF_SCC4 | |
66 | # define CPM_CR_ENET_PAGE CPM_CR_SCC4_PAGE | |
67 | # define CPM_CR_ENET_SBLOCK CPM_CR_SCC4_SBLOCK | |
68 | # define CMXSCR_MASK (CMXSCR_SC4 |\ | |
8bde7f77 WD |
69 | CMXSCR_RS4CS_MSK |\ |
70 | CMXSCR_TS4CS_MSK) | |
fe8c2806 WD |
71 | |
72 | #endif | |
73 | ||
74 | ||
75 | /* Ethernet Transmit and Receive Buffers */ | |
76 | #define DBUF_LENGTH 1520 | |
77 | ||
78 | #define TX_BUF_CNT 2 | |
79 | ||
80 | #define TOUT_LOOP 1000000 | |
81 | ||
82 | static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ]; | |
83 | ||
84 | static uint rxIdx; /* index of the current RX buffer */ | |
85 | static uint txIdx; /* index of the current TX buffer */ | |
86 | ||
87 | /* | |
88 | * SCC Ethernet Tx and Rx buffer descriptors allocated at the | |
89 | * immr->udata_bd address on Dual-Port RAM | |
90 | * Provide for Double Buffering | |
91 | */ | |
92 | ||
93 | typedef volatile struct CommonBufferDescriptor { | |
94 | cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ | |
95 | cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ | |
96 | } RTXBD; | |
97 | ||
98 | static RTXBD *rtx; | |
99 | ||
100 | ||
101 | int eth_send(volatile void *packet, int length) | |
102 | { | |
103 | int i; | |
104 | int result = 0; | |
105 | ||
106 | if (length <= 0) { | |
8bde7f77 WD |
107 | printf("scc: bad packet size: %d\n", length); |
108 | goto out; | |
fe8c2806 WD |
109 | } |
110 | ||
111 | for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { | |
8bde7f77 WD |
112 | if (i >= TOUT_LOOP) { |
113 | printf("scc: tx buffer not ready\n"); | |
114 | goto out; | |
115 | } | |
fe8c2806 WD |
116 | } |
117 | ||
118 | rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; | |
119 | rtx->txbd[txIdx].cbd_datlen = length; | |
120 | rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | | |
8bde7f77 | 121 | BD_ENET_TX_WRAP); |
fe8c2806 WD |
122 | |
123 | for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { | |
8bde7f77 WD |
124 | if (i >= TOUT_LOOP) { |
125 | printf("scc: tx error\n"); | |
126 | goto out; | |
127 | } | |
fe8c2806 WD |
128 | } |
129 | ||
130 | /* return only status bits */ | |
131 | result = rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; | |
132 | ||
133 | out: | |
134 | return result; | |
135 | } | |
136 | ||
137 | ||
138 | int eth_rx(void) | |
139 | { | |
140 | int length; | |
141 | ||
142 | for (;;) | |
143 | { | |
8bde7f77 WD |
144 | if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { |
145 | length = -1; | |
146 | break; /* nothing received - leave for() loop */ | |
147 | } | |
148 | ||
149 | length = rtx->rxbd[rxIdx].cbd_datlen; | |
150 | ||
151 | if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) | |
152 | { | |
153 | printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc); | |
154 | } | |
155 | else | |
156 | { | |
157 | /* Pass the packet up to the protocol layers. */ | |
158 | NetReceive(NetRxPackets[rxIdx], length - 4); | |
159 | } | |
160 | ||
161 | ||
162 | /* Give the buffer back to the SCC. */ | |
163 | rtx->rxbd[rxIdx].cbd_datlen = 0; | |
164 | ||
165 | /* wrap around buffer index when necessary */ | |
166 | if ((rxIdx + 1) >= PKTBUFSRX) { | |
167 | rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | | |
168 | BD_ENET_RX_EMPTY); | |
169 | rxIdx = 0; | |
170 | } | |
171 | else { | |
172 | rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; | |
173 | rxIdx++; | |
174 | } | |
fe8c2806 WD |
175 | } |
176 | return length; | |
177 | } | |
178 | ||
179 | /************************************************************** | |
180 | * | |
181 | * SCC Ethernet Initialization Routine | |
182 | * | |
183 | *************************************************************/ | |
184 | ||
185 | int eth_init(bd_t *bis) | |
186 | { | |
187 | int i; | |
188 | volatile immap_t *immr = (immap_t *)CFG_IMMR; | |
189 | scc_enet_t *pram_ptr; | |
190 | uint dpaddr; | |
191 | ||
192 | rxIdx = 0; | |
193 | txIdx = 0; | |
194 | ||
195 | /* assign static pointer to BD area */ | |
196 | dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16); | |
197 | rtx = (RTXBD *)&immr->im_dprambase[dpaddr]; | |
198 | ||
199 | /* 24.21 - (1-3): ioports have been set up already */ | |
200 | ||
201 | /* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */ | |
202 | immr->im_cpmux.cmx_uar = 0; | |
203 | immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) | | |
8bde7f77 | 204 | CFG_CMXSCR_VALUE); |
fe8c2806 WD |
205 | |
206 | ||
207 | /* 24.21 (6) write RBASE and TBASE to parameter RAM */ | |
208 | pram_ptr = (scc_enet_t *)&(immr->im_dprambase[PROFF_ENET]); | |
209 | pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]); | |
210 | pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]); | |
211 | ||
212 | pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Nrml Ops and Mot byte ordering */ | |
213 | pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Nrml access */ | |
214 | ||
215 | pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. package len 1520 */ | |
216 | ||
217 | pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ | |
218 | pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ | |
219 | ||
220 | ||
221 | /* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */ | |
222 | while(immr->im_cpm.cp_cpcr & CPM_CR_FLG); | |
223 | immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE, | |
8bde7f77 WD |
224 | CPM_CR_ENET_SBLOCK, |
225 | 0x0c, | |
226 | CPM_CR_INIT_TRX) | CPM_CR_FLG; | |
fe8c2806 WD |
227 | |
228 | /* 24.21 - (8-18): Set up parameter RAM */ | |
229 | pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ | |
230 | pram_ptr->sen_alec = 0x0; /* Align Error Counter (unused) */ | |
231 | pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ | |
232 | ||
233 | pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ | |
234 | ||
235 | pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ | |
236 | ||
237 | pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ | |
238 | pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ | |
239 | ||
240 | pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ | |
241 | pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ | |
242 | ||
243 | pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ | |
244 | pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ | |
245 | pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ | |
246 | pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ | |
247 | ||
248 | # define ea bis->bi_enetaddr | |
249 | pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; | |
250 | pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; | |
251 | pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; | |
252 | # undef ea | |
253 | ||
254 | pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ | |
255 | ||
256 | pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ | |
257 | pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ | |
258 | pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ | |
259 | pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ | |
260 | ||
261 | pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ | |
262 | pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ | |
263 | pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ | |
264 | ||
265 | ||
266 | /* 24.21 - (19): Initialize RxBD */ | |
267 | for (i = 0; i < PKTBUFSRX; i++) | |
268 | { | |
8bde7f77 WD |
269 | rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; |
270 | rtx->rxbd[i].cbd_datlen = 0; /* Reset */ | |
271 | rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; | |
fe8c2806 WD |
272 | } |
273 | ||
274 | rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; | |
275 | ||
276 | /* 24.21 - (20): Initialize TxBD */ | |
277 | for (i = 0; i < TX_BUF_CNT; i++) | |
278 | { | |
8bde7f77 WD |
279 | rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD | |
280 | BD_ENET_TX_LAST | | |
281 | BD_ENET_TX_TC); | |
282 | rtx->txbd[i].cbd_datlen = 0; /* Reset */ | |
283 | rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0]; | |
fe8c2806 WD |
284 | } |
285 | ||
286 | rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; | |
287 | ||
288 | /* 24.21 - (21): Write 0xffff to SCCE */ | |
289 | immr->im_scc[CONFIG_ETHER_INDEX-1].scc_scce = ~(0x0); | |
290 | ||
291 | /* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */ | |
292 | immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE | | |
8bde7f77 WD |
293 | SCCE_ENET_RXF | |
294 | SCCE_ENET_TXB); | |
fe8c2806 WD |
295 | |
296 | /* 24.21 - (23): we don't use ethernet interrupts */ | |
297 | ||
298 | /* 24.21 - (24): Clear GSMR_H to enable normal operations */ | |
299 | immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrh = 0; | |
300 | ||
301 | /* 24.21 - (25): Clear GSMR_L to enable normal operations */ | |
302 | immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI | | |
8bde7f77 WD |
303 | SCC_GSMRL_TPL_48 | |
304 | SCC_GSMRL_TPP_10 | | |
305 | SCC_GSMRL_MODE_ENET); | |
fe8c2806 WD |
306 | |
307 | /* 24.21 - (26): Initialize DSR */ | |
308 | immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555; | |
309 | ||
310 | /* 24.21 - (27): Initialize PSMR2 | |
311 | * | |
312 | * Settings: | |
313 | * CRC = 32-Bit CCITT | |
314 | * NIB = Begin searching for SFD 22 bits after RENA | |
315 | * FDE = Full Duplex Enable | |
316 | * BRO = Reject broadcast packets | |
317 | * PROMISCOUS = Catch all packets regardless of dest. MAC adress | |
318 | */ | |
319 | immr->im_scc[CONFIG_ETHER_INDEX-1].scc_psmr = SCC_PSMR_ENCRC | | |
320 | SCC_PSMR_NIB22 | | |
321 | #if defined(CONFIG_SCC_ENET_FULL_DUPLEX) | |
322 | SCC_PSMR_FDE | | |
323 | #endif | |
324 | #if defined(CONFIG_SCC_ENET_NO_BROADCAST) | |
325 | SCC_PSMR_BRO | | |
326 | #endif | |
327 | #if defined(CONFIG_SCC_ENET_PROMISCOUS) | |
328 | SCC_PSMR_PRO | | |
329 | #endif | |
330 | 0; | |
331 | ||
332 | /* 24.21 - (28): Write to GSMR_L to enable SCC */ | |
333 | immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR | | |
8bde7f77 | 334 | SCC_GSMRL_ENT); |
fe8c2806 | 335 | |
48b42616 | 336 | return 0; |
fe8c2806 WD |
337 | } |
338 | ||
339 | ||
fe8c2806 WD |
340 | void eth_halt(void) |
341 | { | |
342 | volatile immap_t *immr = (immap_t *)CFG_IMMR; | |
343 | immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR | | |
8bde7f77 | 344 | SCC_GSMRL_ENT); |
fe8c2806 WD |
345 | } |
346 | ||
347 | #if 0 | |
348 | void restart(void) | |
349 | { | |
350 | volatile immap_t *immr = (immap_t *)CFG_IMMR; | |
351 | immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR | | |
8bde7f77 | 352 | SCC_GSMRL_ENT); |
fe8c2806 WD |
353 | } |
354 | #endif | |
355 | ||
356 | #endif /* CONFIG_ETHER_ON_SCC && CFG_CMD_NET */ |