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4d75a504 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | ||
26 | #ifdef CONFIG_PCI | |
27 | ||
28 | #include <pci.h> | |
5d232d0e | 29 | #include <mpc8260.h> |
4d75a504 WD |
30 | #include <asm/m8260_pci.h> |
31 | ||
32 | /* | |
33 | * Local->PCI map (from CPU) controlled by | |
34 | * MPC826x master window | |
35 | * | |
5d232d0e WD |
36 | * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0 |
37 | * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1 | |
4d75a504 | 38 | * |
5d232d0e WD |
39 | * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1) |
40 | * PCI Mem with prefetch | |
41 | * | |
42 | * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2) | |
43 | * PCI Mem w/o prefetch | |
44 | * | |
45 | * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3) | |
46 | * 32-bit PCI IO | |
4d75a504 WD |
47 | * |
48 | * PCI->Local map (from PCI) | |
49 | * MPC826x slave window controlled by | |
50 | * | |
5d232d0e WD |
51 | * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1) |
52 | * MPC826x local memory | |
4d75a504 WD |
53 | */ |
54 | ||
55 | /* | |
56 | * Slave window that allows PCI masters to access MPC826x local memory. | |
57 | * This window is set up using the first set of Inbound ATU registers | |
58 | */ | |
59 | ||
5d232d0e WD |
60 | #ifndef CFG_PCI_SLV_MEM_LOCAL |
61 | #define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ | |
62 | #else | |
63 | #define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL | |
64 | #endif | |
65 | ||
66 | #ifndef CFG_PCI_SLV_MEM_BUS | |
67 | #define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ | |
68 | #else | |
69 | #define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS | |
70 | #endif | |
71 | ||
72 | #ifndef CFG_PICMR0_MASK_ATTRIB | |
4d75a504 WD |
73 | #define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ |
74 | PICMR_PREFETCH_EN) | |
5d232d0e WD |
75 | #else |
76 | #define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB | |
77 | #endif | |
4d75a504 WD |
78 | |
79 | /* | |
5d232d0e WD |
80 | * These are the windows that allow the CPU to access PCI address space. |
81 | * All three PCI master windows, which allow the CPU to access PCI | |
82 | * prefetch, non prefetch, and IO space (see below), must all fit within | |
83 | * these windows. | |
4d75a504 WD |
84 | */ |
85 | ||
5d232d0e WD |
86 | /* PCIBR0 */ |
87 | #ifndef CFG_PCI_MSTR0_LOCAL | |
88 | #define PCI_MSTR0_LOCAL 0x80000000 /* Local base */ | |
89 | #else | |
90 | #define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL | |
91 | #endif | |
92 | ||
93 | #ifndef CFG_PCIMSK0_MASK | |
4d75a504 | 94 | #define PCIMSK0_MASK PCIMSK_1GB /* Size of window */ |
5d232d0e WD |
95 | #else |
96 | #define PCIMSK0_MASK CFG_PCIMSK0_MASK | |
97 | #endif | |
98 | ||
99 | /* PCIBR1 */ | |
100 | #ifndef CFG_PCI_MSTR1_LOCAL | |
101 | #define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ | |
102 | #else | |
103 | #define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL | |
104 | #endif | |
105 | ||
106 | #ifndef CFG_PCIMSK1_MASK | |
107 | #define PCIMSK1_MASK PCIMSK_64MB /* Size of window */ | |
108 | #else | |
109 | #define PCIMSK1_MASK CFG_PCIMSK1_MASK | |
110 | #endif | |
4d75a504 WD |
111 | |
112 | /* | |
113 | * Master window that allows the CPU to access PCI Memory (prefetch). | |
114 | * This window will be setup with the first set of Outbound ATU registers | |
115 | * in the bridge. | |
116 | */ | |
117 | ||
5d232d0e WD |
118 | #ifndef CFG_PCI_MSTR_MEM_LOCAL |
119 | #define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ | |
120 | #else | |
121 | #define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL | |
122 | #endif | |
123 | ||
124 | #ifndef CFG_PCI_MSTR_MEM_BUS | |
125 | #define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ | |
126 | #else | |
127 | #define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS | |
128 | #endif | |
129 | ||
130 | #ifndef CFG_CPU_PCI_MEM_START | |
131 | #define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL | |
132 | #else | |
133 | #define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START | |
134 | #endif | |
135 | ||
136 | #ifndef CFG_PCI_MSTR_MEM_SIZE | |
137 | #define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */ | |
138 | #else | |
139 | #define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE | |
140 | #endif | |
141 | ||
142 | #ifndef CFG_POCMR0_MASK_ATTRIB | |
4d75a504 | 143 | #define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN) |
5d232d0e WD |
144 | #else |
145 | #define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB | |
146 | #endif | |
4d75a504 WD |
147 | |
148 | /* | |
149 | * Master window that allows the CPU to access PCI Memory (non-prefetch). | |
150 | * This window will be setup with the second set of Outbound ATU registers | |
151 | * in the bridge. | |
152 | */ | |
153 | ||
5d232d0e WD |
154 | #ifndef CFG_PCI_MSTR_MEMIO_LOCAL |
155 | #define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */ | |
156 | #else | |
157 | #define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL | |
158 | #endif | |
159 | ||
160 | #ifndef CFG_PCI_MSTR_MEMIO_BUS | |
161 | #define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */ | |
162 | #else | |
163 | #define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS | |
164 | #endif | |
165 | ||
166 | #ifndef CFG_CPU_PCI_MEMIO_START | |
167 | #define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL | |
168 | #else | |
169 | #define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START | |
170 | #endif | |
171 | ||
172 | #ifndef CFG_PCI_MSTR_MEMIO_SIZE | |
682011ff | 173 | #define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */ |
5d232d0e WD |
174 | #else |
175 | #define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE | |
176 | #endif | |
177 | ||
178 | #ifndef CFG_POCMR1_MASK_ATTRIB | |
179 | #define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) | |
180 | #else | |
181 | #define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB | |
182 | #endif | |
4d75a504 WD |
183 | |
184 | /* | |
185 | * Master window that allows the CPU to access PCI IO space. | |
186 | * This window will be setup with the third set of Outbound ATU registers | |
187 | * in the bridge. | |
188 | */ | |
189 | ||
5d232d0e WD |
190 | #ifndef CFG_PCI_MSTR_IO_LOCAL |
191 | #define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */ | |
192 | #else | |
193 | #define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL | |
194 | #endif | |
195 | ||
196 | #ifndef CFG_PCI_MSTR_IO_BUS | |
197 | #define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */ | |
198 | #else | |
199 | #define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS | |
200 | #endif | |
201 | ||
202 | #ifndef CFG_CPU_PCI_IO_START | |
203 | #define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL | |
204 | #else | |
205 | #define CPU_PCI_IO_START CFG_CPU_PCI_IO_START | |
206 | #endif | |
207 | ||
208 | #ifndef CFG_PCI_MSTR_IO_SIZE | |
209 | #define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */ | |
210 | #else | |
211 | #define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE | |
66fd3d1c | 212 | #endif |
5d232d0e WD |
213 | |
214 | #ifndef CFG_POCMR2_MASK_ATTRIB | |
4d75a504 | 215 | #define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO) |
5d232d0e WD |
216 | #else |
217 | #define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB | |
218 | #endif | |
4d75a504 WD |
219 | |
220 | /* PCI bus configuration registers. | |
221 | */ | |
222 | ||
223 | #define PCI_CLASS_BRIDGE_CTLR 0x06 | |
224 | ||
225 | ||
226 | static inline void pci_outl(u32 addr, u32 data) | |
227 | { | |
228 | *(volatile u32 *) addr = cpu_to_le32(data); | |
229 | } | |
230 | ||
231 | void pci_mpc8250_init(struct pci_controller *hose) | |
232 | { | |
5d232d0e WD |
233 | #ifdef CONFIG_MPC8266ADS |
234 | DECLARE_GLOBAL_DATA_PTR; | |
235 | #endif | |
4d75a504 WD |
236 | u16 tempShort; |
237 | u32 immr_addr = CFG_IMMR; | |
238 | volatile immap_t *immap = (immap_t *) CFG_IMMR; | |
239 | pci_dev_t host_devno = PCI_BDF(0, 0, 0); | |
240 | ||
241 | pci_setup_indirect(hose, CFG_IMMR + PCI_CFG_ADDR_REG, | |
242 | CFG_IMMR + PCI_CFG_DATA_REG); | |
243 | ||
5d232d0e WD |
244 | /* |
245 | * Setting required to enable local bus for PCI (SIUMCR [LBPC]). | |
246 | */ | |
247 | #ifdef CONFIG_MPC8266ADS | |
248 | immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) | |
249 | | SIUMCR_LBPC01; | |
250 | #else | |
4d75a504 WD |
251 | /* |
252 | * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), | |
253 | * and local bus for PCI (SIUMCR [LBPC]). | |
254 | */ | |
255 | immap->im_siu_conf.sc_siumcr = 0x00640000; | |
5d232d0e | 256 | #endif |
4d75a504 WD |
257 | |
258 | /* Make PCI lowest priority */ | |
259 | /* Each 4 bits is a device bus request and the MS 4bits | |
260 | is highest priority */ | |
261 | /* Bus 4bit value | |
262 | --- ---------- | |
263 | CPM high 0b0000 | |
264 | CPM middle 0b0001 | |
265 | CPM low 0b0010 | |
266 | PCI reguest 0b0011 | |
267 | Reserved 0b0100 | |
268 | Reserved 0b0101 | |
269 | Internal Core 0b0110 | |
270 | External Master 1 0b0111 | |
271 | External Master 2 0b1000 | |
272 | External Master 3 0b1001 | |
273 | The rest are reserved */ | |
274 | immap->im_siu_conf.sc_ppc_alrh = 0x61207893; | |
275 | ||
276 | /* Park bus on core while modifying PCI Bus accesses */ | |
277 | immap->im_siu_conf.sc_ppc_acr = 0x6; | |
278 | ||
279 | /* | |
5d232d0e WD |
280 | * Set up master windows that allow the CPU to access PCI space. These |
281 | * windows are set up using the two SIU PCIBR registers. | |
4d75a504 WD |
282 | */ |
283 | *(volatile unsigned long*)(immr_addr + M8265_PCIMSK0) = PCIMSK0_MASK; | |
284 | *(volatile unsigned long*)(immr_addr + M8265_PCIBR0) = | |
5d232d0e WD |
285 | PCI_MSTR0_LOCAL | PCIBR_ENABLE; |
286 | ||
287 | #ifdef CONFIG_MPC8266ADS | |
288 | *(volatile unsigned long*)(immr_addr + M8265_PCIMSK1) = PCIMSK1_MASK; | |
289 | *(volatile unsigned long*)(immr_addr + M8265_PCIBR1) = | |
290 | PCI_MSTR1_LOCAL | PCIBR_ENABLE; | |
291 | #endif | |
4d75a504 WD |
292 | |
293 | /* Release PCI RST (by default the PCI RST signal is held low) */ | |
294 | pci_outl (immr_addr | PCI_GCR_REG, PCIGCR_PCI_BUS_EN); | |
295 | ||
296 | /* give it some time */ | |
5d232d0e WD |
297 | { |
298 | #ifdef CONFIG_MPC8266ADS | |
299 | /* Give the PCI cards more time to initialize before query | |
300 | This might be good for other boards also | |
301 | */ | |
302 | int i; | |
303 | for (i = 0; i < 1000; ++i) | |
304 | #endif | |
305 | udelay(1000); | |
306 | } | |
4d75a504 WD |
307 | |
308 | /* | |
309 | * Set up master window that allows the CPU to access PCI Memory (prefetch) | |
310 | * space. This window is set up using the first set of Outbound ATU registers. | |
311 | */ | |
312 | pci_outl (immr_addr | POTAR_REG0, PCI_MSTR_MEM_BUS >> 12); /* PCI base */ | |
313 | pci_outl (immr_addr | POBAR_REG0, PCI_MSTR_MEM_LOCAL >> 12); /* Local base */ | |
314 | pci_outl (immr_addr | POCMR_REG0, POCMR0_MASK_ATTRIB); /* Size & attribute */ | |
315 | ||
316 | /* | |
317 | * Set up master window that allows the CPU to access PCI Memory (non-prefetch) | |
318 | * space. This window is set up using the second set of Outbound ATU registers. | |
319 | */ | |
320 | pci_outl (immr_addr | POTAR_REG1, PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */ | |
321 | pci_outl (immr_addr | POBAR_REG1, PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */ | |
322 | pci_outl (immr_addr | POCMR_REG1, POCMR1_MASK_ATTRIB); /* Size & attribute */ | |
323 | ||
324 | /* | |
325 | * Set up master window that allows the CPU to access PCI IO space. This window | |
326 | * is set up using the third set of Outbound ATU registers. | |
327 | */ | |
328 | pci_outl (immr_addr | POTAR_REG2, PCI_MSTR_IO_BUS >> 12); /* PCI base */ | |
329 | pci_outl (immr_addr | POBAR_REG2, PCI_MSTR_IO_LOCAL >> 12); /* Local base */ | |
330 | pci_outl (immr_addr | POCMR_REG2, POCMR2_MASK_ATTRIB); /* Size & attribute */ | |
331 | ||
332 | /* | |
333 | * Set up slave window that allows PCI masters to access MPC826x local memory. | |
334 | * This window is set up using the first set of Inbound ATU registers | |
335 | */ | |
336 | pci_outl (immr_addr | PITAR_REG0, PCI_SLV_MEM_LOCAL >> 12); /* Local base */ | |
337 | pci_outl (immr_addr | PIBAR_REG0, PCI_SLV_MEM_BUS >> 12); /* PCI base */ | |
338 | pci_outl (immr_addr | PICMR_REG0, PICMR0_MASK_ATTRIB); /* Size & attribute */ | |
339 | ||
340 | /* See above for description - puts PCI request as highest priority */ | |
341 | immap->im_siu_conf.sc_ppc_alrh = 0x03124567; | |
342 | ||
343 | /* Park the bus on the PCI */ | |
344 | immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI; | |
345 | ||
346 | /* Host mode - specify the bridge as a host-PCI bridge */ | |
347 | ||
348 | pci_hose_write_config_byte(hose, host_devno, PCI_CLASS_CODE, | |
349 | PCI_CLASS_BRIDGE_CTLR); | |
350 | ||
351 | /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */ | |
352 | pci_hose_read_config_word(hose, host_devno, PCI_COMMAND, &tempShort); | |
353 | pci_hose_write_config_word(hose, host_devno, PCI_COMMAND, | |
354 | tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); | |
355 | ||
7a8e9bed WD |
356 | #ifdef CONFIG_MPC8266ADS |
357 | /* do some bridge init, should be done on all 8260 based bridges */ | |
358 | pci_hose_write_config_byte(hose, host_devno, PCI_CACHE_LINE_SIZE, 0x08); | |
359 | pci_hose_write_config_byte(hose, host_devno, PCI_LATENCY_TIMER, 0xF8); | |
360 | #endif | |
361 | ||
4d75a504 WD |
362 | hose->first_busno = 0; |
363 | hose->last_busno = 0xff; | |
364 | ||
365 | /* System memory space */ | |
5d232d0e WD |
366 | #ifdef CONFIG_MPC8266ADS |
367 | pci_set_region(hose->regions + 0, | |
368 | PCI_SLV_MEM_BUS, | |
369 | PCI_SLV_MEM_LOCAL, | |
370 | gd->ram_size, | |
371 | PCI_REGION_MEM | PCI_REGION_MEMORY); | |
372 | #else | |
4d75a504 WD |
373 | pci_set_region(hose->regions + 0, |
374 | CFG_SDRAM_BASE, | |
375 | CFG_SDRAM_BASE, | |
376 | 0x4000000, | |
377 | PCI_REGION_MEM | PCI_REGION_MEMORY); | |
5d232d0e | 378 | #endif |
4d75a504 WD |
379 | |
380 | /* PCI memory space */ | |
5d232d0e | 381 | #ifdef CONFIG_MPC8266ADS |
7a8e9bed WD |
382 | pci_set_region(hose->regions + 1, |
383 | PCI_MSTR_MEMIO_BUS, | |
384 | PCI_MSTR_MEMIO_LOCAL, | |
385 | PCI_MSTR_MEMIO_SIZE, | |
386 | PCI_REGION_MEM); | |
5d232d0e | 387 | #else |
4d75a504 WD |
388 | pci_set_region(hose->regions + 1, |
389 | PCI_MSTR_MEM_BUS, | |
390 | PCI_MSTR_MEM_LOCAL, | |
391 | PCI_MSTR_MEM_SIZE, | |
392 | PCI_REGION_MEM); | |
5d232d0e | 393 | #endif |
4d75a504 WD |
394 | |
395 | /* PCI I/O space */ | |
396 | pci_set_region(hose->regions + 2, | |
397 | PCI_MSTR_IO_BUS, | |
398 | PCI_MSTR_IO_LOCAL, | |
399 | PCI_MSTR_IO_SIZE, | |
400 | PCI_REGION_IO); | |
401 | ||
402 | hose->region_count = 3; | |
403 | ||
404 | pci_register_hose(hose); | |
405 | ||
406 | hose->last_busno = pci_hose_scan(hose); | |
407 | } | |
408 | ||
409 | #endif /* CONFIG_PCI */ |