[people/ms/u-boot.git] / cpu / mpc8260 / pci.c

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Copyright (c) 2005 MontaVista Software, Inc.
 * Vitaly Bordug <vbordug@ru.mvista.com>
 * Added support for PCI bridge on MPC8272ADS
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

#ifdef CONFIG_PCI

#include <pci.h>
#include <mpc8260.h>
#include <asm/m8260_pci.h>
#include <asm/io.h>

#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
DECLARE_GLOBAL_DATA_PTR;
#endif

/*
 *   Local->PCI map (from CPU)				   controlled by
 *   MPC826x master window
 *
 *   0x80000000 - 0xBFFFFFFF	CPU2PCI space		   PCIBR0
 *   0xF4000000 - 0xF7FFFFFF	CPU2PCI space		   PCIBR1
 *
 *   0x80000000 - 0x9FFFFFFF	0x80000000 - 0x9FFFFFFF	  (Outbound ATU #1)
 *				PCI Mem with prefetch
 *
 *   0xA0000000 - 0xBFFFFFFF	0xA0000000 - 0xBFFFFFFF	  (Outbound ATU #2)
 *				PCI Mem w/o  prefetch
 *
 *   0xF4000000 - 0xF7FFFFFF	0x00000000 - 0x03FFFFFF	  (Outbound ATU #3)
 *				32-bit PCI IO
 *
 *   PCI->Local map (from PCI)
 *   MPC826x slave window				   controlled by
 *
 *   0x00000000 - 0x1FFFFFFF	0x00000000 - 0x1FFFFFFF	  (Inbound ATU #1)
 *				MPC826x local memory
 */

/*
 * Slave window that allows PCI masters to access MPC826x local memory.
 * This window is set up using the first set of Inbound ATU registers
 */

#ifndef CFG_PCI_SLV_MEM_LOCAL
#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE	/* Local base */
#else
#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
#endif

#ifndef CFG_PCI_SLV_MEM_BUS
#define PCI_SLV_MEM_BUS 0x00000000	/* PCI base */
#else
#define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS
#endif

#ifndef CFG_PICMR0_MASK_ATTRIB
#define PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
				 PICMR_PREFETCH_EN)
#else
#define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB
#endif

/*
 * These are the windows that allow the CPU to access PCI address space.
 * All three PCI master windows, which allow the CPU to access PCI
 * prefetch, non prefetch, and IO space (see below), must all fit within
 * these windows.
 */

/* PCIBR0 */
#ifndef CFG_PCI_MSTR0_LOCAL
#define PCI_MSTR0_LOCAL		0x80000000	/* Local base */
#else
#define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
#endif

#ifndef CFG_PCIMSK0_MASK
#define PCIMSK0_MASK		PCIMSK_1GB	/* Size of window */
#else
#define PCIMSK0_MASK	CFG_PCIMSK0_MASK
#endif

/* PCIBR1 */
#ifndef CFG_PCI_MSTR1_LOCAL
#define PCI_MSTR1_LOCAL		0xF4000000	/* Local base */
#else
#define PCI_MSTR1_LOCAL		CFG_PCI_MSTR1_LOCAL
#endif

#ifndef CFG_PCIMSK1_MASK
#define	 PCIMSK1_MASK		PCIMSK_64MB	/* Size of window */
#else
#define	 PCIMSK1_MASK		CFG_PCIMSK1_MASK
#endif

/*
 * Master window that allows the CPU to access PCI Memory (prefetch).
 * This window will be setup with the first set of Outbound ATU registers
 * in the bridge.
 */

#ifndef CFG_PCI_MSTR_MEM_LOCAL
#define PCI_MSTR_MEM_LOCAL 0x80000000	/* Local base */
#else
#define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL
#endif

#ifndef CFG_PCI_MSTR_MEM_BUS
#define PCI_MSTR_MEM_BUS 0x80000000	/* PCI base   */
#else
#define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS
#endif

#ifndef CFG_CPU_PCI_MEM_START
#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
#else
#define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START
#endif

#ifndef CFG_PCI_MSTR_MEM_SIZE
#define PCI_MSTR_MEM_SIZE 0x10000000	/* 256MB */
#else
#define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE
#endif

#ifndef CFG_POCMR0_MASK_ATTRIB
#define POCMR0_MASK_ATTRIB	(POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
#else
#define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB
#endif

/*
 * Master window that allows the CPU to access PCI Memory (non-prefetch).
 * This window will be setup with the second set of Outbound ATU registers
 * in the bridge.
 */

#ifndef CFG_PCI_MSTR_MEMIO_LOCAL
#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
#else
#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
#endif

#ifndef CFG_PCI_MSTR_MEMIO_BUS
#define PCI_MSTR_MEMIO_BUS 0x90000000	/* PCI base   */
#else
#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
#endif

#ifndef CFG_CPU_PCI_MEMIO_START
#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
#else
#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START
#endif

#ifndef CFG_PCI_MSTR_MEMIO_SIZE
#define PCI_MSTR_MEMIO_SIZE 0x10000000	/* 256 MB */
#else
#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
#endif

#ifndef CFG_POCMR1_MASK_ATTRIB
#define POCMR1_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE)
#else
#define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
#endif

/*
 * Master window that allows the CPU to access PCI IO space.
 * This window will be setup with the third set of Outbound ATU registers
 * in the bridge.
 */

#ifndef CFG_PCI_MSTR_IO_LOCAL
#define PCI_MSTR_IO_LOCAL 0xA0000000	/* Local base */
#else
#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
#endif

#ifndef CFG_PCI_MSTR_IO_BUS
#define PCI_MSTR_IO_BUS 0xA0000000	/* PCI base   */
#else
#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
#endif

#ifndef CFG_CPU_PCI_IO_START
#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
#else
#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START
#endif

#ifndef CFG_PCI_MSTR_IO_SIZE
#define PCI_MSTR_IO_SIZE 0x10000000	/* 256MB */
#else
#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
#endif

#ifndef CFG_POCMR2_MASK_ATTRIB
#define POCMR2_MASK_ATTRIB	(POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
#else
#define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB
#endif

/* PCI bus configuration registers.
 */

#define PCI_CLASS_BRIDGE_CTLR	0x06


static inline void pci_outl (u32 addr, u32 data)
{
	*(volatile u32 *) addr = cpu_to_le32 (data);
}

void pci_mpc8250_init (struct pci_controller *hose)
{
	u16 tempShort;

	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	pci_dev_t host_devno = PCI_BDF (0, 0, 0);

	pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG,
			    CFG_IMMR + PCI_CFG_DATA_REG);

	/*
	 * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
	 */
#ifdef CONFIG_MPC8266ADS
	immap->im_siu_conf.sc_siumcr =
		(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
		| SIUMCR_LBPC01;
#elif defined CONFIG_MPC8272
	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
				  ~SIUMCR_BBD &
				  ~SIUMCR_ESE &
				  ~SIUMCR_PBSE &
				  ~SIUMCR_CDIS &
				  ~SIUMCR_DPPC11 &
				  ~SIUMCR_L2CPC11 &
				  ~SIUMCR_LBPC11 &
				  ~SIUMCR_APPC11 &
				  ~SIUMCR_CS10PC11 &
				  ~SIUMCR_BCTLC11 &
				  ~SIUMCR_MMR11)
				  | SIUMCR_DPPC11
				  | SIUMCR_L2CPC01
				  | SIUMCR_LBPC00
				  | SIUMCR_APPC10
				  | SIUMCR_CS10PC00
				  | SIUMCR_BCTLC00
				  | SIUMCR_MMR11;

#else
	/*
	 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
	 * and local bus for PCI (SIUMCR [LBPC]).
	 */
	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
						~SIUMCR_LBPC11 &
						~SIUMCR_CS10PC11 &
						~SIUMCR_LBPC11) |
					SIUMCR_LBPC01 |
					SIUMCR_CS10PC01 |
					SIUMCR_APPC10;
#endif

	/* Make PCI lowest priority */
	/* Each 4 bits is a device bus request	and the MS 4bits
	   is highest priority */
	/* Bus		     4bit value
	   ---		     ----------
	   CPM high	     0b0000
	   CPM middle	     0b0001
	   CPM low	     0b0010
	   PCI reguest	     0b0011
	   Reserved	     0b0100
	   Reserved	     0b0101
	   Internal Core     0b0110
	   External Master 1 0b0111
	   External Master 2 0b1000
	   External Master 3 0b1001
	   The rest are reserved */
	immap->im_siu_conf.sc_ppc_alrh = 0x61207893;

	/* Park bus on core while modifying PCI Bus accesses */
	immap->im_siu_conf.sc_ppc_acr = 0x6;

	/*
	 * Set up master windows that allow the CPU to access PCI space. These
	 * windows are set up using the two SIU PCIBR registers.
	 */
	immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
	immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;

#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
	immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
	immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
#endif

	/* Release PCI RST (by default the PCI RST signal is held low)	*/
	immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);

	/* give it some time */
	{
#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
		/* Give the PCI cards more time to initialize before query
		   This might be good for other boards also
		 */
		int i;

		for (i = 0; i < 1000; ++i)
#endif
			udelay (1000);
	}

	/*
	 * Set up master window that allows the CPU to access PCI Memory (prefetch)
	 * space. This window is set up using the first set of Outbound ATU registers.
	 */
	immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12);	/* PCI base */
	immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12);	/* Local base */
	immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB);	/* Size & attribute */

	/*
	 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
	 * space. This window is set up using the second set of Outbound ATU registers.
	 */
	immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12);	/* PCI base */
	immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12);	/* Local base */
	immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB);	/* Size & attribute */

	/*
	 * Set up master window that allows the CPU to access PCI IO space. This window
	 * is set up using the third set of Outbound ATU registers.
	 */
	immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
	immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12);	/* Local base */
	immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB);	/* Size & attribute */

	/*
	 * Set up slave window that allows PCI masters to access MPC826x local memory.
	 * This window is set up using the first set of Inbound ATU registers
	 */
	immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12);	/* PCI base */
	immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
	immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB);	/* Size & attribute */

	/* See above for description - puts PCI request as highest priority */
#ifdef CONFIG_MPC8272
	immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
#else
	immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
#endif

	/* Park the bus on the PCI */
	immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;

	/* Host mode - specify the bridge as a host-PCI bridge */

	pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
				    PCI_CLASS_BRIDGE_CTLR);

	/* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
	pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
	pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
				    tempShort | PCI_COMMAND_MASTER |
				    PCI_COMMAND_MEMORY);

	/* do some bridge init, should be done on all 8260 based bridges */
	pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
				    0x08);
	pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
				    0xF8);

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	/* System memory space */
#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
	pci_set_region (hose->regions + 0,
			PCI_SLV_MEM_BUS,
			PCI_SLV_MEM_LOCAL,
			gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
#else
	pci_set_region (hose->regions + 0,
			CFG_SDRAM_BASE,
			CFG_SDRAM_BASE,
			0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
#endif

	/* PCI memory space */
#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
	pci_set_region (hose->regions + 1,
			PCI_MSTR_MEMIO_BUS,
			PCI_MSTR_MEMIO_LOCAL,
			PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
#else
	pci_set_region (hose->regions + 1,
			PCI_MSTR_MEM_BUS,
			PCI_MSTR_MEM_LOCAL,
			PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
#endif

	/* PCI I/O space */
	pci_set_region (hose->regions + 2,
			PCI_MSTR_IO_BUS,
			PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);

	hose->region_count = 3;

	pci_register_hose (hose);
	/* Mask off master abort machine checks */
	immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
	eieio ();

	hose->last_busno = pci_hose_scan (hose);


	/* clear the error in the error status register */
	immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);

	/* unmask master abort machine checks */
	immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
}

#endif /* CONFIG_PCI */
Commit	Line	Data
4d75a504 WD	1	/*
	2	* (C) Copyright 2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
716c1dcb	5	* Copyright (c) 2005 MontaVista Software, Inc.
1972dc0a WD	6	* Vitaly Bordug <vbordug@ru.mvista.com>
	7	* Added support for PCI bridge on MPC8272ADS
	8	*
4d75a504 WD	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <common.h>
	29
	30	#ifdef CONFIG_PCI
	31
	32	#include <pci.h>
5d232d0e	33	#include <mpc8260.h>
4d75a504	34	#include <asm/m8260_pci.h>
3c74e32a	35	#include <asm/io.h>
d87080b7	36
392c252e	37	#if defined CONFIG_MPC8266ADS \|\| defined CONFIG_MPC8272 \|\| defined CONFIG_PM826
d87080b7 WD	38	DECLARE_GLOBAL_DATA_PTR;
	39	#endif
	40
4d75a504	41	/*
3c74e32a	42	* Local->PCI map (from CPU) controlled by
4d75a504 WD	43	* MPC826x master window
4d75a504 WD	44	*
3c74e32a WD	45	* 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
3c74e32a WD	46	* 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
8bde7f77	47	*
3c74e32a WD	48	* 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
3c74e32a WD	49	* PCI Mem with prefetch
5d232d0e	50	*
3c74e32a WD	51	* 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2)
3c74e32a WD	52	* PCI Mem w/o prefetch
5d232d0e	53	*
3c74e32a WD	54	* 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
3c74e32a WD	55	* 32-bit PCI IO
8bde7f77	56	*
4d75a504	57	* PCI->Local map (from PCI)
3c74e32a	58	* MPC826x slave window controlled by
4d75a504	59	*
3c74e32a WD	60	* 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1)
3c74e32a WD	61	* MPC826x local memory
4d75a504 WD	62	*/
4d75a504 WD	63
8bde7f77 WD	64	/*
8bde7f77 WD	65	* Slave window that allows PCI masters to access MPC826x local memory.
4d75a504 WD	66	* This window is set up using the first set of Inbound ATU registers
	67	*/
	68
8bde7f77	69	#ifndef CFG_PCI_SLV_MEM_LOCAL
3c74e32a	70	#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
8bde7f77 WD	71	#else
8bde7f77 WD	72	#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
5d232d0e WD	73	#endif
	74
	75	#ifndef CFG_PCI_SLV_MEM_BUS
3c74e32a	76	#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
5d232d0e WD	77	#else
	78	#define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS
	79	#endif
	80
	81	#ifndef CFG_PICMR0_MASK_ATTRIB
4d75a504	82	#define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB \| PICMR_ENABLE \| \
8bde7f77	83	PICMR_PREFETCH_EN)
5d232d0e WD	84	#else
	85	#define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB
	86	#endif
4d75a504	87
8bde7f77	88	/*
5d232d0e	89	* These are the windows that allow the CPU to access PCI address space.
8bde7f77 WD	90	* All three PCI master windows, which allow the CPU to access PCI
8bde7f77 WD	91	* prefetch, non prefetch, and IO space (see below), must all fit within
5d232d0e	92	* these windows.
4d75a504 WD	93	*/
4d75a504 WD	94
5d232d0e WD	95	/* PCIBR0 */
5d232d0e WD	96	#ifndef CFG_PCI_MSTR0_LOCAL
3c74e32a	97	#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
8bde7f77	98	#else
5d232d0e WD	99	#define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
	100	#endif
	101
	102	#ifndef CFG_PCIMSK0_MASK
3c74e32a	103	#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
5d232d0e WD	104	#else
	105	#define PCIMSK0_MASK CFG_PCIMSK0_MASK
	106	#endif
	107
	108	/* PCIBR1 */
	109	#ifndef CFG_PCI_MSTR1_LOCAL
3c74e32a	110	#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
8bde7f77 WD	111	#else
8bde7f77 WD	112	#define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL
5d232d0e WD	113	#endif
	114
	115	#ifndef CFG_PCIMSK1_MASK
3c74e32a	116	#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
5d232d0e	117	#else
3c74e32a	118	#define PCIMSK1_MASK CFG_PCIMSK1_MASK
5d232d0e	119	#endif
4d75a504	120
8bde7f77	121	/*
4d75a504 WD	122	* Master window that allows the CPU to access PCI Memory (prefetch).
	123	* This window will be setup with the first set of Outbound ATU registers
	124	* in the bridge.
	125	*/
	126
5d232d0e	127	#ifndef CFG_PCI_MSTR_MEM_LOCAL
3c74e32a	128	#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
5d232d0e WD	129	#else
	130	#define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL
	131	#endif
	132
	133	#ifndef CFG_PCI_MSTR_MEM_BUS
3c74e32a	134	#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
5d232d0e WD	135	#else
	136	#define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS
	137	#endif
	138
	139	#ifndef CFG_CPU_PCI_MEM_START
	140	#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
	141	#else
	142	#define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START
	143	#endif
	144
	145	#ifndef CFG_PCI_MSTR_MEM_SIZE
3c74e32a	146	#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
5d232d0e WD	147	#else
	148	#define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE
	149	#endif
	150
	151	#ifndef CFG_POCMR0_MASK_ATTRIB
4d75a504	152	#define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB \| POCMR_ENABLE \| POCMR_PREFETCH_EN)
5d232d0e WD	153	#else
	154	#define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB
	155	#endif
4d75a504	156
8bde7f77	157	/*
4d75a504 WD	158	* Master window that allows the CPU to access PCI Memory (non-prefetch).
	159	* This window will be setup with the second set of Outbound ATU registers
	160	* in the bridge.
	161	*/
	162
8bde7f77	163	#ifndef CFG_PCI_MSTR_MEMIO_LOCAL
3c74e32a	164	#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
8bde7f77 WD	165	#else
8bde7f77 WD	166	#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
5d232d0e WD	167	#endif
5d232d0e WD	168
8bde7f77	169	#ifndef CFG_PCI_MSTR_MEMIO_BUS
3c74e32a	170	#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
8bde7f77 WD	171	#else
8bde7f77 WD	172	#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
5d232d0e WD	173	#endif
5d232d0e WD	174
8bde7f77 WD	175	#ifndef CFG_CPU_PCI_MEMIO_START
	176	#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
	177	#else
	178	#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START
5d232d0e WD	179	#endif
5d232d0e WD	180
8bde7f77	181	#ifndef CFG_PCI_MSTR_MEMIO_SIZE
3c74e32a	182	#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
8bde7f77 WD	183	#else
8bde7f77 WD	184	#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
5d232d0e WD	185	#endif
	186
	187	#ifndef CFG_POCMR1_MASK_ATTRIB
3c74e32a	188	#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB \| POCMR_ENABLE)
5d232d0e WD	189	#else
	190	#define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
	191	#endif
4d75a504	192
8bde7f77	193	/*
4d75a504 WD	194	* Master window that allows the CPU to access PCI IO space.
	195	* This window will be setup with the third set of Outbound ATU registers
	196	* in the bridge.
	197	*/
	198
8bde7f77	199	#ifndef CFG_PCI_MSTR_IO_LOCAL
3c74e32a	200	#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
8bde7f77 WD	201	#else
8bde7f77 WD	202	#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
5d232d0e WD	203	#endif
5d232d0e WD	204
8bde7f77	205	#ifndef CFG_PCI_MSTR_IO_BUS
3c74e32a	206	#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
8bde7f77 WD	207	#else
8bde7f77 WD	208	#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
5d232d0e WD	209	#endif
5d232d0e WD	210
8bde7f77 WD	211	#ifndef CFG_CPU_PCI_IO_START
	212	#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
	213	#else
	214	#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START
5d232d0e WD	215	#endif
5d232d0e WD	216
8bde7f77	217	#ifndef CFG_PCI_MSTR_IO_SIZE
3c74e32a	218	#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
8bde7f77 WD	219	#else
8bde7f77 WD	220	#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
66fd3d1c	221	#endif
5d232d0e WD	222
5d232d0e WD	223	#ifndef CFG_POCMR2_MASK_ATTRIB
3c74e32a	224	#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB \| POCMR_ENABLE \| POCMR_PCI_IO)
5d232d0e WD	225	#else
	226	#define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB
	227	#endif
4d75a504 WD	228
	229	/* PCI bus configuration registers.
	230	*/
	231
	232	#define PCI_CLASS_BRIDGE_CTLR 0x06
	233
	234
3c74e32a	235	static inline void pci_outl (u32 addr, u32 data)
4d75a504	236	{
3c74e32a	237	(volatile u32 ) addr = cpu_to_le32 (data);
4d75a504 WD	238	}
4d75a504 WD	239
3c74e32a	240	void pci_mpc8250_init (struct pci_controller *hose)
4d75a504	241	{
3c74e32a WD	242	u16 tempShort;
	243
	244	volatile immap_t immap = (immap_t ) CFG_IMMR;
	245	pci_dev_t host_devno = PCI_BDF (0, 0, 0);
4d75a504	246
3c74e32a WD	247	pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG,
3c74e32a WD	248	CFG_IMMR + PCI_CFG_DATA_REG);
4d75a504	249
3c74e32a WD	250	/*
	251	* Setting required to enable local bus for PCI (SIUMCR [LBPC]).
	252	*/
5d232d0e	253	#ifdef CONFIG_MPC8266ADS
3c74e32a WD	254	immap->im_siu_conf.sc_siumcr =
	255	(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
	256	\| SIUMCR_LBPC01;
1972dc0a	257	#elif defined CONFIG_MPC8272
716c1dcb WD	258	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
	259	~SIUMCR_BBD &
	260	~SIUMCR_ESE &
	261	~SIUMCR_PBSE &
	262	~SIUMCR_CDIS &
	263	~SIUMCR_DPPC11 &
	264	~SIUMCR_L2CPC11 &
	265	~SIUMCR_LBPC11 &
	266	~SIUMCR_APPC11 &
	267	~SIUMCR_CS10PC11 &
	268	~SIUMCR_BCTLC11 &
	269	~SIUMCR_MMR11)
	270	\| SIUMCR_DPPC11
	271	\| SIUMCR_L2CPC01
	272	\| SIUMCR_LBPC00
	273	\| SIUMCR_APPC10
	274	\| SIUMCR_CS10PC00
	275	\| SIUMCR_BCTLC00
	276	\| SIUMCR_MMR11;
1972dc0a	277
5d232d0e	278	#else
3c74e32a WD	279	/*
	280	* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
	281	* and local bus for PCI (SIUMCR [LBPC]).
	282	*/
	283	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
	284	~SIUMCR_LBPC11 &
8bde7f77	285	~SIUMCR_CS10PC11 &
3c74e32a WD	286	~SIUMCR_LBPC11) \|
	287	SIUMCR_LBPC01 \|
	288	SIUMCR_CS10PC01 \|
	289	SIUMCR_APPC10;
5d232d0e	290	#endif
4d75a504	291
3c74e32a WD	292	/* Make PCI lowest priority */
	293	/* Each 4 bits is a device bus request and the MS 4bits
	294	is highest priority */
	295	/* Bus 4bit value
	296	--- ----------
	297	CPM high 0b0000
	298	CPM middle 0b0001
	299	CPM low 0b0010
	300	PCI reguest 0b0011
	301	Reserved 0b0100
	302	Reserved 0b0101
	303	Internal Core 0b0110
	304	External Master 1 0b0111
	305	External Master 2 0b1000
	306	External Master 3 0b1001
	307	The rest are reserved */
	308	immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
	309
	310	/* Park bus on core while modifying PCI Bus accesses */
	311	immap->im_siu_conf.sc_ppc_acr = 0x6;
	312
	313	/*
	314	* Set up master windows that allow the CPU to access PCI space. These
	315	* windows are set up using the two SIU PCIBR registers.
	316	*/
	317	immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
	318	immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL \| PCIBR_ENABLE;
5d232d0e	319
1972dc0a	320	#if defined CONFIG_MPC8266ADS \|\| defined CONFIG_MPC8272
d4326aca WD	321	immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
d4326aca WD	322	immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL \| PCIBR_ENABLE;
8bde7f77	323	#endif
4d75a504	324
3c74e32a WD	325	/* Release PCI RST (by default the PCI RST signal is held low) */
3c74e32a WD	326	immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
4d75a504	327
3c74e32a WD	328	/* give it some time */
3c74e32a WD	329	{
1972dc0a	330	#if defined CONFIG_MPC8266ADS \|\| defined CONFIG_MPC8272
8bde7f77	331	/* Give the PCI cards more time to initialize before query
3c74e32a WD	332	This might be good for other boards also
	333	*/
	334	int i;
	335
	336	for (i = 0; i < 1000; ++i)
5d232d0e	337	#endif
3c74e32a WD	338	udelay (1000);
	339	}
	340
	341	/*
	342	* Set up master window that allows the CPU to access PCI Memory (prefetch)
	343	* space. This window is set up using the first set of Outbound ATU registers.
	344	*/
	345	immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */
	346	immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
	347	immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */
	348
	349	/*
	350	* Set up master window that allows the CPU to access PCI Memory (non-prefetch)
	351	* space. This window is set up using the second set of Outbound ATU registers.
	352	*/
	353	immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
	354	immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
	355	immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */
	356
	357	/*
	358	* Set up master window that allows the CPU to access PCI IO space. This window
	359	* is set up using the third set of Outbound ATU registers.
	360	*/
	361	immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
	362	immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */
	363	immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */
	364
	365	/*
	366	* Set up slave window that allows PCI masters to access MPC826x local memory.
	367	* This window is set up using the first set of Inbound ATU registers
	368	*/
	369	immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */
	370	immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
	371	immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */
	372
	373	/* See above for description - puts PCI request as highest priority */
1972dc0a WD	374	#ifdef CONFIG_MPC8272
	375	immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
	376	#else
3c74e32a	377	immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
1972dc0a	378	#endif
3c74e32a WD	379
	380	/* Park the bus on the PCI */
	381	immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
	382
	383	/* Host mode - specify the bridge as a host-PCI bridge */
	384
	385	pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
	386	PCI_CLASS_BRIDGE_CTLR);
	387
	388	/* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
	389	pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
	390	pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
	391	tempShort \| PCI_COMMAND_MASTER \|
	392	PCI_COMMAND_MEMORY);
4d75a504	393
7a8e9bed	394	/* do some bridge init, should be done on all 8260 based bridges */
3c74e32a WD	395	pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
	396	0x08);
	397	pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
	398	0xF8);
7a8e9bed	399
3c74e32a WD	400	hose->first_busno = 0;
3c74e32a WD	401	hose->last_busno = 0xff;
4d75a504	402
3c74e32a	403	/* System memory space */
392c252e	404	#if defined CONFIG_MPC8266ADS \|\| defined CONFIG_MPC8272 \|\| defined CONFIG_PM826
3c74e32a WD	405	pci_set_region (hose->regions + 0,
	406	PCI_SLV_MEM_BUS,
	407	PCI_SLV_MEM_LOCAL,
	408	gd->ram_size, PCI_REGION_MEM \| PCI_REGION_MEMORY);
5d232d0e	409	#else
3c74e32a WD	410	pci_set_region (hose->regions + 0,
	411	CFG_SDRAM_BASE,
	412	CFG_SDRAM_BASE,
	413	0x4000000, PCI_REGION_MEM \| PCI_REGION_MEMORY);
5d232d0e	414	#endif
4d75a504	415
3c74e32a	416	/* PCI memory space */
716c1dcb	417	#if defined CONFIG_MPC8266ADS \|\| defined CONFIG_MPC8272
3c74e32a WD	418	pci_set_region (hose->regions + 1,
	419	PCI_MSTR_MEMIO_BUS,
	420	PCI_MSTR_MEMIO_LOCAL,
	421	PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
5d232d0e	422	#else
3c74e32a WD	423	pci_set_region (hose->regions + 1,
	424	PCI_MSTR_MEM_BUS,
	425	PCI_MSTR_MEM_LOCAL,
	426	PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
5d232d0e	427	#endif
4d75a504	428
3c74e32a WD	429	/* PCI I/O space */
	430	pci_set_region (hose->regions + 2,
	431	PCI_MSTR_IO_BUS,
	432	PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
	433
	434	hose->region_count = 3;
	435
	436	pci_register_hose (hose);
	437	/* Mask off master abort machine checks */
	438	immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
	439	eieio ();
	440
	441	hose->last_busno = pci_hose_scan (hose);
4d75a504	442
4d75a504	443
3c74e32a WD	444	/* clear the error in the error status register */
3c74e32a WD	445	immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
4d75a504	446
3c74e32a WD	447	/* unmask master abort machine checks */
3c74e32a WD	448	immap->im_pci.pci_emr \|= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
4d75a504 WD	449	}
4d75a504 WD	450
3c74e32a	451	#endif /* CONFIG_PCI */